Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2729190	1			T1	1		T2	1		T4	24
all_values[1]	2729190	1			T1	1		T2	1		T4	24
all_values[2]	2729190	1			T1	1		T2	1		T4	24
all_values[3]	2729190	1			T1	1		T2	1		T4	24
all_values[4]	2729190	1			T1	1		T2	1		T4	24
all_values[5]	2729190	1			T1	1		T2	1		T4	24
all_values[6]	2729190	1			T1	1		T2	1		T4	24
all_values[7]	2729190	1			T1	1		T2	1		T4	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21474295

1

T1

8

T2

8

T4

192

auto[1]

359225

1

T17

54

T18

105

T19

251758

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21806354

1

T1

8

T2

8

T4

186

auto[1]

27166

1

T4

6

T23

182

T17

123

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2651994	1			T1	1		T2	1		T4	24
all_values[0]	auto[0]	auto[1]	12460	1			T23	117		T17	41		T28	39
all_values[0]	auto[1]	auto[0]	64199	1			T17	3		T18	8		T19	50224
all_values[0]	auto[1]	auto[1]	537	1			T17	1		T18	7		T19	127
all_values[1]	auto[0]	auto[0]	2710544	1			T1	1		T2	1		T4	24
all_values[1]	auto[0]	auto[1]	8643	1			T23	63		T17	40		T28	9
all_values[1]	auto[1]	auto[0]	9673	1			T17	4		T18	7		T22	2
all_values[1]	auto[1]	auto[1]	330	1			T17	7		T18	6		T19	1
all_values[2]	auto[0]	auto[0]	2705054	1			T1	1		T2	1		T4	24
all_values[2]	auto[0]	auto[1]	3086	1			T23	2		T17	7		T18	7
all_values[2]	auto[1]	auto[0]	20832	1			T17	3		T18	5		T21	2
all_values[2]	auto[1]	auto[1]	218	1			T17	3		T18	5		T19	1
all_values[3]	auto[0]	auto[0]	2674542	1			T1	1		T2	1		T4	18
all_values[3]	auto[0]	auto[1]	204	1			T4	6		T17	4		T18	8
all_values[3]	auto[1]	auto[0]	54269	1			T17	3		T18	3		T19	50348
all_values[3]	auto[1]	auto[1]	175	1			T17	1		T18	8		T19	2
all_values[4]	auto[0]	auto[0]	2664383	1			T1	1		T2	1		T4	24
all_values[4]	auto[0]	auto[1]	208	1			T17	4		T18	4		T19	1
all_values[4]	auto[1]	auto[0]	64402	1			T17	5		T18	12		T19	50348
all_values[4]	auto[1]	auto[1]	197	1			T17	2		T19	2		T21	2
all_values[5]	auto[0]	auto[0]	2670169	1			T1	1		T2	1		T4	24
all_values[5]	auto[0]	auto[1]	168	1			T17	2		T18	4		T21	2
all_values[5]	auto[1]	auto[0]	58679	1			T17	5		T18	8		T19	50349
all_values[5]	auto[1]	auto[1]	174	1			T17	3		T18	5		T19	3
all_values[6]	auto[0]	auto[0]	2662404	1			T1	1		T2	1		T4	24
all_values[6]	auto[0]	auto[1]	164	1			T17	2		T18	4		T21	2
all_values[6]	auto[1]	auto[0]	66412	1			T17	7		T18	11		T19	50349
all_values[6]	auto[1]	auto[1]	210	1			T17	2		T18	3		T19	2
all_values[7]	auto[0]	auto[0]	2710093	1			T1	1		T2	1		T4	24
all_values[7]	auto[0]	auto[1]	179	1			T17	4		T18	3		T21	1
all_values[7]	auto[1]	auto[0]	18705	1			T17	5		T18	16		T21	4
all_values[7]	auto[1]	auto[1]	213	1			T18	1		T19	2		T21	4