Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34457	1			T2	2		T8	46		T9	20
auto[SpiFlashAddrCfg]	7383	1			T4	6		T8	24		T10	6
auto[SpiFlashAddr3b]	9071	1			T4	5		T8	30		T10	4
auto[SpiFlashAddr4b]	7448	1			T4	1		T8	20		T15	21

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32953

1

T2

2

T4

12

T8

72

auto[1]

25406

1

T8

48

T10

22

T15

36

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31456

1

T2

2

T4

6

T8

48

auto[1]

26903

1

T4

6

T8

72

T10

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39190	1			T8	57		T9	20		T10	14
values[1]	1112	1			T8	1		T10	4		T15	2
values[2]	1453	1			T4	2		T8	3		T15	5
values[3]	1398	1			T4	1		T8	9		T15	9
values[4]	1479	1			T10	2		T15	1		T23	2
values[5]	1428	1			T8	4		T15	1		T23	4
values[6]	1399	1			T4	1		T8	8		T15	8
values[7]	1450	1			T8	6		T23	3		T17	3
values[8]	9450	1			T2	2		T4	8		T8	32

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28695

1

T2

2

T9

20

T10

22

auto[1]

29664

1

T4

12

T8

120

T23

119

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55028

1

T2

2

T4

12

T8

109

write

3331

1

T8

11

T10

8

T15

5

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19015

1

T4

9

T8

62

T9

20

valids[0x1]

39344

1

T2

2

T4

3

T8

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1453	1			T8	3		T15	1		T23	5
internal_process_ops[0x5a]	1529	1			T8	3		T10	2		T15	2
internal_process_ops[0x05]	20805	1			T8	8		T10	6		T15	5
internal_process_ops[0x35]	1472	1			T8	5		T15	1		T23	2
internal_process_ops[0x15]	1499	1			T8	4		T15	3		T23	1
internal_process_ops[0x03]	1011	1			T4	1		T8	2		T10	2
internal_process_ops[0x0b]	1034	1			T4	2		T10	2		T15	7
internal_process_ops[0x3b]	979	1			T4	2		T8	1		T23	2
internal_process_ops[0x6b]	1034	1			T4	1		T12	2		T15	2
internal_process_ops[0xbb]	998	1			T4	3		T8	1		T15	1
internal_process_ops[0xeb]	994	1			T4	3		T8	3		T15	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56756

1

T2

2

T4

12

T8

112

auto[1]

1603

1

T8

8

T10

8

T23

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55964

1

T2

2

T4

12

T8

110

auto[1]

2395

1

T8

10

T15

5

T23

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9729

1

T2

2

T9

20

T15

17

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5610

1

T10

6

T15

6

T28

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1902

1

T15

7

T28

1

T30

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1637

1

T10

4

T15

7

T28

1

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2369

1

T12

6

T15

11

T28

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2172

1

T10

4

T15

7

T30

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1944

1

T15

8

T28

3

T30

5

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1762

1

T15

12

T28

6

T30

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

122

1

T149

2

T22

2

T49

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

64

1

T19

1

T42

2

T48

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

88

1

T30

1

T19

1

T48

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

130

1

T10

6

T30

3

T19

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

109

1

T15

1

T19

1

T42

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

66

1

T46

1

T150

1

T49

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

92

1

T15

3

T48

1

T112

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

89

1

T10

2

T19

3

T22

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

129

1

T19

1

T46

2

T22

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T19

1

T22

2

T49

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

78

1

T22

1

T48

1

T150

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T30

4

T19

1

T46

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

107

1

T19

1

T46

2

T151

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

109

1

T28

1

T19

1

T22

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T15

1

T22

2

T150

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

90

1

T19

1

T45

2

T46

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10571

1

T8

30

T23

33

T17

25

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7701

1

T8

13

T23

16

T17

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1511

1

T4

6

T8

13

T23

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1500

1

T8

8

T23

17

T17

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1872

1

T4

5

T8

14

T23

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1839

1

T8

13

T23

10

T17

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1424

1

T4

1

T8

7

T23

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1485

1

T8

11

T23

9

T17

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T17

1

T20

2

T21

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T8

3

T20

1

T21

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

129

1

T20

3

T21

1

T69

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

118

1

T17

2

T40

1

T20

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

133

1

T8

1

T36

2

T21

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

106

1

T20

2

T21

1

T22

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

133

1

T8

2

T23

3

T39

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T23

2

T20

6

T21

8

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

96

1

T20

4

T21

2

T77

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

108

1

T8

3

T23

3

T21

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

107

1

T20

2

T21

1

T69

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

108

1

T39

5

T21

2

T152

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T23

1

T40

1

T20

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

107

1

T8

1

T17

2

T20

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T21

2

T69

2

T43

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

109

1

T8

1

T39

1

T40

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3769	1			T9	20		T15	13		T24	2
auto[0]	values[0]	valids[0x1]	14333	1			T10	14		T12	4		T15	21
auto[0]	values[1]	valids[0x1]	591	1			T10	4		T15	2		T28	1
auto[0]	values[2]	valids[0x0]	504	1			T15	4		T30	5		T19	3
auto[0]	values[2]	valids[0x1]	279	1			T15	1		T19	1		T149	2
auto[0]	values[3]	valids[0x0]	524	1			T15	3		T28	1		T30	1
auto[0]	values[3]	valids[0x1]	255	1			T15	6		T19	2		T22	1
auto[0]	values[4]	valids[0x0]	505	1			T10	2		T28	1		T30	3
auto[0]	values[4]	valids[0x1]	315	1			T15	1		T30	2		T19	4
auto[0]	values[5]	valids[0x0]	518	1			T28	1		T30	3		T19	3
auto[0]	values[5]	valids[0x1]	283	1			T15	1		T30	3		T19	2
auto[0]	values[6]	valids[0x0]	508	1			T15	4		T30	4		T19	8
auto[0]	values[6]	valids[0x1]	302	1			T15	4		T22	5		T48	1
auto[0]	values[7]	valids[0x0]	546	1			T28	3		T19	8		T153	4
auto[0]	values[7]	valids[0x1]	289	1			T28	1		T30	5		T19	6
auto[0]	values[8]	valids[0x0]	3176	1			T12	2		T15	11		T28	6
auto[0]	values[8]	valids[0x1]	1998	1			T2	2		T10	2		T15	9
auto[1]	values[0]	valids[0x0]	4022	1			T8	18		T23	21		T17	10
auto[1]	values[0]	valids[0x1]	17066	1			T8	39		T23	46		T17	24
auto[1]	values[1]	valids[0x1]	521	1			T8	1		T23	3		T17	3
auto[1]	values[2]	valids[0x0]	403	1			T8	2		T23	1		T17	2
auto[1]	values[2]	valids[0x1]	267	1			T4	2		T8	1		T40	2
auto[1]	values[3]	valids[0x0]	366	1			T8	6		T23	2		T39	3
auto[1]	values[3]	valids[0x1]	253	1			T4	1		T8	3		T17	1
auto[1]	values[4]	valids[0x0]	396	1			T23	2		T17	3		T39	2
auto[1]	values[4]	valids[0x1]	263	1			T39	2		T40	2		T20	3
auto[1]	values[5]	valids[0x0]	401	1			T8	4		T23	3		T40	3
auto[1]	values[5]	valids[0x1]	226	1			T23	1		T20	6		T21	17
auto[1]	values[6]	valids[0x0]	363	1			T4	1		T8	6		T23	2
auto[1]	values[6]	valids[0x1]	226	1			T8	2		T23	2		T40	3
auto[1]	values[7]	valids[0x0]	396	1			T8	4		T23	3		T17	3
auto[1]	values[7]	valids[0x1]	219	1			T8	2		T39	1		T40	1
auto[1]	values[8]	valids[0x0]	2618	1			T4	8		T8	22		T23	14
auto[1]	values[8]	valids[0x1]	1658	1			T8	10		T23	19		T17	2