Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3166303

1

T2

1

T4

760

T6

3376

auto[1]

27476

1

T8

121

T15

39

T23

19

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

893075

1

T2

1

T4

760

T6

3376

auto[1]

2300704

1

T8

4792

T15

6325

T23

3187

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	606594	1			T2	1		T4	280		T6	1335
auto[524288:1048575]	333043	1			T4	233		T6	155		T8	2844
auto[1048576:1572863]	387509	1			T4	2		T6	1038		T8	440
auto[1572864:2097151]	395970	1			T4	7		T6	151		T8	10
auto[2097152:2621439]	360244	1			T4	113		T6	697		T8	286
auto[2621440:3145727]	377314	1			T4	55		T8	1282		T9	7
auto[3145728:3670015]	383139	1			T4	70		T8	15		T12	3
auto[3670016:4194303]	349966	1			T8	26		T9	10		T15	41

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2333291

1

T2

1

T4

47

T6

16

auto[1]

860488

1

T4

713

T6

3360

T8

9

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2807249

1

T2

1

T4

760

T6

3376

auto[1]

386530

1

T9

513

T15

19

T23

2668

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	197005	1			T2	1		T4	280		T6	1335
auto[0]	auto[0]	auto[0:524287]	auto[1]	351968	1			T8	120		T15	2876		T17	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	88787	1			T4	233		T6	155		T8	75
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	199425	1			T8	2715		T15	2270		T23	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	106361	1			T4	2		T6	1038		T8	40
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	218801	1			T8	365		T15	513		T19	259
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	139081	1			T4	7		T6	151		T8	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	224666	1			T39	512		T40	1177		T30	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	76838	1			T4	113		T6	697		T8	20
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	226728	1			T8	266		T23	257		T17	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	72082	1			T4	55		T8	24		T12	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	246391	1			T8	1248		T15	640		T23	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	88001	1			T4	70		T8	12		T12	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	236293	1			T23	258		T17	406		T39	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	107528	1			T8	22		T9	10		T15	35
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	203247	1			T15	3		T23	1		T17	640
auto[0]	auto[1]	auto[0:524287]	auto[0]	2549	1			T9	11		T15	3		T24	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	50692	1			T30	2		T20	256		T21	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	612	1			T20	3		T21	2		T69	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39995	1			T20	2		T21	2		T42	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1469	1			T15	10		T42	1		T77	23
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	57273	1			T42	2723		T225	4		T150	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2248	1			T9	495		T39	1		T19	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	26910	1			T21	4		T46	256		T69	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1958	1			T23	4		T20	3		T21	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51211	1			T23	179		T20	87		T21	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1124	1			T9	7		T17	3		T19	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	54815	1			T17	257		T19	872		T20	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2104	1			T23	4		T39	2		T30	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53945	1			T23	2475		T21	256		T69	36
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1413	1			T19	4		T20	1		T21	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	34783	1			T21	23		T42	259		T152	312
auto[1]	auto[0]	auto[0:524287]	auto[0]	562	1			T8	7		T17	1		T28	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3271	1			T8	8		T17	4		T28	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	362	1			T8	7		T28	1		T20	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3388	1			T8	47		T20	11		T21	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	466	1			T8	12		T15	3		T19	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2730	1			T8	23		T15	23		T19	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	377	1			T30	1		T19	4		T20	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2331	1			T19	2		T20	3		T21	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	358	1			T15	4		T23	1		T17	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2725	1			T23	1		T17	3		T40	25
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	390	1			T8	10		T23	1		T17	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2037	1			T23	1		T17	1		T20	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	399	1			T8	3		T23	2		T39	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2003	1			T23	6		T39	29		T20	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	389	1			T8	4		T15	3		T23	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2259	1			T40	1		T19	3		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	78	1			T30	2		T70	3		T207	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	469	1			T30	2		T70	53		T226	10
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	87	1			T20	2		T21	2		T47	4
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	387	1			T21	14		T22	1		T70	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	106	1			T15	6		T77	7		T150	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	303	1			T150	2		T49	9		T112	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	67	1			T46	3		T69	1		T22	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	290	1			T69	4		T22	2		T112	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	54	1			T23	3		T20	1		T21	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	372	1			T23	3		T20	1		T21	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	89	1			T17	1		T19	1		T21	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	386	1			T17	1		T19	2		T21	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	65	1			T70	1		T43	2		T219	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	329	1			T70	6		T43	2		T219	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	66	1			T21	2		T42	3		T48	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	281	1			T21	2		T42	6		T48	16

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1932353	1			T2	1		T4	47		T6	16
auto[0]	auto[0]	auto[1]	850849	1			T4	713		T6	3360		T9	3
auto[0]	auto[1]	auto[0]	374194	1			T9	12		T15	13		T23	2662
auto[0]	auto[1]	auto[1]	8907	1			T9	501		T21	1		T70	2
auto[1]	auto[0]	auto[0]	23436	1			T8	112		T15	31		T23	11
auto[1]	auto[0]	auto[1]	611	1			T8	9		T15	2		T23	2
auto[1]	auto[1]	auto[0]	3308	1			T15	4		T23	6		T17	2
auto[1]	auto[1]	auto[1]	121	1			T15	2		T21	1		T46	1