Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2729190	1			T1	1		T2	1		T4	24
all_pins[1]	2729190	1			T1	1		T2	1		T4	24
all_pins[2]	2729190	1			T1	1		T2	1		T4	24
all_pins[3]	2729190	1			T1	1		T2	1		T4	24
all_pins[4]	2729190	1			T1	1		T2	1		T4	24
all_pins[5]	2729190	1			T1	1		T2	1		T4	24
all_pins[6]	2729190	1			T1	1		T2	1		T4	24
all_pins[7]	2729190	1			T1	1		T2	1		T4	24

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21764311	1			T1	8		T2	8		T4	192
values[0x1]	69209	1			T17	19		T18	35		T19	50973
transitions[0x0=>0x1]	67838	1			T17	14		T18	29		T19	50483
transitions[0x1=>0x0]	67855	1			T17	14		T18	29		T19	50483

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2728589	1			T1	1		T2	1		T4	24
all_pins[0]	values[0x1]	601	1			T17	1		T18	7		T19	139
all_pins[0]	transitions[0x0=>0x1]	399	1			T18	6		T19	139		T22	2
all_pins[0]	transitions[0x1=>0x0]	150	1			T17	6		T18	5		T19	1
all_pins[1]	values[0x0]	2728838	1			T1	1		T2	1		T4	24
all_pins[1]	values[0x1]	352	1			T17	7		T18	6		T19	1
all_pins[1]	transitions[0x0=>0x1]	289	1			T17	4		T18	5		T19	1
all_pins[1]	transitions[0x1=>0x0]	167	1			T18	4		T19	1		T22	2
all_pins[2]	values[0x0]	2728960	1			T1	1		T2	1		T4	24
all_pins[2]	values[0x1]	230	1			T17	3		T18	5		T19	1
all_pins[2]	transitions[0x0=>0x1]	183	1			T17	3		T18	3		T19	1
all_pins[2]	transitions[0x1=>0x0]	128	1			T17	1		T18	6		T19	2
all_pins[3]	values[0x0]	2729015	1			T1	1		T2	1		T4	24
all_pins[3]	values[0x1]	175	1			T17	1		T18	8		T19	2
all_pins[3]	transitions[0x0=>0x1]	130	1			T17	1		T18	8		T22	2
all_pins[3]	transitions[0x1=>0x0]	152	1			T17	2		T21	2		T32	2
all_pins[4]	values[0x0]	2728993	1			T1	1		T2	1		T4	24
all_pins[4]	values[0x1]	197	1			T17	2		T19	2		T21	2
all_pins[4]	transitions[0x0=>0x1]	148	1			T17	1		T19	1		T21	2
all_pins[4]	transitions[0x1=>0x0]	1118	1			T17	2		T18	5		T19	490
all_pins[5]	values[0x0]	2728023	1			T1	1		T2	1		T4	24
all_pins[5]	values[0x1]	1167	1			T17	3		T18	5		T19	491
all_pins[5]	transitions[0x0=>0x1]	330	1			T17	3		T18	3		T19	4
all_pins[5]	transitions[0x1=>0x0]	65437	1			T17	2		T18	1		T19	49848
all_pins[6]	values[0x0]	2662916	1			T1	1		T2	1		T4	24
all_pins[6]	values[0x1]	66274	1			T17	2		T18	3		T19	50335
all_pins[6]	transitions[0x0=>0x1]	66208	1			T17	2		T18	3		T19	50335
all_pins[6]	transitions[0x1=>0x0]	147	1			T18	1		T19	2		T21	1
all_pins[7]	values[0x0]	2728977	1			T1	1		T2	1		T4	24
all_pins[7]	values[0x1]	213	1			T18	1		T19	2		T21	4
all_pins[7]	transitions[0x0=>0x1]	151	1			T18	1		T19	2		T21	2
all_pins[7]	transitions[0x1=>0x0]	556	1			T17	1		T18	7		T19	139