Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16733

1

T2

2

T9

20

T12

6

auto[1]

11962

1

T10

22

T15

36

T28

9

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3832	1			T15	20		T24	2		T30	22
values[1]	4084	1			T15	20		T19	43		T227	10
values[2]	3089	1			T19	66		T45	2		T78	12
values[3]	3273	1			T2	2		T9	20		T15	20
values[4]	3811	1			T19	40		T148	6		T42	20
values[5]	3820	1			T10	22		T12	6		T19	26
values[6]	3019	1			T28	24		T30	20		T19	49
values[7]	3767	1			T15	20		T30	65		T19	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4096	1			T12	6		T30	24		T19	46
values[1]	3907	1			T15	20		T42	20		T228	8
values[2]	3229	1			T10	22		T30	20		T19	63
values[3]	3434	1			T2	2		T9	20		T15	20
values[4]	3053	1			T24	2		T28	24		T19	20
values[5]	3579	1			T19	46		T45	2		T58	8
values[6]	3939	1			T15	40		T19	43		T78	12
values[7]	3458	1			T30	20		T19	40		T46	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	392	1			T19	8		T22	65		T229	8
auto[0]	values[0]	values[1]	266	1			T47	8		T48	128		T166	11
auto[0]	values[0]	values[2]	274	1			T112	17		T166	13		T180	11
auto[0]	values[0]	values[3]	282	1			T30	15		T48	18		T230	10
auto[0]	values[0]	values[4]	330	1			T24	2		T150	15		T49	12
auto[0]	values[0]	values[5]	263	1			T231	10		T150	10		T49	42
auto[0]	values[0]	values[6]	252	1			T15	11		T232	2		T47	16
auto[0]	values[0]	values[7]	259	1			T42	9		T233	20		T187	13
auto[0]	values[1]	values[0]	304	1			T150	15		T194	15		T171	47
auto[0]	values[1]	values[1]	641	1			T114	36		T217	4		T34	11
auto[0]	values[1]	values[2]	232	1			T166	15		T234	12		T235	12
auto[0]	values[1]	values[3]	213	1			T15	10		T22	12		T48	12
auto[0]	values[1]	values[4]	327	1			T49	13		T236	10		T237	2
auto[0]	values[1]	values[5]	244	1			T19	15		T178	8		T22	12
auto[0]	values[1]	values[6]	303	1			T195	13		T184	13		T192	9
auto[0]	values[1]	values[7]	185	1			T19	10		T227	10		T22	17
auto[0]	values[2]	values[0]	225	1			T150	14		T172	53		T238	38
auto[0]	values[2]	values[1]	229	1			T207	18		T239	4		T183	13
auto[0]	values[2]	values[2]	203	1			T172	11		T171	16		T183	11
auto[0]	values[2]	values[3]	235	1			T166	14		T184	17		T203	21
auto[0]	values[2]	values[4]	165	1			T172	17		T166	15		T207	17
auto[0]	values[2]	values[5]	251	1			T19	12		T22	17		T240	2
auto[0]	values[2]	values[6]	241	1			T19	12		T78	12		T207	13
auto[0]	values[2]	values[7]	206	1			T19	12		T203	15		T192	32
auto[0]	values[3]	values[0]	169	1			T42	21		T241	8		T111	6
auto[0]	values[3]	values[1]	227	1			T15	7		T22	11		T194	12
auto[0]	values[3]	values[2]	312	1			T34	14		T230	7		T242	13
auto[0]	values[3]	values[3]	373	1			T2	2		T9	20		T30	11
auto[0]	values[3]	values[4]	250	1			T42	12		T211	8		T189	7
auto[0]	values[3]	values[5]	200	1			T49	10		T175	13		T192	13
auto[0]	values[3]	values[6]	198	1			T47	16		T22	8		T243	10
auto[0]	values[3]	values[7]	244	1			T48	14		T150	29		T171	8
auto[0]	values[4]	values[0]	225	1			T172	13		T207	25		T194	30
auto[0]	values[4]	values[1]	201	1			T184	11		T189	11		T235	13
auto[0]	values[4]	values[2]	278	1			T19	21		T22	13		T244	14
auto[0]	values[4]	values[3]	159	1			T148	6		T42	9		T245	10
auto[0]	values[4]	values[4]	124	1			T113	14		T171	20		T180	15
auto[0]	values[4]	values[5]	489	1			T34	200		T175	78		T192	10
auto[0]	values[4]	values[6]	364	1			T172	10		T204	12		T215	11
auto[0]	values[4]	values[7]	436	1			T112	11		T166	13		T184	14
auto[0]	values[5]	values[0]	222	1			T12	6		T150	8		T207	5
auto[0]	values[5]	values[1]	256	1			T42	11		T22	36		T112	11
auto[0]	values[5]	values[2]	302	1			T22	12		T203	7		T189	11
auto[0]	values[5]	values[3]	197	1			T19	7		T42	10		T184	17
auto[0]	values[5]	values[4]	240	1			T46	11		T119	26		T246	4
auto[0]	values[5]	values[5]	245	1			T74	4		T207	12		T247	8
auto[0]	values[5]	values[6]	481	1			T118	12		T172	10		T218	14
auto[0]	values[5]	values[7]	238	1			T149	11		T216	16		T214	10
auto[0]	values[6]	values[0]	367	1			T19	11		T184	16		T34	100
auto[0]	values[6]	values[1]	200	1			T112	16		T34	9		T175	11
auto[0]	values[6]	values[2]	134	1			T30	14		T19	16		T171	13
auto[0]	values[6]	values[3]	167	1			T22	36		T175	26		T215	21
auto[0]	values[6]	values[4]	151	1			T28	15		T248	4		T249	6
auto[0]	values[6]	values[5]	176	1			T196	8		T235	10		T187	21
auto[0]	values[6]	values[6]	202	1			T150	10		T250	2		T187	20
auto[0]	values[6]	values[7]	302	1			T151	110		T150	10		T166	10
auto[0]	values[7]	values[0]	367	1			T30	13		T46	13		T22	13
auto[0]	values[7]	values[1]	266	1			T228	8		T207	10		T251	20
auto[0]	values[7]	values[2]	165	1			T207	18		T188	13		T242	15
auto[0]	values[7]	values[3]	342	1			T30	13		T168	2		T193	14
auto[0]	values[7]	values[4]	160	1			T19	9		T46	7		T150	10
auto[0]	values[7]	values[5]	152	1			T58	8		T207	13		T175	23
auto[0]	values[7]	values[6]	333	1			T15	16		T19	8		T49	45
auto[0]	values[7]	values[7]	297	1			T30	12		T46	8		T112	13
auto[1]	values[0]	values[0]	342	1			T19	12		T22	19		T171	15
auto[1]	values[0]	values[1]	160	1			T47	12		T48	13		T166	9
auto[1]	values[0]	values[2]	111	1			T112	3		T166	7		T180	9
auto[1]	values[0]	values[3]	152	1			T30	7		T48	12		T230	10
auto[1]	values[0]	values[4]	232	1			T150	5		T49	47		T172	6
auto[1]	values[0]	values[5]	258	1			T150	55		T49	46		T172	22
auto[1]	values[0]	values[6]	133	1			T15	9		T47	4		T49	11
auto[1]	values[0]	values[7]	126	1			T42	11		T187	7		T212	7
auto[1]	values[1]	values[0]	346	1			T150	13		T194	5		T171	5
auto[1]	values[1]	values[1]	184	1			T34	9		T194	12		T187	11
auto[1]	values[1]	values[2]	165	1			T166	5		T235	8		T215	8
auto[1]	values[1]	values[3]	339	1			T15	10		T22	8		T48	54
auto[1]	values[1]	values[4]	151	1			T49	22		T212	6		T215	8
auto[1]	values[1]	values[5]	146	1			T19	8		T22	8		T150	6
auto[1]	values[1]	values[6]	187	1			T195	7		T184	8		T192	11
auto[1]	values[1]	values[7]	117	1			T19	10		T22	3		T150	6
auto[1]	values[2]	values[0]	190	1			T150	9		T172	58		T252	10
auto[1]	values[2]	values[1]	152	1			T207	8		T183	17		T190	10
auto[1]	values[2]	values[2]	168	1			T172	9		T171	14		T183	9
auto[1]	values[2]	values[3]	203	1			T166	6		T184	8		T203	19
auto[1]	values[2]	values[4]	116	1			T172	6		T166	5		T207	5
auto[1]	values[2]	values[5]	211	1			T19	11		T45	2		T22	8
auto[1]	values[2]	values[6]	183	1			T19	11		T207	10		T184	8
auto[1]	values[2]	values[7]	111	1			T19	8		T203	8		T192	16
auto[1]	values[3]	values[0]	110	1			T42	8		T34	67		T171	6
auto[1]	values[3]	values[1]	148	1			T15	13		T22	10		T194	9
auto[1]	values[3]	values[2]	202	1			T34	6		T230	13		T242	7
auto[1]	values[3]	values[3]	170	1			T30	9		T48	21		T112	23
auto[1]	values[3]	values[4]	278	1			T42	8		T189	13		T176	12
auto[1]	values[3]	values[5]	136	1			T49	24		T175	7		T192	7
auto[1]	values[3]	values[6]	190	1			T47	4		T22	12		T172	8
auto[1]	values[3]	values[7]	66	1			T48	6		T150	9		T171	12
auto[1]	values[4]	values[0]	189	1			T172	7		T207	16		T194	15
auto[1]	values[4]	values[1]	263	1			T184	12		T189	9		T235	7
auto[1]	values[4]	values[2]	179	1			T19	19		T22	14		T184	12
auto[1]	values[4]	values[3]	145	1			T42	11		T49	11		T253	56
auto[1]	values[4]	values[4]	96	1			T171	8		T180	5		T213	43
auto[1]	values[4]	values[5]	170	1			T34	6		T175	6		T192	10
auto[1]	values[4]	values[6]	233	1			T172	10		T215	17		T242	10
auto[1]	values[4]	values[7]	260	1			T112	23		T166	7		T184	6
auto[1]	values[5]	values[0]	257	1			T150	12		T207	15		T184	16
auto[1]	values[5]	values[1]	148	1			T42	9		T22	15		T112	26
auto[1]	values[5]	values[2]	276	1			T10	22		T22	39		T203	13
auto[1]	values[5]	values[3]	209	1			T19	19		T42	10		T184	9
auto[1]	values[5]	values[4]	191	1			T46	9		T183	13		T215	7
auto[1]	values[5]	values[5]	166	1			T207	13		T140	11		T192	6
auto[1]	values[5]	values[6]	166	1			T153	6		T172	10		T171	8
auto[1]	values[5]	values[7]	226	1			T149	9		T222	8		T242	9
auto[1]	values[6]	values[0]	147	1			T19	15		T184	5		T34	7
auto[1]	values[6]	values[1]	268	1			T112	9		T34	11		T175	9
auto[1]	values[6]	values[2]	127	1			T30	6		T19	7		T171	13
auto[1]	values[6]	values[3]	115	1			T22	7		T175	10		T215	8
auto[1]	values[6]	values[4]	144	1			T28	9		T51	11		T122	5
auto[1]	values[6]	values[5]	139	1			T254	18		T235	26		T187	10
auto[1]	values[6]	values[6]	123	1			T150	10		T187	5		T255	8
auto[1]	values[6]	values[7]	257	1			T150	10		T166	10		T184	9
auto[1]	values[7]	values[0]	244	1			T30	11		T46	7		T22	11
auto[1]	values[7]	values[1]	298	1			T207	10		T183	15		T190	8
auto[1]	values[7]	values[2]	101	1			T207	7		T188	7		T242	5
auto[1]	values[7]	values[3]	133	1			T30	8		T189	8		T183	10
auto[1]	values[7]	values[4]	98	1			T19	11		T46	13		T150	11
auto[1]	values[7]	values[5]	333	1			T207	10		T175	58		T230	18
auto[1]	values[7]	values[6]	350	1			T15	4		T19	12		T49	12
auto[1]	values[7]	values[7]	128	1			T30	8		T46	12		T112	7