Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	379	1			T15	1		T28	1		T30	1
auto[ReadAddrCrossIntoMailbox]	253	1			T15	1		T30	2		T19	4
auto[ReadAddrCrossOutOfMailbox]	299	1			T15	2		T19	11		T46	3
auto[ReadAddrCrossAllMailbox]	201	1			T15	2		T30	1		T19	3
auto[ReadAddrOutsideMailbox]	3377	1			T10	4		T12	6		T15	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2162

1

T10

2

T12

3

T15

7

auto[1]

2347

1

T10

2

T12

3

T15

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	779	1			T10	2		T12	4		T15	4
read_ops[0x0b]	771	1			T10	2		T15	7		T30	4
read_ops[0x3b]	729	1			T30	4		T19	17		T46	3
read_ops[0x6b]	788	1			T12	2		T15	2		T28	1
read_ops[0xbb]	730	1			T15	1		T28	1		T30	3
read_ops[0xeb]	712	1			T15	4		T28	2		T30	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T166	1		T207	1		T183	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T46	1		T166	1		T207	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T19	1		T22	3		T166	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T195	1		T172	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T119	1		T257	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T150	1		T119	1		T172	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T150	1		T258	1		T144	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T46	1		T184	1		T34	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T10	1		T12	2		T19	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T10	1		T12	2		T15	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T22	1		T150	1		T211	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T15	1		T42	2		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T19	1		T195	1		T189	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T15	1		T42	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T19	1		T243	2		T48	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T46	1		T22	1		T243	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T19	1		T22	1		T243	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T15	1		T30	1		T243	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T10	1		T15	1		T30	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T10	1		T15	3		T30	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T148	1		T119	3		T172	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T19	2		T46	1		T148	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T30	1		T119	1		T183	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T19	1		T46	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T19	1		T22	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T19	5		T46	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T22	1		T48	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T119	1		T166	1		T207	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T30	3		T19	5		T42	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T19	3		T42	3		T22	6
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T228	1		T150	1		T211	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T19	1		T46	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T47	1		T22	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T47	1		T172	1		T207	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T15	1		T19	1		T119	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T19	2		T49	1		T119	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T22	1		T243	1		T150	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T243	1		T112	2		T180	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T12	1		T15	1		T30	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T12	1		T28	1		T19	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T19	1		T148	1		T150	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T28	1		T148	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T42	1		T48	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T34	1		T180	1		T235	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T19	1		T150	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T112	1		T34	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T48	1		T150	1		T119	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T19	1		T22	1		T119	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T30	1		T19	3		T46	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T15	1		T30	2		T19	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T30	1		T46	1		T42	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T42	1		T47	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	12	1			T30	1		T217	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T19	1		T217	1		T183	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T15	1		T42	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T46	1		T22	1		T150	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T15	1		T19	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T46	1		T22	1		T166	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T15	2		T28	2		T30	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T30	1		T19	3		T22	4