Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2706	1			T2	2		T15	40		T30	42
values[1]	4218	1			T15	20		T30	41		T19	26
values[2]	3666	1			T24	2		T30	20		T19	43
values[3]	3658	1			T19	72		T22	55		T150	41
values[4]	3352	1			T10	22		T19	20		T46	20
values[5]	4289	1			T12	6		T30	24		T19	63
values[6]	3320	1			T15	20		T28	24		T19	20
values[7]	3486	1			T9	20		T19	20		T46	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3544	1			T15	20		T30	24		T19	66
values[1]	3948	1			T19	46		T42	20		T47	20
values[2]	3887	1			T15	20		T46	20		T153	6
values[3]	3857	1			T9	20		T15	20		T46	20
values[4]	3825	1			T12	6		T30	43		T19	40
values[5]	2764	1			T15	20		T24	2		T30	20
values[6]	3537	1			T2	2		T19	49		T245	10
values[7]	3333	1			T10	22		T28	24		T30	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27954

1

T2

2

T9

20

T10

14

auto[1]

741

1

T10

8

T28

1

T30

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	576	1			T15	20		T42	20		T74	4
auto[0]	values[0]	values[1]	255	1			T19	20		T118	12		T246	4
auto[0]	values[0]	values[2]	156	1			T111	6		T259	10		T257	20
auto[0]	values[0]	values[3]	331	1			T15	20		T114	36		T184	20
auto[0]	values[0]	values[4]	441	1			T30	20		T192	21		T260	6
auto[0]	values[0]	values[5]	306	1			T30	18		T166	20		T203	20
auto[0]	values[0]	values[6]	356	1			T2	2		T245	10		T178	8
auto[0]	values[0]	values[7]	218	1			T241	8		T252	6		T237	2
auto[0]	values[1]	values[0]	449	1			T49	54		T166	19		T171	30
auto[0]	values[1]	values[1]	747	1			T19	24		T47	20		T22	19
auto[0]	values[1]	values[2]	629	1			T15	20		T49	21		T172	48
auto[0]	values[1]	values[3]	467	1			T194	21		T176	55		T187	25
auto[0]	values[1]	values[4]	428	1			T30	21		T48	31		T112	45
auto[0]	values[1]	values[5]	328	1			T22	20		T166	18		T187	24
auto[0]	values[1]	values[6]	621	1			T150	20		T175	20		T235	20
auto[0]	values[1]	values[7]	441	1			T30	18		T22	20		T150	22
auto[0]	values[2]	values[0]	451	1			T19	21		T151	110		T150	20
auto[0]	values[2]	values[1]	422	1			T49	54		T207	45		T175	47
auto[0]	values[2]	values[2]	314	1			T183	30		T261	26		T235	20
auto[0]	values[2]	values[3]	488	1			T48	64		T49	34		T207	22
auto[0]	values[2]	values[4]	641	1			T49	32		T112	35		T234	12
auto[0]	values[2]	values[5]	354	1			T24	2		T19	19		T46	20
auto[0]	values[2]	values[6]	530	1			T232	2		T22	48		T256	2
auto[0]	values[2]	values[7]	363	1			T30	20		T228	8		T193	14
auto[0]	values[3]	values[0]	531	1			T19	21		T49	52		T166	20
auto[0]	values[3]	values[1]	545	1			T195	20		T172	18		T207	22
auto[0]	values[3]	values[2]	557	1			T175	167		T189	18		T183	84
auto[0]	values[3]	values[3]	581	1			T22	55		T112	32		T184	20
auto[0]	values[3]	values[4]	315	1			T171	27		T183	20		T235	49
auto[0]	values[3]	values[5]	375	1			T19	23		T150	21		T235	24
auto[0]	values[3]	values[6]	419	1			T19	25		T166	16		T207	25
auto[0]	values[3]	values[7]	239	1			T150	19		T112	35		T240	2
auto[0]	values[4]	values[0]	370	1			T172	20		T250	2		T175	83
auto[0]	values[4]	values[1]	344	1			T150	20		T211	8		T217	4
auto[0]	values[4]	values[2]	555	1			T46	17		T150	37		T175	52
auto[0]	values[4]	values[3]	548	1			T227	10		T262	14		T192	20
auto[0]	values[4]	values[4]	445	1			T42	19		T168	2		T22	43
auto[0]	values[4]	values[5]	311	1			T19	18		T172	20		T215	19
auto[0]	values[4]	values[6]	316	1			T207	20		T263	6		T264	14
auto[0]	values[4]	values[7]	382	1			T10	14		T49	34		T233	20
auto[0]	values[5]	values[0]	428	1			T30	23		T19	19		T189	20
auto[0]	values[5]	values[1]	443	1			T207	20		T34	20		T171	76
auto[0]	values[5]	values[2]	613	1			T166	20		T184	23		T34	99
auto[0]	values[5]	values[3]	680	1			T47	19		T34	20		T265	16
auto[0]	values[5]	values[4]	365	1			T12	6		T19	20		T48	19
auto[0]	values[5]	values[5]	456	1			T42	28		T231	10		T216	16
auto[0]	values[5]	values[6]	610	1			T19	22		T150	20		T113	14
auto[0]	values[5]	values[7]	600	1			T58	8		T42	38		T119	26
auto[0]	values[6]	values[0]	292	1			T149	19		T22	31		T184	22
auto[0]	values[6]	values[1]	625	1			T42	20		T22	74		T207	31
auto[0]	values[6]	values[2]	566	1			T22	50		T48	30		T150	63
auto[0]	values[6]	values[3]	192	1			T243	10		T171	28		T266	2
auto[0]	values[6]	values[4]	434	1			T46	18		T180	16		T267	20
auto[0]	values[6]	values[5]	282	1			T15	20		T49	20		T171	23
auto[0]	values[6]	values[6]	265	1			T47	20		T172	19		T185	20
auto[0]	values[6]	values[7]	581	1			T28	23		T19	19		T148	6
auto[0]	values[7]	values[0]	341	1			T48	117		T112	19		T172	19
auto[0]	values[7]	values[1]	486	1			T180	17		T50	26		T268	2
auto[0]	values[7]	values[2]	401	1			T153	6		T196	8		T112	37
auto[0]	values[7]	values[3]	483	1			T9	20		T46	20		T48	20
auto[0]	values[7]	values[4]	664	1			T19	20		T244	14		T172	63
auto[0]	values[7]	values[5]	276	1			T172	17		T207	19		T230	20
auto[0]	values[7]	values[6]	317	1			T22	19		T184	18		T269	18
auto[0]	values[7]	values[7]	409	1			T78	12		T49	27		T172	22
auto[1]	values[0]	values[0]	13	1			T45	2		T50	1		T210	1
auto[1]	values[0]	values[1]	3	1			T270	1		T271	2		-	-
auto[1]	values[0]	values[2]	4	1			T174	1		T122	2		T272	1
auto[1]	values[0]	values[3]	5	1			T174	1		T273	2		T274	1
auto[1]	values[0]	values[4]	12	1			T30	2		T255	1		T275	1
auto[1]	values[0]	values[5]	7	1			T30	2		T188	1		T276	2
auto[1]	values[0]	values[6]	19	1			T150	1		T194	3		T188	1
auto[1]	values[0]	values[7]	4	1			T252	4		-	-		-	-
auto[1]	values[1]	values[0]	25	1			T49	3		T166	1		T171	1
auto[1]	values[1]	values[1]	10	1			T19	2		T22	1		T171	1
auto[1]	values[1]	values[2]	19	1			T207	3		T176	3		T230	1
auto[1]	values[1]	values[3]	11	1			T277	1		T278	3		T279	4
auto[1]	values[1]	values[4]	6	1			T192	2		T187	2		T51	1
auto[1]	values[1]	values[5]	12	1			T166	2		T188	1		T280	2
auto[1]	values[1]	values[6]	8	1			T181	1		T281	3		T272	2
auto[1]	values[1]	values[7]	17	1			T30	2		T150	1		T188	1
auto[1]	values[2]	values[0]	12	1			T19	2		T207	1		T215	1
auto[1]	values[2]	values[1]	20	1			T49	5		T175	2		T276	1
auto[1]	values[2]	values[2]	6	1			T210	2		T282	4		-	-
auto[1]	values[2]	values[3]	13	1			T48	2		T207	1		T34	1
auto[1]	values[2]	values[4]	16	1			T49	2		T112	1		T212	2
auto[1]	values[2]	values[5]	11	1			T19	1		T22	1		T188	4
auto[1]	values[2]	values[6]	16	1			T22	1		T230	5		T283	2
auto[1]	values[2]	values[7]	9	1			T166	1		T180	2		T187	1
auto[1]	values[3]	values[0]	14	1			T19	2		T49	2		T177	1
auto[1]	values[3]	values[1]	6	1			T172	2		T207	1		T50	1
auto[1]	values[3]	values[2]	14	1			T175	4		T189	2		T183	1
auto[1]	values[3]	values[3]	20	1			T112	2		T215	3		T242	3
auto[1]	values[3]	values[4]	7	1			T171	1		T235	2		T284	3
auto[1]	values[3]	values[5]	10	1			T235	2		T276	1		T285	1
auto[1]	values[3]	values[6]	19	1			T19	1		T166	4		T207	1
auto[1]	values[3]	values[7]	6	1			T150	1		T189	1		T212	1
auto[1]	values[4]	values[0]	10	1			T175	1		T192	2		T235	2
auto[1]	values[4]	values[1]	10	1			T192	1		T283	3		T173	1
auto[1]	values[4]	values[2]	12	1			T46	3		T150	1		T175	1
auto[1]	values[4]	values[3]	9	1			T177	1		T286	1		T275	1
auto[1]	values[4]	values[4]	10	1			T42	1		T50	1		T144	1
auto[1]	values[4]	values[5]	5	1			T19	2		T215	1		T272	1
auto[1]	values[4]	values[6]	5	1			T287	2		T288	2		T289	1
auto[1]	values[4]	values[7]	20	1			T10	8		T49	1		T203	2
auto[1]	values[5]	values[0]	13	1			T30	1		T19	1		T235	2
auto[1]	values[5]	values[1]	6	1			T207	1		T171	2		T144	1
auto[1]	values[5]	values[2]	14	1			T184	2		T171	1		T192	1
auto[1]	values[5]	values[3]	13	1			T47	1		T190	3		T242	1
auto[1]	values[5]	values[4]	10	1			T48	1		T213	2		T177	2
auto[1]	values[5]	values[5]	6	1			T42	1		T166	1		T255	3
auto[1]	values[5]	values[6]	17	1			T19	1		T242	1		T290	2
auto[1]	values[5]	values[7]	15	1			T42	2		T188	1		T213	3
auto[1]	values[6]	values[0]	9	1			T149	1		T190	2		T291	1
auto[1]	values[6]	values[1]	11	1			T22	2		T184	1		T277	1
auto[1]	values[6]	values[2]	11	1			T22	1		T150	2		T257	1
auto[1]	values[6]	values[3]	3	1			T171	2		T292	1		-	-
auto[1]	values[6]	values[4]	21	1			T46	2		T180	4		T177	4
auto[1]	values[6]	values[5]	13	1			T171	4		T280	5		T278	1
auto[1]	values[6]	values[6]	4	1			T172	1		T140	1		T122	1
auto[1]	values[6]	values[7]	11	1			T28	1		T19	1		T194	1
auto[1]	values[7]	values[0]	10	1			T48	4		T112	1		T172	1
auto[1]	values[7]	values[1]	15	1			T180	3		T50	2		T200	2
auto[1]	values[7]	values[2]	16	1			T207	1		T184	2		T180	1
auto[1]	values[7]	values[3]	13	1			T194	1		T242	3		T293	3
auto[1]	values[7]	values[4]	10	1			T192	2		T277	1		T173	1
auto[1]	values[7]	values[5]	12	1			T172	3		T207	1		T254	2
auto[1]	values[7]	values[6]	15	1			T22	1		T184	3		T194	2
auto[1]	values[7]	values[7]	18	1			T49	1		T172	1		T180	1