Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	775	1			T17	11		T18	20		T19	4
all_values[1]	775	1			T17	11		T18	20		T19	4
all_values[2]	775	1			T17	11		T18	20		T19	4
all_values[3]	775	1			T17	11		T18	20		T19	4
all_values[4]	775	1			T17	11		T18	20		T19	4
all_values[5]	775	1			T17	11		T18	20		T19	4
all_values[6]	775	1			T17	11		T18	20		T19	4
all_values[7]	775	1			T17	11		T18	20		T19	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3206

1

T17

51

T18

72

T19

16

auto[1]

2994

1

T17

37

T18

88

T19

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2429

1

T17

37

T18

70

T19

10

auto[1]

3771

1

T17

51

T18

90

T19

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3536

1

T17

53

T18

102

T19

15

auto[1]

2664

1

T17

35

T18

58

T19

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	143	1			T17	3		T18	4		T19	2
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T17	1		T18	2		T21	1
all_values[0]	auto[0]	auto[1]	auto[0]	129	1			T17	2		T18	3		T19	2
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T18	4		T21	1		T22	2
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T17	2		T18	1		T21	3
all_values[0]	auto[1]	auto[1]	auto[1]	162	1			T17	3		T18	6		T21	3
all_values[1]	auto[0]	auto[0]	auto[0]	169	1			T18	5		T21	1		T22	3
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T17	1		T18	2		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	126	1			T18	3		T22	1		T32	3
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T17	4		T18	1		T21	3
all_values[1]	auto[1]	auto[0]	auto[1]	179	1			T17	4		T18	5		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	149	1			T17	2		T18	4		T21	3
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T18	3		T19	2		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T17	3		T18	1		T21	2
all_values[2]	auto[0]	auto[1]	auto[0]	116	1			T17	1		T18	2		T21	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T17	1		T18	5		T21	1
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T17	4		T18	5		T21	2
all_values[2]	auto[1]	auto[1]	auto[1]	143	1			T17	2		T18	4		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T17	5		T21	4		T22	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T17	2		T18	2		T32	2
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T17	1		T18	2		T21	4
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T18	7		T19	1		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	172	1			T17	1		T18	6		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	153	1			T17	2		T18	3		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	131	1			T17	2		T18	6		T21	4
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T17	1		T18	1		T22	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T17	3		T18	9		T21	2
all_values[4]	auto[0]	auto[1]	auto[1]	84	1			T17	1		T19	1		T33	1
all_values[4]	auto[1]	auto[0]	auto[1]	172	1			T17	2		T18	4		T19	2
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T17	2		T19	1		T21	2
all_values[5]	auto[0]	auto[0]	auto[0]	222	1			T17	4		T18	5		T21	4
all_values[5]	auto[0]	auto[1]	auto[0]	211	1			T17	2		T18	6		T19	1
all_values[5]	auto[1]	auto[0]	auto[1]	175	1			T17	2		T18	5		T21	3
all_values[5]	auto[1]	auto[1]	auto[1]	167	1			T17	3		T18	4		T19	3
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T17	5		T18	4		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T18	2		T22	1		T139	3
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T17	2		T18	5		T21	3
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T17	1		T18	2		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	165	1			T17	1		T18	4		T19	1
all_values[6]	auto[1]	auto[1]	auto[1]	171	1			T17	2		T18	3		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	137	1			T17	5		T18	2		T19	2
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T17	1		T18	2		T21	1
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T17	2		T18	11		T21	1
all_values[7]	auto[0]	auto[1]	auto[1]	93	1			T18	1		T21	2		T22	1
all_values[7]	auto[1]	auto[0]	auto[1]	169	1			T17	2		T18	1		T21	1
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T17	1		T18	3		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal