Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1796

1

T11

8

T13

12

T23

8

auto[1]

1758

1

T11

4

T13

8

T23

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1933

1

T11

7

T13

20

T23

12

auto[1]

1621

1

T11

5

T23

1

T25

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2848

1

T11

8

T13

14

T23

11

auto[1]

706

1

T11

4

T13

6

T23

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	680	1			T11	2		T13	3		T23	5
valid[1]	740	1			T11	2		T13	4		T23	2
valid[2]	746	1			T11	3		T13	1		T23	1
valid[3]	684	1			T11	4		T13	6		T23	3
valid[4]	704	1			T11	1		T13	6		T23	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	112	1			T13	1		T23	3		T17	1
auto[0]	auto[0]	valid[0]	auto[1]	144	1			T11	1		T69	1		T320	1
auto[0]	auto[0]	valid[1]	auto[0]	135	1			T11	1		T13	3		T29	2
auto[0]	auto[0]	valid[1]	auto[1]	179	1			T11	1		T27	1		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	121	1			T28	1		T29	1		T31	1
auto[0]	auto[0]	valid[2]	auto[1]	169	1			T11	1		T25	1		T27	1
auto[0]	auto[0]	valid[3]	auto[0]	107	1			T13	1		T23	2		T17	1
auto[0]	auto[0]	valid[3]	auto[1]	166	1			T11	1		T27	1		T19	2
auto[0]	auto[0]	valid[4]	auto[0]	126	1			T13	3		T23	1		T17	1
auto[0]	auto[0]	valid[4]	auto[1]	172	1			T11	1		T19	1		T54	2
auto[0]	auto[1]	valid[0]	auto[0]	128	1			T23	2		T17	3		T28	1
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T27	1		T54	1		T320	1
auto[0]	auto[1]	valid[1]	auto[0]	117	1			T23	1		T17	1		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	183	1			T23	1		T25	1		T56	1
auto[0]	auto[1]	valid[2]	auto[0]	131	1			T11	2		T13	1		T23	1
auto[0]	auto[1]	valid[2]	auto[1]	157	1			T25	1		T28	2		T59	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T13	3		T17	1		T28	1
auto[0]	auto[1]	valid[3]	auto[1]	145	1			T25	1		T321	4		T42	1
auto[0]	auto[1]	valid[4]	auto[0]	130	1			T13	2		T28	1		T29	3
auto[0]	auto[1]	valid[4]	auto[1]	152	1			T25	1		T26	1		T27	1
auto[1]	auto[0]	valid[0]	auto[0]	80	1			T11	1		T13	2		T17	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T28	2		T19	1		T21	1
auto[1]	auto[0]	valid[2]	auto[0]	85	1			T28	1		T19	1		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T11	1		T13	1		T23	1
auto[1]	auto[0]	valid[4]	auto[0]	57	1			T13	1		T23	1		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	62	1			T31	1		T20	4		T56	2
auto[1]	auto[1]	valid[1]	auto[0]	55	1			T13	1		T28	2		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	83	1			T31	1		T19	1		T20	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T11	2		T13	1		T28	1
auto[1]	auto[1]	valid[4]	auto[0]	67	1			T29	2		T31	1		T19	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal