Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48718

1

T11

177

T13

429

T23

231

auto[1]

16564

1

T11

58

T23

36

T25

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47649

1

T11

154

T13

305

T23

181

auto[1]

17633

1

T11

81

T13

124

T23

86

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33555	1			T11	126		T13	208		T23	139
others[1]	5582	1			T11	17		T13	53		T23	21
others[2]	5474	1			T11	20		T13	35		T23	21
others[3]	6301	1			T11	11		T13	40		T23	27
interest[1]	3570	1			T11	13		T13	24		T23	21
interest[4]	21893	1			T11	82		T13	142		T23	95
interest[64]	10800	1			T11	48		T13	69		T23	38

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15866	1			T11	52		T13	151		T23	80
auto[0]	auto[0]	others[1]	2618	1			T11	8		T13	41		T23	10
auto[0]	auto[0]	others[2]	2593	1			T11	7		T13	25		T23	13
auto[0]	auto[0]	others[3]	3054	1			T11	4		T13	24		T23	12
auto[0]	auto[0]	interest[1]	1751	1			T11	5		T13	14		T23	9
auto[0]	auto[0]	interest[4]	10260	1			T11	33		T13	105		T23	55
auto[0]	auto[0]	interest[64]	5203	1			T11	20		T13	50		T23	21
auto[0]	auto[1]	others[0]	8596	1			T11	34		T23	18		T25	5
auto[0]	auto[1]	others[1]	1439	1			T11	3		T23	3		T28	4
auto[0]	auto[1]	others[2]	1402	1			T11	4		T23	1		T28	6
auto[0]	auto[1]	others[3]	1547	1			T11	3		T23	4		T28	5
auto[0]	auto[1]	interest[1]	881	1			T11	3		T23	4		T28	3
auto[0]	auto[1]	interest[4]	5658	1			T11	21		T23	11		T25	5
auto[0]	auto[1]	interest[64]	2699	1			T11	11		T23	6		T28	12
auto[1]	auto[0]	others[0]	9093	1			T11	40		T13	57		T23	41
auto[1]	auto[0]	others[1]	1525	1			T11	6		T13	12		T23	8
auto[1]	auto[0]	others[2]	1479	1			T11	9		T13	10		T23	7
auto[1]	auto[0]	others[3]	1700	1			T11	4		T13	16		T23	11
auto[1]	auto[0]	interest[1]	938	1			T11	5		T13	10		T23	8
auto[1]	auto[0]	interest[4]	5975	1			T11	28		T13	37		T23	29
auto[1]	auto[0]	interest[64]	2898	1			T11	17		T13	19		T23	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal