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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1131
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T132 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1816963076 Jul 28 05:21:38 PM PDT 24 Jul 28 05:21:40 PM PDT 24 1244313037 ps
T1035 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1020384498 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:25 PM PDT 24 720803254 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3947053135 Jul 28 05:21:27 PM PDT 24 Jul 28 05:21:28 PM PDT 24 17643720 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1838848537 Jul 28 05:21:20 PM PDT 24 Jul 28 05:21:22 PM PDT 24 93860445 ps
T134 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2601298620 Jul 28 05:21:45 PM PDT 24 Jul 28 05:21:49 PM PDT 24 793794044 ps
T102 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.786508991 Jul 28 05:21:11 PM PDT 24 Jul 28 05:21:13 PM PDT 24 86903003 ps
T135 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2096458244 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:35 PM PDT 24 202361772 ps
T1037 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1836858594 Jul 28 05:21:49 PM PDT 24 Jul 28 05:21:50 PM PDT 24 121642655 ps
T1038 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3793282844 Jul 28 05:21:50 PM PDT 24 Jul 28 05:21:55 PM PDT 24 58604234 ps
T84 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3707001630 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:37 PM PDT 24 125059203 ps
T155 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3695870271 Jul 28 05:21:25 PM PDT 24 Jul 28 05:21:32 PM PDT 24 204158262 ps
T162 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3088929744 Jul 28 05:21:44 PM PDT 24 Jul 28 05:21:51 PM PDT 24 557649932 ps
T1039 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4289747791 Jul 28 05:21:53 PM PDT 24 Jul 28 05:21:54 PM PDT 24 41323195 ps
T1040 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.28457074 Jul 28 05:21:42 PM PDT 24 Jul 28 05:21:43 PM PDT 24 134569108 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1763450059 Jul 28 05:21:26 PM PDT 24 Jul 28 05:21:34 PM PDT 24 281085109 ps
T136 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1164207032 Jul 28 05:21:46 PM PDT 24 Jul 28 05:21:55 PM PDT 24 3709266172 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.832746053 Jul 28 05:21:26 PM PDT 24 Jul 28 05:21:28 PM PDT 24 62232943 ps
T154 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3283982487 Jul 28 05:21:47 PM PDT 24 Jul 28 05:21:55 PM PDT 24 511343639 ps
T103 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.682728716 Jul 28 05:21:39 PM PDT 24 Jul 28 05:21:40 PM PDT 24 188145416 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3006376492 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:21 PM PDT 24 70867258 ps
T104 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.256225669 Jul 28 05:21:34 PM PDT 24 Jul 28 05:21:35 PM PDT 24 43475207 ps
T1044 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1545577504 Jul 28 05:21:52 PM PDT 24 Jul 28 05:21:52 PM PDT 24 24870741 ps
T137 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1119392648 Jul 28 05:21:24 PM PDT 24 Jul 28 05:21:25 PM PDT 24 99690824 ps
T1045 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2610334152 Jul 28 05:21:45 PM PDT 24 Jul 28 05:21:46 PM PDT 24 14732042 ps
T1046 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4265137686 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:21 PM PDT 24 205940240 ps
T105 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2433366265 Jul 28 05:21:18 PM PDT 24 Jul 28 05:21:19 PM PDT 24 30397091 ps
T1047 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3415676679 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:34 PM PDT 24 278382612 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3409155893 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:34 PM PDT 24 46583008 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.261140571 Jul 28 05:21:17 PM PDT 24 Jul 28 05:21:24 PM PDT 24 495911123 ps
T73 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1610823543 Jul 28 05:21:20 PM PDT 24 Jul 28 05:21:21 PM PDT 24 19606544 ps
T138 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4006935809 Jul 28 05:21:34 PM PDT 24 Jul 28 05:21:38 PM PDT 24 822482181 ps
T87 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2206229123 Jul 28 05:21:27 PM PDT 24 Jul 28 05:21:31 PM PDT 24 122296760 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2177188133 Jul 28 05:21:18 PM PDT 24 Jul 28 05:21:31 PM PDT 24 2418818819 ps
T160 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4025727658 Jul 28 05:21:18 PM PDT 24 Jul 28 05:21:28 PM PDT 24 1562936566 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.464846590 Jul 28 05:21:25 PM PDT 24 Jul 28 05:21:27 PM PDT 24 24854803 ps
T1052 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1757413091 Jul 28 05:21:41 PM PDT 24 Jul 28 05:21:42 PM PDT 24 41308565 ps
T1053 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3665457599 Jul 28 05:21:20 PM PDT 24 Jul 28 05:21:21 PM PDT 24 13643896 ps
T88 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1066659160 Jul 28 05:21:38 PM PDT 24 Jul 28 05:21:42 PM PDT 24 177027582 ps
T1054 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.119971832 Jul 28 05:21:44 PM PDT 24 Jul 28 05:21:45 PM PDT 24 11592546 ps
T1055 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1877282442 Jul 28 05:21:44 PM PDT 24 Jul 28 05:21:47 PM PDT 24 96347155 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.156931064 Jul 28 05:21:40 PM PDT 24 Jul 28 05:21:41 PM PDT 24 28098510 ps
T1057 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2746496360 Jul 28 05:21:49 PM PDT 24 Jul 28 05:21:51 PM PDT 24 46791551 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.342395130 Jul 28 05:21:17 PM PDT 24 Jul 28 05:21:18 PM PDT 24 26484533 ps
T106 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3330339266 Jul 28 05:21:13 PM PDT 24 Jul 28 05:21:35 PM PDT 24 5064737541 ps
T1059 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2934546915 Jul 28 05:21:34 PM PDT 24 Jul 28 05:21:36 PM PDT 24 144643069 ps
T1060 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2474312521 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:51 PM PDT 24 15323177 ps
T85 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2931666446 Jul 28 05:21:45 PM PDT 24 Jul 28 05:21:47 PM PDT 24 46436468 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.93899668 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:23 PM PDT 24 116839685 ps
T1062 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3107811448 Jul 28 05:21:28 PM PDT 24 Jul 28 05:21:29 PM PDT 24 32759032 ps
T107 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.30731463 Jul 28 05:21:47 PM PDT 24 Jul 28 05:21:48 PM PDT 24 38803734 ps
T90 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1210242386 Jul 28 05:21:17 PM PDT 24 Jul 28 05:21:21 PM PDT 24 346748335 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3348336176 Jul 28 05:21:45 PM PDT 24 Jul 28 05:22:02 PM PDT 24 2187579455 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.218272464 Jul 28 05:21:21 PM PDT 24 Jul 28 05:21:23 PM PDT 24 217859833 ps
T163 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2263426704 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:46 PM PDT 24 774705210 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2761992815 Jul 28 05:21:22 PM PDT 24 Jul 28 05:21:30 PM PDT 24 941178528 ps
T1063 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.609256468 Jul 28 05:21:50 PM PDT 24 Jul 28 05:21:54 PM PDT 24 159276137 ps
T1064 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2284337168 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:53 PM PDT 24 95252923 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.373951834 Jul 28 05:21:34 PM PDT 24 Jul 28 05:21:36 PM PDT 24 74623888 ps
T1066 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2142358154 Jul 28 05:21:26 PM PDT 24 Jul 28 05:21:31 PM PDT 24 911761914 ps
T92 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4085597870 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:22 PM PDT 24 83065460 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.750934258 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:38 PM PDT 24 3183786831 ps
T1068 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3513008202 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:52 PM PDT 24 48970446 ps
T1069 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.824214824 Jul 28 05:21:26 PM PDT 24 Jul 28 05:21:29 PM PDT 24 774147262 ps
T1070 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2458022085 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:52 PM PDT 24 21331412 ps
T1071 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.133568845 Jul 28 05:21:50 PM PDT 24 Jul 28 05:21:53 PM PDT 24 104679703 ps
T1072 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3367221583 Jul 28 05:21:49 PM PDT 24 Jul 28 05:21:50 PM PDT 24 68350553 ps
T1073 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2317333349 Jul 28 05:21:47 PM PDT 24 Jul 28 05:21:48 PM PDT 24 27306653 ps
T1074 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.369641683 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:52 PM PDT 24 13524797 ps
T91 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.352396791 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:54 PM PDT 24 106750911 ps
T1075 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2060411527 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:34 PM PDT 24 16227413 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.361120165 Jul 28 05:21:27 PM PDT 24 Jul 28 05:21:30 PM PDT 24 87547513 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.470188612 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:34 PM PDT 24 14517918 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1920255620 Jul 28 05:21:24 PM PDT 24 Jul 28 05:21:30 PM PDT 24 2580102066 ps
T1079 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1453585500 Jul 28 05:21:49 PM PDT 24 Jul 28 05:21:50 PM PDT 24 39366621 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.660720438 Jul 28 05:21:46 PM PDT 24 Jul 28 05:21:50 PM PDT 24 106914280 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3797914288 Jul 28 05:21:16 PM PDT 24 Jul 28 05:21:17 PM PDT 24 54375979 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2259661166 Jul 28 05:21:21 PM PDT 24 Jul 28 05:21:21 PM PDT 24 39756214 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2605511511 Jul 28 05:21:46 PM PDT 24 Jul 28 05:21:48 PM PDT 24 71593305 ps
T1084 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4263447625 Jul 28 05:21:49 PM PDT 24 Jul 28 05:21:50 PM PDT 24 36621675 ps
T1085 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3577083428 Jul 28 05:21:15 PM PDT 24 Jul 28 05:21:17 PM PDT 24 182153980 ps
T1086 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2124794739 Jul 28 05:21:24 PM PDT 24 Jul 28 05:21:26 PM PDT 24 99606635 ps
T1087 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3202204793 Jul 28 05:21:25 PM PDT 24 Jul 28 05:21:27 PM PDT 24 56918802 ps
T1088 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2414079379 Jul 28 05:21:47 PM PDT 24 Jul 28 05:21:48 PM PDT 24 71561973 ps
T1089 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3676908800 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:37 PM PDT 24 136149900 ps
T1090 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2797778833 Jul 28 05:21:15 PM PDT 24 Jul 28 05:21:19 PM PDT 24 626974868 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.818839065 Jul 28 05:21:31 PM PDT 24 Jul 28 05:21:32 PM PDT 24 31655371 ps
T1092 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.369833321 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:41 PM PDT 24 591301172 ps
T158 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3788170105 Jul 28 05:21:38 PM PDT 24 Jul 28 05:21:53 PM PDT 24 3585255376 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3989247380 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:35 PM PDT 24 4575388656 ps
T1094 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2612299083 Jul 28 05:21:31 PM PDT 24 Jul 28 05:21:33 PM PDT 24 44647457 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2046200081 Jul 28 05:21:29 PM PDT 24 Jul 28 05:21:30 PM PDT 24 69386715 ps
T1096 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2920262608 Jul 28 05:21:26 PM PDT 24 Jul 28 05:21:29 PM PDT 24 114054330 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4095202342 Jul 28 05:21:17 PM PDT 24 Jul 28 05:21:19 PM PDT 24 116446767 ps
T1098 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3999277378 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:35 PM PDT 24 1198061274 ps
T1099 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2214074079 Jul 28 05:21:50 PM PDT 24 Jul 28 05:21:51 PM PDT 24 24564672 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1066579255 Jul 28 05:21:27 PM PDT 24 Jul 28 05:21:41 PM PDT 24 212946636 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.921325044 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:33 PM PDT 24 14626005 ps
T1101 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1140125702 Jul 28 05:21:39 PM PDT 24 Jul 28 05:21:40 PM PDT 24 155046690 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3815333909 Jul 28 05:21:12 PM PDT 24 Jul 28 05:21:14 PM PDT 24 244571699 ps
T1103 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3527530229 Jul 28 05:21:39 PM PDT 24 Jul 28 05:21:43 PM PDT 24 182332144 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.564358803 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:26 PM PDT 24 1018570066 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.702993319 Jul 28 05:21:19 PM PDT 24 Jul 28 05:21:20 PM PDT 24 12028573 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3224536318 Jul 28 05:21:39 PM PDT 24 Jul 28 05:21:40 PM PDT 24 95606904 ps
T1107 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2639031859 Jul 28 05:21:25 PM PDT 24 Jul 28 05:21:29 PM PDT 24 120148826 ps
T1108 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4173899735 Jul 28 05:21:33 PM PDT 24 Jul 28 05:21:35 PM PDT 24 68613344 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2015161043 Jul 28 05:21:44 PM PDT 24 Jul 28 05:21:48 PM PDT 24 460619894 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3412036555 Jul 28 05:21:27 PM PDT 24 Jul 28 05:22:03 PM PDT 24 1050363884 ps
T1111 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3800745131 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:34 PM PDT 24 58546434 ps
T1112 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.30199545 Jul 28 05:21:50 PM PDT 24 Jul 28 05:21:51 PM PDT 24 95483802 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.697957101 Jul 28 05:21:12 PM PDT 24 Jul 28 05:21:15 PM PDT 24 229270992 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1372045231 Jul 28 05:21:46 PM PDT 24 Jul 28 05:21:50 PM PDT 24 57553456 ps
T159 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.913629998 Jul 28 05:21:31 PM PDT 24 Jul 28 05:21:47 PM PDT 24 2243017408 ps
T1115 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1048918503 Jul 28 05:21:49 PM PDT 24 Jul 28 05:21:50 PM PDT 24 30265983 ps
T1116 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1144428900 Jul 28 05:21:46 PM PDT 24 Jul 28 05:21:47 PM PDT 24 23367950 ps
T1117 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1678919605 Jul 28 05:21:18 PM PDT 24 Jul 28 05:21:21 PM PDT 24 156377781 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.304157365 Jul 28 05:21:18 PM PDT 24 Jul 28 05:21:46 PM PDT 24 4824721840 ps
T161 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.950842718 Jul 28 05:21:27 PM PDT 24 Jul 28 05:21:46 PM PDT 24 2633207894 ps
T1119 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.534579356 Jul 28 05:21:48 PM PDT 24 Jul 28 05:21:51 PM PDT 24 129182693 ps
T1120 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3185344041 Jul 28 05:21:46 PM PDT 24 Jul 28 05:21:47 PM PDT 24 16432129 ps
T1121 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.751201814 Jul 28 05:21:44 PM PDT 24 Jul 28 05:21:46 PM PDT 24 136319412 ps
T1122 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2944602618 Jul 28 05:21:32 PM PDT 24 Jul 28 05:21:35 PM PDT 24 79301567 ps
T157 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1688143050 Jul 28 05:21:38 PM PDT 24 Jul 28 05:21:57 PM PDT 24 301267219 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1359681607 Jul 28 05:21:20 PM PDT 24 Jul 28 05:21:23 PM PDT 24 486600867 ps
T1124 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2917632515 Jul 28 05:21:41 PM PDT 24 Jul 28 05:21:42 PM PDT 24 57249799 ps
T1125 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1080738935 Jul 28 05:21:40 PM PDT 24 Jul 28 05:21:44 PM PDT 24 123214351 ps
T1126 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2877511257 Jul 28 05:21:48 PM PDT 24 Jul 28 05:21:50 PM PDT 24 52404404 ps
T1127 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.746879052 Jul 28 05:21:51 PM PDT 24 Jul 28 05:21:52 PM PDT 24 15073590 ps
T1128 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1171367466 Jul 28 05:21:52 PM PDT 24 Jul 28 05:21:53 PM PDT 24 11042050 ps
T1129 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3335891380 Jul 28 05:21:27 PM PDT 24 Jul 28 05:21:35 PM PDT 24 1277580991 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3510872007 Jul 28 05:21:41 PM PDT 24 Jul 28 05:21:43 PM PDT 24 191679560 ps
T1131 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4029561267 Jul 28 05:21:20 PM PDT 24 Jul 28 05:21:22 PM PDT 24 97167537 ps

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2438450727
Short name T8
Test name
Test status
Simulation time 87666002591 ps
CPU time 152.02 seconds
Started Jul 28 05:34:49 PM PDT 24
Finished Jul 28 05:37:21 PM PDT 24
Peak memory 252156 kb
Host smart-9231a5ff-4808-47a8-91df-ed12f3e56111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438450727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2438450727
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4056724375
Short name T19
Test name
Test status
Simulation time 66650987239 ps
CPU time 667.65 seconds
Started Jul 28 05:35:21 PM PDT 24
Finished Jul 28 05:46:29 PM PDT 24
Peak memory 265100 kb
Host smart-b0431183-b026-4465-8bf9-0d4eaabdedc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056724375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4056724375
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2554240394
Short name T17
Test name
Test status
Simulation time 5864219006 ps
CPU time 33.3 seconds
Started Jul 28 05:34:34 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 252400 kb
Host smart-1ec31f04-aaac-4d34-80af-771b4f2cecdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554240394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2554240394
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4117914204
Short name T95
Test name
Test status
Simulation time 396831653 ps
CPU time 2.74 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 218132 kb
Host smart-8d8ab7b8-859e-4a3f-8504-bfe00a36fd0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117914204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4117914204
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3418203859
Short name T21
Test name
Test status
Simulation time 20852870203 ps
CPU time 286.42 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 267840 kb
Host smart-4aaafe85-c1bb-45c2-8650-aea21941e141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418203859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3418203859
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.489010556
Short name T15
Test name
Test status
Simulation time 84774719212 ps
CPU time 148.63 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:35:47 PM PDT 24
Peak memory 240044 kb
Host smart-738bc58c-8e45-4516-ade9-f6f66ff0aee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489010556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.489010556
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1885626179
Short name T64
Test name
Test status
Simulation time 116184983 ps
CPU time 0.73 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:32:09 PM PDT 24
Peak memory 216124 kb
Host smart-18eb7b2e-234c-47d5-9478-183ac26e0e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885626179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1885626179
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2504561582
Short name T172
Test name
Test status
Simulation time 39861224571 ps
CPU time 108.28 seconds
Started Jul 28 05:34:08 PM PDT 24
Finished Jul 28 05:35:57 PM PDT 24
Peak memory 271356 kb
Host smart-7626a2a0-1185-4e27-b51f-d2982ca2f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504561582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2504561582
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1705727979
Short name T207
Test name
Test status
Simulation time 83991793339 ps
CPU time 422.99 seconds
Started Jul 28 05:34:29 PM PDT 24
Finished Jul 28 05:41:32 PM PDT 24
Peak memory 265280 kb
Host smart-7861866e-2e2d-4e96-958d-21d7bc21cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705727979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1705727979
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1001658050
Short name T184
Test name
Test status
Simulation time 737724702269 ps
CPU time 981.92 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:50:15 PM PDT 24
Peak memory 273176 kb
Host smart-a3054383-0b46-4bf8-bea7-e0e5f3fd9174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001658050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1001658050
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3655302994
Short name T79
Test name
Test status
Simulation time 3197637945 ps
CPU time 15.35 seconds
Started Jul 28 05:21:17 PM PDT 24
Finished Jul 28 05:21:33 PM PDT 24
Peak memory 216364 kb
Host smart-2ba0fab7-64ef-4114-8188-11e1bbf4e2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655302994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3655302994
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4170252705
Short name T235
Test name
Test status
Simulation time 23239694747 ps
CPU time 191.57 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:36:09 PM PDT 24
Peak memory 257536 kb
Host smart-b70aab8f-91a4-48ee-a232-da4574936d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170252705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4170252705
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2753150709
Short name T14
Test name
Test status
Simulation time 172143176 ps
CPU time 1.14 seconds
Started Jul 28 05:32:22 PM PDT 24
Finished Jul 28 05:32:23 PM PDT 24
Peak memory 236428 kb
Host smart-038e184b-ee43-4b9a-ac15-01699a52f7c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753150709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2753150709
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3979141168
Short name T22
Test name
Test status
Simulation time 328852813617 ps
CPU time 610.02 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:43:39 PM PDT 24
Peak memory 263488 kb
Host smart-ed050091-d8e2-4a36-83cd-94cf924d21e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979141168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3979141168
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2515934913
Short name T4
Test name
Test status
Simulation time 995105093 ps
CPU time 14.72 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:36 PM PDT 24
Peak memory 233856 kb
Host smart-ec997daf-44a9-4567-b8a3-1beb83471a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515934913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2515934913
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3322400997
Short name T180
Test name
Test status
Simulation time 135441581308 ps
CPU time 283.3 seconds
Started Jul 28 05:32:27 PM PDT 24
Finished Jul 28 05:37:10 PM PDT 24
Peak memory 266560 kb
Host smart-8237346d-c1f4-4cef-92de-18ee41c6f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322400997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3322400997
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3473429050
Short name T34
Test name
Test status
Simulation time 19021002656 ps
CPU time 103.86 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:35:46 PM PDT 24
Peak memory 265784 kb
Host smart-d34053aa-9ef4-4107-897c-98422a84c346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473429050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3473429050
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2000993810
Short name T99
Test name
Test status
Simulation time 411928214 ps
CPU time 2.17 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 215400 kb
Host smart-7665c132-a300-4307-b623-ea52e50be2d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000993810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2000993810
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.127647913
Short name T188
Test name
Test status
Simulation time 74897859787 ps
CPU time 519.71 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:43:57 PM PDT 24
Peak memory 266144 kb
Host smart-708954ad-4d92-4f39-a2f5-a582140531d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127647913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.127647913
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3707001630
Short name T84
Test name
Test status
Simulation time 125059203 ps
CPU time 4.44 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:37 PM PDT 24
Peak memory 215912 kb
Host smart-a89e1e28-8b83-4d6c-ac2c-90653ebfde98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707001630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3707001630
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.662277866
Short name T42
Test name
Test status
Simulation time 105186814577 ps
CPU time 240.43 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:39:03 PM PDT 24
Peak memory 253764 kb
Host smart-81b660e4-c601-46e1-82d4-4f5709109734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662277866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.662277866
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1321954433
Short name T150
Test name
Test status
Simulation time 41476092162 ps
CPU time 316.66 seconds
Started Jul 28 05:32:31 PM PDT 24
Finished Jul 28 05:37:48 PM PDT 24
Peak memory 256908 kb
Host smart-e442b1d2-2a6a-41bc-9495-6e04ccebe599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321954433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1321954433
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1050389663
Short name T51
Test name
Test status
Simulation time 44566550597 ps
CPU time 510.43 seconds
Started Jul 28 05:33:01 PM PDT 24
Finished Jul 28 05:41:31 PM PDT 24
Peak memory 273960 kb
Host smart-4f161cb7-4099-45a5-93dd-40043d162af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050389663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1050389663
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.330849428
Short name T29
Test name
Test status
Simulation time 7096534785 ps
CPU time 27.68 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 216432 kb
Host smart-55ee6341-8a12-497e-a02e-3b4539e852d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330849428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.330849428
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3836662472
Short name T242
Test name
Test status
Simulation time 521128014602 ps
CPU time 295.67 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:40:22 PM PDT 24
Peak memory 271040 kb
Host smart-03bbe393-b5bf-4537-bbb2-ba4e4609293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836662472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3836662472
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4000653937
Short name T275
Test name
Test status
Simulation time 5655603670 ps
CPU time 117.72 seconds
Started Jul 28 05:34:20 PM PDT 24
Finished Jul 28 05:36:18 PM PDT 24
Peak memory 250280 kb
Host smart-e0aab3fd-4cba-44a0-b33e-e54c8ed946ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000653937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4000653937
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2692130333
Short name T200
Test name
Test status
Simulation time 77885377243 ps
CPU time 195.28 seconds
Started Jul 28 05:34:50 PM PDT 24
Finished Jul 28 05:38:05 PM PDT 24
Peak memory 273708 kb
Host smart-53c6744c-7c70-4a28-b2d5-5b4a7c941068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692130333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2692130333
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1036251652
Short name T60
Test name
Test status
Simulation time 15187264 ps
CPU time 0.75 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:32:55 PM PDT 24
Peak memory 205528 kb
Host smart-7753961c-eda2-4663-a98e-a9b8ddeb7d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036251652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1036251652
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2449827360
Short name T305
Test name
Test status
Simulation time 5034828562 ps
CPU time 32.45 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 216632 kb
Host smart-a4cdd4b1-d312-4a60-b6d8-2733bb57e08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449827360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2449827360
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1831940588
Short name T838
Test name
Test status
Simulation time 198588780323 ps
CPU time 371.46 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:38:58 PM PDT 24
Peak memory 272724 kb
Host smart-854d621d-a013-4597-9528-7130d3d8211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831940588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1831940588
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.251293897
Short name T289
Test name
Test status
Simulation time 14561879650 ps
CPU time 207.39 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:35:36 PM PDT 24
Peak memory 268924 kb
Host smart-6076aced-e5b3-477b-b70c-498461c2ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251293897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.251293897
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1151458620
Short name T203
Test name
Test status
Simulation time 33480017805 ps
CPU time 116.17 seconds
Started Jul 28 05:34:04 PM PDT 24
Finished Jul 28 05:36:01 PM PDT 24
Peak memory 253640 kb
Host smart-9f020857-9f98-4390-b60c-3485ffb40774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151458620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1151458620
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3472384098
Short name T174
Test name
Test status
Simulation time 88965423523 ps
CPU time 439.4 seconds
Started Jul 28 05:34:51 PM PDT 24
Finished Jul 28 05:42:11 PM PDT 24
Peak memory 257240 kb
Host smart-025b326a-877b-4721-a803-6decaa8a48df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472384098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3472384098
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1688143050
Short name T157
Test name
Test status
Simulation time 301267219 ps
CPU time 18.61 seconds
Started Jul 28 05:21:38 PM PDT 24
Finished Jul 28 05:21:57 PM PDT 24
Peak memory 215420 kb
Host smart-cbfd0163-790e-4ded-8ac3-8ac1c6b56854
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688143050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1688143050
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2770609638
Short name T271
Test name
Test status
Simulation time 58569502099 ps
CPU time 428.65 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:39:25 PM PDT 24
Peak memory 265736 kb
Host smart-93dcfe6c-3ef6-4055-93ad-a827d111016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770609638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2770609638
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2066218315
Short name T43
Test name
Test status
Simulation time 49708741973 ps
CPU time 117.85 seconds
Started Jul 28 05:34:08 PM PDT 24
Finished Jul 28 05:36:06 PM PDT 24
Peak memory 256488 kb
Host smart-056e4a74-4599-4a39-9a65-2fd3570fc563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066218315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2066218315
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.622065640
Short name T75
Test name
Test status
Simulation time 121166692 ps
CPU time 2.91 seconds
Started Jul 28 05:33:55 PM PDT 24
Finished Jul 28 05:33:59 PM PDT 24
Peak memory 232816 kb
Host smart-92a50c02-71a4-4c6d-b063-ecad5cabe338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622065640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.622065640
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2206229123
Short name T87
Test name
Test status
Simulation time 122296760 ps
CPU time 3.12 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:31 PM PDT 24
Peak memory 215596 kb
Host smart-c2ff115d-7604-4216-b522-4a9ffd42a15a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206229123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
206229123
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3993644743
Short name T93
Test name
Test status
Simulation time 2269063883 ps
CPU time 13.88 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:59 PM PDT 24
Peak memory 223700 kb
Host smart-45ce99cd-9b59-4096-97ed-6bc807c56b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993644743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3993644743
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1724607070
Short name T299
Test name
Test status
Simulation time 1900853790 ps
CPU time 27.06 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:37 PM PDT 24
Peak memory 233172 kb
Host smart-29e88e99-ea06-4a93-996d-226d4a8384b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724607070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1724607070
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.810355151
Short name T123
Test name
Test status
Simulation time 146942834479 ps
CPU time 398.78 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:38:56 PM PDT 24
Peak memory 282844 kb
Host smart-0e23f338-faff-4719-8367-9aa542defc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810355151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.810355151
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4172916647
Short name T37
Test name
Test status
Simulation time 60227934761 ps
CPU time 390.87 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:38:39 PM PDT 24
Peak memory 270932 kb
Host smart-14356b53-f132-41b8-bb24-2b2cf5071063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172916647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4172916647
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.913629998
Short name T159
Test name
Test status
Simulation time 2243017408 ps
CPU time 14.98 seconds
Started Jul 28 05:21:31 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 215576 kb
Host smart-fd3612d0-d487-4c2e-a1f4-bd8d8cec1112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913629998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.913629998
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.47226976
Short name T272
Test name
Test status
Simulation time 25802306789 ps
CPU time 195.09 seconds
Started Jul 28 05:32:53 PM PDT 24
Finished Jul 28 05:36:08 PM PDT 24
Peak memory 252528 kb
Host smart-e9e4a524-1a2f-4078-a44a-c32b58792a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47226976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.47226976
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2798057529
Short name T738
Test name
Test status
Simulation time 35916706934 ps
CPU time 128.43 seconds
Started Jul 28 05:32:52 PM PDT 24
Finished Jul 28 05:35:01 PM PDT 24
Peak memory 261180 kb
Host smart-23e9b70e-470c-4ed2-b0b7-5d165593f345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798057529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2798057529
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2333176137
Short name T56
Test name
Test status
Simulation time 2523610661 ps
CPU time 11.81 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:33:02 PM PDT 24
Peak memory 216440 kb
Host smart-f515654b-d64a-49b7-b7dc-6401f53481ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333176137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2333176137
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.870996465
Short name T323
Test name
Test status
Simulation time 20151238257 ps
CPU time 126.44 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 251380 kb
Host smart-9f0164b3-fec5-4c0b-8ed7-f8e1eb378188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870996465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.870996465
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1086016711
Short name T210
Test name
Test status
Simulation time 94798572159 ps
CPU time 450.36 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:39:46 PM PDT 24
Peak memory 266700 kb
Host smart-ca2242cc-c848-4ce7-b44e-7b7a7922faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086016711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1086016711
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.619097837
Short name T183
Test name
Test status
Simulation time 5122267874 ps
CPU time 74.93 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 249352 kb
Host smart-3df40f4c-f659-43fd-b593-59e6351f86bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619097837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.619097837
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2061077689
Short name T252
Test name
Test status
Simulation time 9976459936 ps
CPU time 13.71 seconds
Started Jul 28 05:34:29 PM PDT 24
Finished Jul 28 05:34:42 PM PDT 24
Peak memory 240856 kb
Host smart-111c0ad7-6d7b-4e18-ae45-c522114c4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061077689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2061077689
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1669106672
Short name T171
Test name
Test status
Simulation time 47387551564 ps
CPU time 363.64 seconds
Started Jul 28 05:34:51 PM PDT 24
Finished Jul 28 05:40:55 PM PDT 24
Peak memory 268316 kb
Host smart-46546445-f540-4a8a-bc8c-a0cafa0df389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669106672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1669106672
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2782164438
Short name T78
Test name
Test status
Simulation time 1604997670 ps
CPU time 11.88 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 249132 kb
Host smart-8af79212-6178-414c-aab9-2dc7185e2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782164438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2782164438
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4078528128
Short name T61
Test name
Test status
Simulation time 27619471 ps
CPU time 1.64 seconds
Started Jul 28 05:21:21 PM PDT 24
Finished Jul 28 05:21:23 PM PDT 24
Peak memory 215780 kb
Host smart-620e8647-a100-4d0b-8036-ecb1a132ea01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078528128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
078528128
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1610823543
Short name T73
Test name
Test status
Simulation time 19606544 ps
CPU time 1.19 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 207240 kb
Host smart-92250f76-4470-4756-9f94-fcdab0909640
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610823543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1610823543
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3330339266
Short name T106
Test name
Test status
Simulation time 5064737541 ps
CPU time 22.15 seconds
Started Jul 28 05:21:13 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 215480 kb
Host smart-d17f48b0-2504-4d1b-80c5-9b308b47fdb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330339266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3330339266
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1020384498
Short name T1035
Test name
Test status
Simulation time 720803254 ps
CPU time 11.72 seconds
Started Jul 28 05:21:13 PM PDT 24
Finished Jul 28 05:21:25 PM PDT 24
Peak memory 207216 kb
Host smart-8f846382-7dd1-49ef-9957-a8b1da95aead
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020384498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1020384498
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3797914288
Short name T1081
Test name
Test status
Simulation time 54375979 ps
CPU time 1.23 seconds
Started Jul 28 05:21:16 PM PDT 24
Finished Jul 28 05:21:17 PM PDT 24
Peak memory 207068 kb
Host smart-eabe54aa-fe77-479d-8fb0-828336a34987
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797914288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3797914288
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2797778833
Short name T1090
Test name
Test status
Simulation time 626974868 ps
CPU time 3.9 seconds
Started Jul 28 05:21:15 PM PDT 24
Finished Jul 28 05:21:19 PM PDT 24
Peak memory 218132 kb
Host smart-a020083b-95db-4dbd-bb04-bf9700b6f5e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797778833 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2797778833
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3815333909
Short name T1102
Test name
Test status
Simulation time 244571699 ps
CPU time 1.96 seconds
Started Jul 28 05:21:12 PM PDT 24
Finished Jul 28 05:21:14 PM PDT 24
Peak memory 215484 kb
Host smart-145483c1-3b50-4fba-b4cd-01647aea5e34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815333909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
815333909
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2792353457
Short name T1029
Test name
Test status
Simulation time 20368405 ps
CPU time 0.8 seconds
Started Jul 28 05:21:12 PM PDT 24
Finished Jul 28 05:21:13 PM PDT 24
Peak memory 203952 kb
Host smart-16ea5188-f1e0-49cf-8e84-98962d570f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792353457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
792353457
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.786508991
Short name T102
Test name
Test status
Simulation time 86903003 ps
CPU time 1.85 seconds
Started Jul 28 05:21:11 PM PDT 24
Finished Jul 28 05:21:13 PM PDT 24
Peak memory 215336 kb
Host smart-1e4167d2-369e-4990-b204-50c69a34a918
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786508991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.786508991
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2142082732
Short name T1013
Test name
Test status
Simulation time 40620888 ps
CPU time 0.66 seconds
Started Jul 28 05:21:16 PM PDT 24
Finished Jul 28 05:21:17 PM PDT 24
Peak memory 204212 kb
Host smart-31b5c13b-b282-458c-9fe8-6ddd1e741300
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142082732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2142082732
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.697957101
Short name T1113
Test name
Test status
Simulation time 229270992 ps
CPU time 3.73 seconds
Started Jul 28 05:21:12 PM PDT 24
Finished Jul 28 05:21:15 PM PDT 24
Peak memory 215448 kb
Host smart-5eaf02bc-6fc7-4727-8bf1-7141052c64d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697957101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.697957101
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3577083428
Short name T1085
Test name
Test status
Simulation time 182153980 ps
CPU time 2.45 seconds
Started Jul 28 05:21:15 PM PDT 24
Finished Jul 28 05:21:17 PM PDT 24
Peak memory 215508 kb
Host smart-d7ae000a-a75e-4f5e-9cab-6245bff02abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577083428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
577083428
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.261140571
Short name T1049
Test name
Test status
Simulation time 495911123 ps
CPU time 6.53 seconds
Started Jul 28 05:21:17 PM PDT 24
Finished Jul 28 05:21:24 PM PDT 24
Peak memory 215724 kb
Host smart-8de75e24-336f-4274-a2e5-db344f7a3776
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261140571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.261140571
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.564358803
Short name T1104
Test name
Test status
Simulation time 1018570066 ps
CPU time 7.16 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:26 PM PDT 24
Peak memory 207164 kb
Host smart-cdf5b660-74e1-4a13-9e1e-d867de63219a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564358803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.564358803
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.263432701
Short name T1028
Test name
Test status
Simulation time 1402394932 ps
CPU time 20.96 seconds
Started Jul 28 05:21:17 PM PDT 24
Finished Jul 28 05:21:38 PM PDT 24
Peak memory 215432 kb
Host smart-af7027c1-57cf-4a6b-80f1-f24a7c39a486
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263432701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.263432701
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4029561267
Short name T1131
Test name
Test status
Simulation time 97167537 ps
CPU time 1.97 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:22 PM PDT 24
Peak memory 216412 kb
Host smart-c15b4e8a-9989-400a-9aa3-6b6b2255732a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029561267 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4029561267
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3006376492
Short name T1043
Test name
Test status
Simulation time 70867258 ps
CPU time 1.35 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 207184 kb
Host smart-52b3fd2f-292a-46ea-ba50-89a8b533811c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006376492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
006376492
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.342395130
Short name T1058
Test name
Test status
Simulation time 26484533 ps
CPU time 0.76 seconds
Started Jul 28 05:21:17 PM PDT 24
Finished Jul 28 05:21:18 PM PDT 24
Peak memory 203876 kb
Host smart-665aebca-85ca-4a3f-90e0-fd7416b9c25e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342395130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.342395130
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2516174982
Short name T100
Test name
Test status
Simulation time 95416369 ps
CPU time 1.93 seconds
Started Jul 28 05:21:18 PM PDT 24
Finished Jul 28 05:21:20 PM PDT 24
Peak memory 215440 kb
Host smart-eae84f94-293c-4af8-8078-a86a4cc02272
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516174982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2516174982
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2750763282
Short name T1034
Test name
Test status
Simulation time 26902420 ps
CPU time 0.68 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 204192 kb
Host smart-bcec31aa-9da4-415f-bc49-7d4c35354a7f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750763282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2750763282
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.93899668
Short name T1061
Test name
Test status
Simulation time 116839685 ps
CPU time 4.23 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:23 PM PDT 24
Peak memory 215468 kb
Host smart-176cd920-706e-4f48-ba88-e8b5d1ec9b18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93899668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_same_csr_outstanding.93899668
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2934546915
Short name T1059
Test name
Test status
Simulation time 144643069 ps
CPU time 1.91 seconds
Started Jul 28 05:21:34 PM PDT 24
Finished Jul 28 05:21:36 PM PDT 24
Peak memory 215524 kb
Host smart-419f9984-8271-4063-80f2-14f048548d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934546915 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2934546915
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2944602618
Short name T1122
Test name
Test status
Simulation time 79301567 ps
CPU time 2.65 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 215476 kb
Host smart-587856ca-7efb-4adf-aed3-a1aa02095a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944602618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2944602618
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.470188612
Short name T1077
Test name
Test status
Simulation time 14517918 ps
CPU time 0.7 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 203936 kb
Host smart-6bd7963f-14b7-4686-987b-dbd0016bfa33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470188612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.470188612
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3999277378
Short name T1098
Test name
Test status
Simulation time 1198061274 ps
CPU time 3.18 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 215452 kb
Host smart-1394e38b-c5b7-4403-b7b0-3e35baa03fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999277378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3999277378
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4159882888
Short name T63
Test name
Test status
Simulation time 97094620 ps
CPU time 3.83 seconds
Started Jul 28 05:21:35 PM PDT 24
Finished Jul 28 05:21:39 PM PDT 24
Peak memory 216568 kb
Host smart-cfa21a43-ccce-4f71-893a-b28e295205f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159882888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4159882888
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3787121030
Short name T80
Test name
Test status
Simulation time 2467227962 ps
CPU time 14.31 seconds
Started Jul 28 05:21:34 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 215912 kb
Host smart-c823021d-d9a2-4d75-befc-c2e1f1c3bc7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787121030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3787121030
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1458171862
Short name T82
Test name
Test status
Simulation time 24396706 ps
CPU time 1.56 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 215412 kb
Host smart-d4eb23c8-f847-4400-9114-deb658da73d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458171862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1458171862
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4173899735
Short name T1108
Test name
Test status
Simulation time 68613344 ps
CPU time 1.29 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 207176 kb
Host smart-180804ef-1d7b-44f7-a5c9-35236dbf512d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173899735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4173899735
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2060411527
Short name T1075
Test name
Test status
Simulation time 16227413 ps
CPU time 0.78 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 203888 kb
Host smart-138a09d6-63fc-45ca-ae18-1f46c1e0e8c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060411527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2060411527
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.750934258
Short name T1067
Test name
Test status
Simulation time 3183786831 ps
CPU time 4.51 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:38 PM PDT 24
Peak memory 215552 kb
Host smart-0403c2c5-4816-4081-8fb3-58c69640971c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750934258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.750934258
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.373951834
Short name T1065
Test name
Test status
Simulation time 74623888 ps
CPU time 1.62 seconds
Started Jul 28 05:21:34 PM PDT 24
Finished Jul 28 05:21:36 PM PDT 24
Peak memory 215488 kb
Host smart-fc6abf30-9118-420e-9757-12120c8bdd2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373951834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.373951834
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.369833321
Short name T1092
Test name
Test status
Simulation time 591301172 ps
CPU time 8.89 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:41 PM PDT 24
Peak memory 215384 kb
Host smart-c32289ef-3d70-4f92-82d0-348a29dc2312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369833321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.369833321
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3510872007
Short name T1130
Test name
Test status
Simulation time 191679560 ps
CPU time 2.01 seconds
Started Jul 28 05:21:41 PM PDT 24
Finished Jul 28 05:21:43 PM PDT 24
Peak memory 216424 kb
Host smart-6b38f821-5849-4a46-a0d9-0115beb8487b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510872007 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3510872007
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3224536318
Short name T1106
Test name
Test status
Simulation time 95606904 ps
CPU time 1.55 seconds
Started Jul 28 05:21:39 PM PDT 24
Finished Jul 28 05:21:40 PM PDT 24
Peak memory 207156 kb
Host smart-ef41ba35-84d1-478c-b304-1f132b8863d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224536318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3224536318
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.156931064
Short name T1056
Test name
Test status
Simulation time 28098510 ps
CPU time 0.78 seconds
Started Jul 28 05:21:40 PM PDT 24
Finished Jul 28 05:21:41 PM PDT 24
Peak memory 203792 kb
Host smart-bfe97948-e006-467c-8fb6-b18e2d1c716d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156931064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.156931064
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1816963076
Short name T132
Test name
Test status
Simulation time 1244313037 ps
CPU time 1.94 seconds
Started Jul 28 05:21:38 PM PDT 24
Finished Jul 28 05:21:40 PM PDT 24
Peak memory 215504 kb
Host smart-6422cbab-096f-449c-b96a-9b48da390485
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816963076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1816963076
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3527530229
Short name T1103
Test name
Test status
Simulation time 182332144 ps
CPU time 4.07 seconds
Started Jul 28 05:21:39 PM PDT 24
Finished Jul 28 05:21:43 PM PDT 24
Peak memory 217004 kb
Host smart-6b5051fb-2fd7-446e-9a7f-5dfd6d43ae6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527530229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3527530229
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.682728716
Short name T103
Test name
Test status
Simulation time 188145416 ps
CPU time 1.34 seconds
Started Jul 28 05:21:39 PM PDT 24
Finished Jul 28 05:21:40 PM PDT 24
Peak memory 215532 kb
Host smart-1070d7e1-013c-424f-8452-db956754e5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682728716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.682728716
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1140125702
Short name T1101
Test name
Test status
Simulation time 155046690 ps
CPU time 0.79 seconds
Started Jul 28 05:21:39 PM PDT 24
Finished Jul 28 05:21:40 PM PDT 24
Peak memory 203936 kb
Host smart-83b07014-ab54-40aa-9d4f-2bbf2576ce42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140125702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1140125702
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2917632515
Short name T1124
Test name
Test status
Simulation time 57249799 ps
CPU time 1.87 seconds
Started Jul 28 05:21:41 PM PDT 24
Finished Jul 28 05:21:42 PM PDT 24
Peak memory 207248 kb
Host smart-411859cb-77cf-471c-a5d4-965156cf0131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917632515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2917632515
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1066659160
Short name T88
Test name
Test status
Simulation time 177027582 ps
CPU time 4.11 seconds
Started Jul 28 05:21:38 PM PDT 24
Finished Jul 28 05:21:42 PM PDT 24
Peak memory 215552 kb
Host smart-2b37c09f-dd6c-415a-abd7-49a2784b9b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066659160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1066659160
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1877282442
Short name T1055
Test name
Test status
Simulation time 96347155 ps
CPU time 2.56 seconds
Started Jul 28 05:21:44 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 216788 kb
Host smart-5577102e-fe35-4bad-aedb-de97509a8b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877282442 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1877282442
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.28457074
Short name T1040
Test name
Test status
Simulation time 134569108 ps
CPU time 1.21 seconds
Started Jul 28 05:21:42 PM PDT 24
Finished Jul 28 05:21:43 PM PDT 24
Peak memory 215400 kb
Host smart-ef0952d2-fac9-4788-87e3-d2b952821462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.28457074
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1757413091
Short name T1052
Test name
Test status
Simulation time 41308565 ps
CPU time 0.71 seconds
Started Jul 28 05:21:41 PM PDT 24
Finished Jul 28 05:21:42 PM PDT 24
Peak memory 204124 kb
Host smart-4a6628ba-d88c-4584-8b96-6596fca4de5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757413091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1757413091
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2601298620
Short name T134
Test name
Test status
Simulation time 793794044 ps
CPU time 4.4 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:49 PM PDT 24
Peak memory 215408 kb
Host smart-72a063b6-fbe8-40c2-a282-8b60f34066ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601298620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2601298620
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1080738935
Short name T1125
Test name
Test status
Simulation time 123214351 ps
CPU time 3.89 seconds
Started Jul 28 05:21:40 PM PDT 24
Finished Jul 28 05:21:44 PM PDT 24
Peak memory 215504 kb
Host smart-58d4bae6-de92-4ae9-b9a4-82783c61abc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080738935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1080738935
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3788170105
Short name T158
Test name
Test status
Simulation time 3585255376 ps
CPU time 14.87 seconds
Started Jul 28 05:21:38 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 215576 kb
Host smart-72b8717a-e802-454d-b0b0-64b6b8e8175f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788170105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3788170105
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.119971832
Short name T1054
Test name
Test status
Simulation time 11592546 ps
CPU time 0.74 seconds
Started Jul 28 05:21:44 PM PDT 24
Finished Jul 28 05:21:45 PM PDT 24
Peak memory 203884 kb
Host smart-f0dd6602-044e-4eb5-9dfe-5d65ec6877b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119971832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.119971832
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.534579356
Short name T1119
Test name
Test status
Simulation time 129182693 ps
CPU time 2.15 seconds
Started Jul 28 05:21:48 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 215448 kb
Host smart-4e246706-5ba9-4252-8d05-2834259cfb71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534579356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.534579356
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1372045231
Short name T1114
Test name
Test status
Simulation time 57553456 ps
CPU time 3.61 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 215628 kb
Host smart-afeefc35-a04c-4c03-b1c5-f95a44b13ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372045231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1372045231
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3088929744
Short name T162
Test name
Test status
Simulation time 557649932 ps
CPU time 6.89 seconds
Started Jul 28 05:21:44 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 215484 kb
Host smart-bdafc017-9f33-4264-8760-b046a33cc40f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088929744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3088929744
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2015161043
Short name T1109
Test name
Test status
Simulation time 460619894 ps
CPU time 3.69 seconds
Started Jul 28 05:21:44 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 217508 kb
Host smart-a306a044-25e0-4309-964f-cba970bbb530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015161043 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2015161043
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2605511511
Short name T1083
Test name
Test status
Simulation time 71593305 ps
CPU time 2.02 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 215320 kb
Host smart-0feceabd-b0bb-4fa0-af77-58bd58c56f19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605511511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2605511511
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1400732420
Short name T1022
Test name
Test status
Simulation time 12897386 ps
CPU time 0.74 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 203820 kb
Host smart-371b6255-2c60-44b1-84ae-a245fc86aabe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400732420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1400732420
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.609256468
Short name T1063
Test name
Test status
Simulation time 159276137 ps
CPU time 4.29 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:54 PM PDT 24
Peak memory 215460 kb
Host smart-264e2167-2427-4219-916f-4c7740967459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609256468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.609256468
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3948789316
Short name T89
Test name
Test status
Simulation time 36404547 ps
CPU time 2.38 seconds
Started Jul 28 05:21:48 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 215520 kb
Host smart-148d4452-f2e3-4a19-a3bb-10c1c3566926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948789316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3948789316
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3283982487
Short name T154
Test name
Test status
Simulation time 511343639 ps
CPU time 8.45 seconds
Started Jul 28 05:21:47 PM PDT 24
Finished Jul 28 05:21:55 PM PDT 24
Peak memory 215956 kb
Host smart-c3b32119-5226-48d2-9cf6-51949c4061fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283982487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3283982487
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3576600276
Short name T83
Test name
Test status
Simulation time 86015834 ps
CPU time 2.97 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 216476 kb
Host smart-34106dd5-b76e-442a-9bec-870f634686bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576600276 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3576600276
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1543056936
Short name T1030
Test name
Test status
Simulation time 55895072 ps
CPU time 2.08 seconds
Started Jul 28 05:21:47 PM PDT 24
Finished Jul 28 05:21:49 PM PDT 24
Peak memory 215488 kb
Host smart-d626de22-f1a3-4018-8947-96878121dddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543056936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1543056936
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3185344041
Short name T1120
Test name
Test status
Simulation time 16432129 ps
CPU time 0.72 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 203920 kb
Host smart-219d364e-94f1-4016-bbff-ee4d5da3125c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185344041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3185344041
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2877511257
Short name T1126
Test name
Test status
Simulation time 52404404 ps
CPU time 1.66 seconds
Started Jul 28 05:21:48 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 215336 kb
Host smart-f14afd2d-47ee-4918-b050-699a26e3b7aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877511257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2877511257
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2931666446
Short name T85
Test name
Test status
Simulation time 46436468 ps
CPU time 1.77 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 215484 kb
Host smart-4a854df9-8d98-4046-9f6b-e83cea10dee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931666446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2931666446
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1164207032
Short name T136
Test name
Test status
Simulation time 3709266172 ps
CPU time 8.68 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:55 PM PDT 24
Peak memory 216108 kb
Host smart-5f2240c3-0b3f-4537-8370-2a960d03db99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164207032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1164207032
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.133568845
Short name T1071
Test name
Test status
Simulation time 104679703 ps
CPU time 2.76 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 216708 kb
Host smart-2af99a91-be1c-4c01-9c79-1ac337878d63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133568845 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.133568845
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.30731463
Short name T107
Test name
Test status
Simulation time 38803734 ps
CPU time 1.36 seconds
Started Jul 28 05:21:47 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 207320 kb
Host smart-2381740c-e791-4cfa-93d8-072090de8961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30731463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.30731463
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1247499615
Short name T1032
Test name
Test status
Simulation time 18338037 ps
CPU time 0.74 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 203836 kb
Host smart-3651560e-e255-41a8-b657-39e255f72966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247499615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1247499615
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.660720438
Short name T1080
Test name
Test status
Simulation time 106914280 ps
CPU time 3 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 215476 kb
Host smart-6a0195d7-edff-45fe-81b8-1b42f4a3b8da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660720438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.660720438
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2746496360
Short name T1057
Test name
Test status
Simulation time 46791551 ps
CPU time 1.76 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 215572 kb
Host smart-7d930fb6-29fc-4dda-9320-9840ab7ea953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746496360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2746496360
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3348336176
Short name T156
Test name
Test status
Simulation time 2187579455 ps
CPU time 16.81 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:22:02 PM PDT 24
Peak memory 215492 kb
Host smart-324a7806-a8ee-4528-babb-2b207b3efa92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348336176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3348336176
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3793282844
Short name T1038
Test name
Test status
Simulation time 58604234 ps
CPU time 4.14 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:55 PM PDT 24
Peak memory 218732 kb
Host smart-3eb996b9-ab09-4e28-af8e-4eb9facd8ce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793282844 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3793282844
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.751201814
Short name T1121
Test name
Test status
Simulation time 136319412 ps
CPU time 2.3 seconds
Started Jul 28 05:21:44 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 215396 kb
Host smart-3a3f164b-ef65-46fd-92a7-89ee1f53a1f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751201814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.751201814
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2610334152
Short name T1045
Test name
Test status
Simulation time 14732042 ps
CPU time 0.7 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 203904 kb
Host smart-9882a360-5b3a-4868-a1b6-19af60c45654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610334152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2610334152
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2284337168
Short name T1064
Test name
Test status
Simulation time 95252923 ps
CPU time 1.8 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 215380 kb
Host smart-54882d33-9b1b-404d-92ef-8e9da1b7171b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284337168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2284337168
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.352396791
Short name T91
Test name
Test status
Simulation time 106750911 ps
CPU time 3.23 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:54 PM PDT 24
Peak memory 215560 kb
Host smart-60b38ae8-ea28-4a74-80c5-bb3950a136e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352396791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.352396791
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2761992815
Short name T108
Test name
Test status
Simulation time 941178528 ps
CPU time 8.58 seconds
Started Jul 28 05:21:22 PM PDT 24
Finished Jul 28 05:21:30 PM PDT 24
Peak memory 207044 kb
Host smart-afe21fe7-4f77-4191-8807-3d261a0d210b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761992815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2761992815
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.304157365
Short name T1118
Test name
Test status
Simulation time 4824721840 ps
CPU time 26.92 seconds
Started Jul 28 05:21:18 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 215472 kb
Host smart-70ff1a02-ff22-4698-995e-050658072a9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304157365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.304157365
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2433366265
Short name T105
Test name
Test status
Simulation time 30397091 ps
CPU time 1.16 seconds
Started Jul 28 05:21:18 PM PDT 24
Finished Jul 28 05:21:19 PM PDT 24
Peak memory 207252 kb
Host smart-0d8a4670-a068-499f-acae-361d8abc8d2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433366265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2433366265
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1359681607
Short name T1123
Test name
Test status
Simulation time 486600867 ps
CPU time 3.3 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:23 PM PDT 24
Peak memory 217640 kb
Host smart-31ad8330-5aad-42b3-8151-5f61895dcbc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359681607 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1359681607
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.192665912
Short name T124
Test name
Test status
Simulation time 127774613 ps
CPU time 1.25 seconds
Started Jul 28 05:21:21 PM PDT 24
Finished Jul 28 05:21:22 PM PDT 24
Peak memory 215320 kb
Host smart-a16a8aa6-293a-4e10-8751-d80c68ec27a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192665912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.192665912
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3349443921
Short name T1014
Test name
Test status
Simulation time 11918004 ps
CPU time 0.73 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:20 PM PDT 24
Peak memory 203924 kb
Host smart-693a64b1-8b94-43ca-87a7-0e27d5a6d892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349443921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
349443921
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3384010952
Short name T101
Test name
Test status
Simulation time 18946821 ps
CPU time 1.36 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 215344 kb
Host smart-265003fc-a907-4be6-bc6c-dbe3d1f8961b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384010952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3384010952
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3665457599
Short name T1053
Test name
Test status
Simulation time 13643896 ps
CPU time 0.69 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 204212 kb
Host smart-40438ffe-f75c-4a75-94eb-d07c5abdbc28
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665457599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3665457599
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4095202342
Short name T1097
Test name
Test status
Simulation time 116446767 ps
CPU time 1.87 seconds
Started Jul 28 05:21:17 PM PDT 24
Finished Jul 28 05:21:19 PM PDT 24
Peak memory 215420 kb
Host smart-4b7a8c3a-61df-4307-82d5-eff862d17baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095202342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4095202342
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1210242386
Short name T90
Test name
Test status
Simulation time 346748335 ps
CPU time 3.66 seconds
Started Jul 28 05:21:17 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 215572 kb
Host smart-47b0851b-d1b9-4010-a1db-23a494962900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210242386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
210242386
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2011924346
Short name T96
Test name
Test status
Simulation time 551926750 ps
CPU time 13.87 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 215572 kb
Host smart-fc878a16-4574-4321-81c4-6f21682bec06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011924346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2011924346
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1836858594
Short name T1037
Test name
Test status
Simulation time 121642655 ps
CPU time 0.72 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 203936 kb
Host smart-a8ba5118-dc04-450f-81be-918d9deef95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836858594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1836858594
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2414079379
Short name T1088
Test name
Test status
Simulation time 71561973 ps
CPU time 0.74 seconds
Started Jul 28 05:21:47 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 203932 kb
Host smart-07e80665-f2b9-4901-9a7c-31c429eff4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414079379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2414079379
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1849575603
Short name T1023
Test name
Test status
Simulation time 14153645 ps
CPU time 0.71 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 204260 kb
Host smart-6b90dc52-fca8-4fba-b590-65d6358a4937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849575603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1849575603
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2760276661
Short name T1021
Test name
Test status
Simulation time 23857427 ps
CPU time 0.7 seconds
Started Jul 28 05:21:48 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 203964 kb
Host smart-55569eda-63d4-4bc4-babb-5a8a7d144a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760276661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2760276661
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2317333349
Short name T1073
Test name
Test status
Simulation time 27306653 ps
CPU time 0.81 seconds
Started Jul 28 05:21:47 PM PDT 24
Finished Jul 28 05:21:48 PM PDT 24
Peak memory 203912 kb
Host smart-6357b2b4-bc83-48ff-b5c4-fc101f7dbba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317333349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2317333349
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2482093402
Short name T1020
Test name
Test status
Simulation time 36893387 ps
CPU time 0.76 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 203964 kb
Host smart-28497a1b-e53b-406a-bdcb-3f8d835a4f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482093402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2482093402
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.508107577
Short name T1025
Test name
Test status
Simulation time 14304326 ps
CPU time 0.75 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:45 PM PDT 24
Peak memory 203884 kb
Host smart-1b68a1f2-5a81-45f1-afd5-81e70bedba8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508107577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.508107577
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3371975589
Short name T1015
Test name
Test status
Simulation time 102369341 ps
CPU time 0.79 seconds
Started Jul 28 05:21:45 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 203960 kb
Host smart-131b5165-81fd-42c6-9f64-3987b402151b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371975589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3371975589
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1144428900
Short name T1116
Test name
Test status
Simulation time 23367950 ps
CPU time 0.73 seconds
Started Jul 28 05:21:46 PM PDT 24
Finished Jul 28 05:21:47 PM PDT 24
Peak memory 203928 kb
Host smart-e6ec2db5-1972-4cfc-8180-72f2373769ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144428900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1144428900
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.87943452
Short name T1024
Test name
Test status
Simulation time 17604968 ps
CPU time 0.75 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 204224 kb
Host smart-b05a28eb-d270-4c11-86ec-67028614b43d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87943452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.87943452
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3989247380
Short name T1093
Test name
Test status
Simulation time 4575388656 ps
CPU time 16.13 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 207272 kb
Host smart-2964c6ab-6de5-4d35-8881-a4ff532254d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989247380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3989247380
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2177188133
Short name T1050
Test name
Test status
Simulation time 2418818819 ps
CPU time 13.34 seconds
Started Jul 28 05:21:18 PM PDT 24
Finished Jul 28 05:21:31 PM PDT 24
Peak memory 207244 kb
Host smart-3a901b25-fa7f-4cd6-81e9-4eb3ba78e8f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177188133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2177188133
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3145022344
Short name T72
Test name
Test status
Simulation time 75243318 ps
CPU time 0.97 seconds
Started Jul 28 05:21:21 PM PDT 24
Finished Jul 28 05:21:22 PM PDT 24
Peak memory 207320 kb
Host smart-2f1f47c6-7ad3-42b2-9142-3ffc8e5402d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145022344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3145022344
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4265137686
Short name T1046
Test name
Test status
Simulation time 205940240 ps
CPU time 1.8 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 216544 kb
Host smart-bfcfb8de-f59c-4d4d-8698-91cee41c7cb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265137686 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4265137686
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1678919605
Short name T1117
Test name
Test status
Simulation time 156377781 ps
CPU time 2.52 seconds
Started Jul 28 05:21:18 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 215432 kb
Host smart-58152f23-72f1-40f5-9f5d-75850d92014d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678919605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
678919605
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2259661166
Short name T1082
Test name
Test status
Simulation time 39756214 ps
CPU time 0.75 seconds
Started Jul 28 05:21:21 PM PDT 24
Finished Jul 28 05:21:21 PM PDT 24
Peak memory 204212 kb
Host smart-d90b6d45-db29-4bef-ba19-2ed4f8df7dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259661166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
259661166
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.218272464
Short name T109
Test name
Test status
Simulation time 217859833 ps
CPU time 2.16 seconds
Started Jul 28 05:21:21 PM PDT 24
Finished Jul 28 05:21:23 PM PDT 24
Peak memory 215372 kb
Host smart-dc880aa8-7f16-418f-80ba-f12e44b0f352
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218272464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.218272464
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.702993319
Short name T1105
Test name
Test status
Simulation time 12028573 ps
CPU time 0.71 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:20 PM PDT 24
Peak memory 203892 kb
Host smart-7784725b-743f-4e3a-86f5-7ae6648626be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702993319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.702993319
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1838848537
Short name T133
Test name
Test status
Simulation time 93860445 ps
CPU time 2.16 seconds
Started Jul 28 05:21:20 PM PDT 24
Finished Jul 28 05:21:22 PM PDT 24
Peak memory 215452 kb
Host smart-76787774-b779-42f7-8319-f3fed20fd419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838848537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1838848537
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4085597870
Short name T92
Test name
Test status
Simulation time 83065460 ps
CPU time 2.43 seconds
Started Jul 28 05:21:19 PM PDT 24
Finished Jul 28 05:21:22 PM PDT 24
Peak memory 215556 kb
Host smart-23bfd93d-962d-485a-831e-11afa0c200b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085597870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
085597870
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4025727658
Short name T160
Test name
Test status
Simulation time 1562936566 ps
CPU time 9.39 seconds
Started Jul 28 05:21:18 PM PDT 24
Finished Jul 28 05:21:28 PM PDT 24
Peak memory 215420 kb
Host smart-9f09c58d-35ff-4df7-a2b5-25882ce1ba76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025727658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4025727658
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1171367466
Short name T1128
Test name
Test status
Simulation time 11042050 ps
CPU time 0.7 seconds
Started Jul 28 05:21:52 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 203928 kb
Host smart-182190b0-9160-46db-90b0-648ac64abd43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171367466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1171367466
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2214074079
Short name T1099
Test name
Test status
Simulation time 24564672 ps
CPU time 0.73 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 203804 kb
Host smart-6cc3bd26-f9de-4ff4-b927-ba3a8a4d4548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214074079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2214074079
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4263447625
Short name T1084
Test name
Test status
Simulation time 36621675 ps
CPU time 0.71 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 204216 kb
Host smart-c97c8e4f-01d1-4063-ab81-9d784679957a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263447625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4263447625
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1013918388
Short name T1017
Test name
Test status
Simulation time 19026943 ps
CPU time 0.72 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 203828 kb
Host smart-e117d649-e0f9-4e93-a22f-d1c0e85d19e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013918388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1013918388
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1048918503
Short name T1115
Test name
Test status
Simulation time 30265983 ps
CPU time 0.73 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 203880 kb
Host smart-d4287ffb-ac62-4c88-862d-efbd51867913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048918503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1048918503
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2458022085
Short name T1070
Test name
Test status
Simulation time 21331412 ps
CPU time 0.69 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 203944 kb
Host smart-2c348da7-7249-42fb-af6a-ccf5b174d501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458022085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2458022085
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1545577504
Short name T1044
Test name
Test status
Simulation time 24870741 ps
CPU time 0.7 seconds
Started Jul 28 05:21:52 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 203928 kb
Host smart-65c846b4-0433-4e0a-bc18-4b95a7c0daad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545577504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1545577504
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.30199545
Short name T1112
Test name
Test status
Simulation time 95483802 ps
CPU time 0.74 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 204244 kb
Host smart-f7e4c804-04e2-44b0-87a9-cf5d9393d066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30199545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.30199545
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2929634219
Short name T1016
Test name
Test status
Simulation time 23189654 ps
CPU time 0.71 seconds
Started Jul 28 05:21:54 PM PDT 24
Finished Jul 28 05:21:55 PM PDT 24
Peak memory 203820 kb
Host smart-5ca4dab0-995c-4202-bcbb-34dbb13b9b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929634219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2929634219
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2474312521
Short name T1060
Test name
Test status
Simulation time 15323177 ps
CPU time 0.71 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 203932 kb
Host smart-289472ba-2da5-4cc3-ad53-ebd213596582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474312521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2474312521
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1066579255
Short name T110
Test name
Test status
Simulation time 212946636 ps
CPU time 14.55 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:41 PM PDT 24
Peak memory 207040 kb
Host smart-63467628-6895-4456-9eae-8ed50c2d9f1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066579255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1066579255
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3412036555
Short name T1110
Test name
Test status
Simulation time 1050363884 ps
CPU time 35.3 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:22:03 PM PDT 24
Peak memory 207192 kb
Host smart-6369ecd0-3042-48dc-b661-205c958fda7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412036555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3412036555
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.785909609
Short name T71
Test name
Test status
Simulation time 94193919 ps
CPU time 1.42 seconds
Started Jul 28 05:21:29 PM PDT 24
Finished Jul 28 05:21:31 PM PDT 24
Peak memory 216420 kb
Host smart-8c59e467-343c-4ac8-8c6f-81517b1b8f6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785909609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.785909609
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2639031859
Short name T1107
Test name
Test status
Simulation time 120148826 ps
CPU time 3.54 seconds
Started Jul 28 05:21:25 PM PDT 24
Finished Jul 28 05:21:29 PM PDT 24
Peak memory 218032 kb
Host smart-90955737-683a-4fca-9136-91cef416350e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639031859 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2639031859
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.361120165
Short name T1076
Test name
Test status
Simulation time 87547513 ps
CPU time 2.52 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:30 PM PDT 24
Peak memory 207452 kb
Host smart-805a8574-951d-4a3d-af92-6e80710bacc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361120165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.361120165
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3947053135
Short name T1036
Test name
Test status
Simulation time 17643720 ps
CPU time 0.8 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:28 PM PDT 24
Peak memory 203904 kb
Host smart-99e88675-10d9-45b5-95db-5de4949e421c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947053135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
947053135
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3924248814
Short name T98
Test name
Test status
Simulation time 144197514 ps
CPU time 1.34 seconds
Started Jul 28 05:21:25 PM PDT 24
Finished Jul 28 05:21:26 PM PDT 24
Peak memory 215308 kb
Host smart-c8b72224-35b1-4886-8100-e990eecb869d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924248814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3924248814
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2046200081
Short name T1095
Test name
Test status
Simulation time 69386715 ps
CPU time 0.68 seconds
Started Jul 28 05:21:29 PM PDT 24
Finished Jul 28 05:21:30 PM PDT 24
Peak memory 203856 kb
Host smart-a7289754-8fc6-4879-b5a1-007af6304777
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046200081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2046200081
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.832746053
Short name T1042
Test name
Test status
Simulation time 62232943 ps
CPU time 2.07 seconds
Started Jul 28 05:21:26 PM PDT 24
Finished Jul 28 05:21:28 PM PDT 24
Peak memory 207468 kb
Host smart-650be546-e908-43ae-b494-ebad8e8f679b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832746053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.832746053
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.464846590
Short name T1051
Test name
Test status
Simulation time 24854803 ps
CPU time 1.4 seconds
Started Jul 28 05:21:25 PM PDT 24
Finished Jul 28 05:21:27 PM PDT 24
Peak memory 215536 kb
Host smart-7176a900-3e89-4616-9b71-cca928968740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464846590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.464846590
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.950842718
Short name T161
Test name
Test status
Simulation time 2633207894 ps
CPU time 18.26 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 216524 kb
Host smart-0135bd33-54a1-40e4-b757-cc7684ead8c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950842718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.950842718
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3513008202
Short name T1068
Test name
Test status
Simulation time 48970446 ps
CPU time 0.75 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 203856 kb
Host smart-ef341d2a-e265-4908-8c12-f8426b510f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513008202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3513008202
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.427823802
Short name T1019
Test name
Test status
Simulation time 18569284 ps
CPU time 0.81 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 204208 kb
Host smart-9653199c-9ce2-441b-a6f5-c14a35731272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427823802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.427823802
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.369641683
Short name T1074
Test name
Test status
Simulation time 13524797 ps
CPU time 0.73 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 203892 kb
Host smart-af0e6c34-daa0-4b8b-80fd-60e02e73e123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369641683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.369641683
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.746879052
Short name T1127
Test name
Test status
Simulation time 15073590 ps
CPU time 0.77 seconds
Started Jul 28 05:21:51 PM PDT 24
Finished Jul 28 05:21:52 PM PDT 24
Peak memory 204228 kb
Host smart-d9daadd2-6870-45fd-a6fa-6a8dda22acdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746879052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.746879052
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.947511585
Short name T1027
Test name
Test status
Simulation time 15150341 ps
CPU time 0.73 seconds
Started Jul 28 05:21:52 PM PDT 24
Finished Jul 28 05:21:53 PM PDT 24
Peak memory 203956 kb
Host smart-5462fb7e-4d29-43b8-b0ec-baf95eb372a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947511585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.947511585
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1160813814
Short name T1018
Test name
Test status
Simulation time 11905368 ps
CPU time 0.71 seconds
Started Jul 28 05:21:50 PM PDT 24
Finished Jul 28 05:21:51 PM PDT 24
Peak memory 204260 kb
Host smart-5b581c20-b693-49e6-8690-1dd3565437d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160813814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1160813814
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1453585500
Short name T1079
Test name
Test status
Simulation time 39366621 ps
CPU time 0.72 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 204244 kb
Host smart-70aafb33-e33f-4a57-8851-f0c515371243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453585500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1453585500
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1653116982
Short name T1033
Test name
Test status
Simulation time 151869019 ps
CPU time 0.71 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:49 PM PDT 24
Peak memory 204264 kb
Host smart-dc8fba1d-f50e-4b01-bc87-43d0411a40fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653116982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1653116982
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4289747791
Short name T1039
Test name
Test status
Simulation time 41323195 ps
CPU time 0.74 seconds
Started Jul 28 05:21:53 PM PDT 24
Finished Jul 28 05:21:54 PM PDT 24
Peak memory 203836 kb
Host smart-5fa1295b-99ba-49b1-a47c-9f6ee727963c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289747791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4289747791
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3367221583
Short name T1072
Test name
Test status
Simulation time 68350553 ps
CPU time 0.79 seconds
Started Jul 28 05:21:49 PM PDT 24
Finished Jul 28 05:21:50 PM PDT 24
Peak memory 204236 kb
Host smart-a4fcd4c8-2db8-4d7f-bec3-ce42331f6a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367221583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3367221583
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3202204793
Short name T1087
Test name
Test status
Simulation time 56918802 ps
CPU time 1.82 seconds
Started Jul 28 05:21:25 PM PDT 24
Finished Jul 28 05:21:27 PM PDT 24
Peak memory 215592 kb
Host smart-56fed0b5-12da-439c-9181-b6af606172eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202204793 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3202204793
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.956632693
Short name T97
Test name
Test status
Simulation time 36074301 ps
CPU time 1.36 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:28 PM PDT 24
Peak memory 215440 kb
Host smart-9d64abdc-72f5-42b4-a7cc-66cfa5de01d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956632693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.956632693
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3107811448
Short name T1062
Test name
Test status
Simulation time 32759032 ps
CPU time 0.75 seconds
Started Jul 28 05:21:28 PM PDT 24
Finished Jul 28 05:21:29 PM PDT 24
Peak memory 204248 kb
Host smart-de0e388d-fe2e-45a5-ae3e-a4387dd39e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107811448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
107811448
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.824214824
Short name T1069
Test name
Test status
Simulation time 774147262 ps
CPU time 2.16 seconds
Started Jul 28 05:21:26 PM PDT 24
Finished Jul 28 05:21:29 PM PDT 24
Peak memory 215432 kb
Host smart-eb548ed9-3409-466a-9f8a-1de34f510fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824214824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.824214824
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1920255620
Short name T1078
Test name
Test status
Simulation time 2580102066 ps
CPU time 5.93 seconds
Started Jul 28 05:21:24 PM PDT 24
Finished Jul 28 05:21:30 PM PDT 24
Peak memory 215632 kb
Host smart-ddf81134-df91-4a5a-b774-3b72aa5cf0f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920255620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
920255620
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3695870271
Short name T155
Test name
Test status
Simulation time 204158262 ps
CPU time 7.02 seconds
Started Jul 28 05:21:25 PM PDT 24
Finished Jul 28 05:21:32 PM PDT 24
Peak memory 215500 kb
Host smart-7dcfbb3b-b20e-4b5c-be56-7c125d54dc31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695870271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3695870271
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3234227169
Short name T94
Test name
Test status
Simulation time 179294925 ps
CPU time 1.71 seconds
Started Jul 28 05:21:26 PM PDT 24
Finished Jul 28 05:21:28 PM PDT 24
Peak memory 215456 kb
Host smart-96878a3a-1a85-4505-99ca-002d25c5764a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234227169 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3234227169
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2124794739
Short name T1086
Test name
Test status
Simulation time 99606635 ps
CPU time 2.05 seconds
Started Jul 28 05:21:24 PM PDT 24
Finished Jul 28 05:21:26 PM PDT 24
Peak memory 207136 kb
Host smart-5936a26c-3379-4bcb-b0ca-b0f22dbe89f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124794739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
124794739
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2977406733
Short name T1031
Test name
Test status
Simulation time 35629453 ps
CPU time 0.76 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:28 PM PDT 24
Peak memory 204252 kb
Host smart-db61494a-17a3-44c8-8c8a-d0b8fa801ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977406733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
977406733
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2142358154
Short name T1066
Test name
Test status
Simulation time 911761914 ps
CPU time 4.74 seconds
Started Jul 28 05:21:26 PM PDT 24
Finished Jul 28 05:21:31 PM PDT 24
Peak memory 215420 kb
Host smart-7642d284-9077-4cf8-abfb-34f53b57bf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142358154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2142358154
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3335891380
Short name T1129
Test name
Test status
Simulation time 1277580991 ps
CPU time 8.24 seconds
Started Jul 28 05:21:27 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 216832 kb
Host smart-405c09e0-bf9f-43da-a63b-70ec7b882f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335891380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3335891380
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.483064540
Short name T62
Test name
Test status
Simulation time 170444170 ps
CPU time 2.74 seconds
Started Jul 28 05:21:34 PM PDT 24
Finished Jul 28 05:21:37 PM PDT 24
Peak memory 216964 kb
Host smart-946ce205-dd46-4527-9df5-eec2f196c225
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483064540 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.483064540
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1119392648
Short name T137
Test name
Test status
Simulation time 99690824 ps
CPU time 1.49 seconds
Started Jul 28 05:21:24 PM PDT 24
Finished Jul 28 05:21:25 PM PDT 24
Peak memory 215512 kb
Host smart-756f63a8-3fe8-4425-b4b0-dd4f03e8c584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119392648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
119392648
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3473724391
Short name T1026
Test name
Test status
Simulation time 13776805 ps
CPU time 0.73 seconds
Started Jul 28 05:21:31 PM PDT 24
Finished Jul 28 05:21:32 PM PDT 24
Peak memory 203912 kb
Host smart-6733abd3-7d06-426b-a0f3-171bf198733c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473724391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
473724391
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4006935809
Short name T138
Test name
Test status
Simulation time 822482181 ps
CPU time 4.39 seconds
Started Jul 28 05:21:34 PM PDT 24
Finished Jul 28 05:21:38 PM PDT 24
Peak memory 215876 kb
Host smart-c87dd55e-8070-469a-8671-04a30e030184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006935809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4006935809
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2920262608
Short name T1096
Test name
Test status
Simulation time 114054330 ps
CPU time 3.48 seconds
Started Jul 28 05:21:26 PM PDT 24
Finished Jul 28 05:21:29 PM PDT 24
Peak memory 217200 kb
Host smart-a20e1b17-1398-430d-b622-73a073a0a863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920262608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
920262608
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1763450059
Short name T1041
Test name
Test status
Simulation time 281085109 ps
CPU time 7.07 seconds
Started Jul 28 05:21:26 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 216000 kb
Host smart-ecc5863f-6982-4724-a778-becdc7ae2ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763450059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1763450059
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2096458244
Short name T135
Test name
Test status
Simulation time 202361772 ps
CPU time 2.74 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 218100 kb
Host smart-12873ea8-5db0-4a90-88b8-aa7c038be202
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096458244 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2096458244
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.256225669
Short name T104
Test name
Test status
Simulation time 43475207 ps
CPU time 1.45 seconds
Started Jul 28 05:21:34 PM PDT 24
Finished Jul 28 05:21:35 PM PDT 24
Peak memory 207120 kb
Host smart-a1b9446f-4302-4d42-b74d-5990709367eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256225669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.256225669
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.818839065
Short name T1091
Test name
Test status
Simulation time 31655371 ps
CPU time 0.76 seconds
Started Jul 28 05:21:31 PM PDT 24
Finished Jul 28 05:21:32 PM PDT 24
Peak memory 203872 kb
Host smart-8cc0129a-53c4-4625-9d86-0b5870d8acfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818839065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.818839065
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3676908800
Short name T1089
Test name
Test status
Simulation time 136149900 ps
CPU time 3.16 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:37 PM PDT 24
Peak memory 215724 kb
Host smart-a77adedd-bb38-4b08-a4cc-af690da69532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676908800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3676908800
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2612299083
Short name T1094
Test name
Test status
Simulation time 44647457 ps
CPU time 2.07 seconds
Started Jul 28 05:21:31 PM PDT 24
Finished Jul 28 05:21:33 PM PDT 24
Peak memory 215676 kb
Host smart-e38f5538-dcae-4af4-9d45-10d7836e3dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612299083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
612299083
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2263426704
Short name T163
Test name
Test status
Simulation time 774705210 ps
CPU time 13.33 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:46 PM PDT 24
Peak memory 215928 kb
Host smart-4bd0ac0f-d7dc-4bfa-a85b-cc223024b714
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263426704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2263426704
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3409155893
Short name T1048
Test name
Test status
Simulation time 46583008 ps
CPU time 1.86 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 215456 kb
Host smart-05adde33-1779-44a9-a1ff-ef99efa084d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409155893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3409155893
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3415676679
Short name T1047
Test name
Test status
Simulation time 278382612 ps
CPU time 2.13 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 215488 kb
Host smart-edca1777-a255-474d-a4a5-3e5387e4dccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415676679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
415676679
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.921325044
Short name T1100
Test name
Test status
Simulation time 14626005 ps
CPU time 0.77 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:33 PM PDT 24
Peak memory 203896 kb
Host smart-3a782877-abae-424c-ac20-ddf4e088a77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921325044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.921325044
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3800745131
Short name T1111
Test name
Test status
Simulation time 58546434 ps
CPU time 1.84 seconds
Started Jul 28 05:21:32 PM PDT 24
Finished Jul 28 05:21:34 PM PDT 24
Peak memory 215468 kb
Host smart-8b772c28-40f0-4bc1-9917-f85bbd729492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800745131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3800745131
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2701509337
Short name T86
Test name
Test status
Simulation time 128576108 ps
CPU time 2.77 seconds
Started Jul 28 05:21:33 PM PDT 24
Finished Jul 28 05:21:36 PM PDT 24
Peak memory 215564 kb
Host smart-536804be-0467-4a02-aa95-e547b8013190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701509337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
701509337
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2869146909
Short name T81
Test name
Test status
Simulation time 111277390 ps
CPU time 7.29 seconds
Started Jul 28 05:21:35 PM PDT 24
Finished Jul 28 05:21:42 PM PDT 24
Peak memory 215824 kb
Host smart-9bdf8693-f07c-4055-91a5-1411c5ecb26b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869146909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2869146909
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.854791113
Short name T707
Test name
Test status
Simulation time 14067657 ps
CPU time 0.75 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:32:09 PM PDT 24
Peak memory 204988 kb
Host smart-3e61c7db-ade5-44e0-9475-640c4671f387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854791113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.854791113
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1711171816
Short name T569
Test name
Test status
Simulation time 83647005 ps
CPU time 2.63 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:11 PM PDT 24
Peak memory 232864 kb
Host smart-28c64fa3-bfca-4c12-9ad7-07c7f6702420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711171816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1711171816
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1793027014
Short name T327
Test name
Test status
Simulation time 59808404 ps
CPU time 0.78 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 206740 kb
Host smart-6bf8b24e-c17f-4375-a111-fec4f9ed5bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793027014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1793027014
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.83839034
Short name T574
Test name
Test status
Simulation time 14092955225 ps
CPU time 48.36 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:57 PM PDT 24
Peak memory 251308 kb
Host smart-dc5bf820-1582-4f7c-b32d-98a8f0fd2345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83839034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.83839034
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1246255797
Short name T639
Test name
Test status
Simulation time 3468421721 ps
CPU time 45.93 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:55 PM PDT 24
Peak memory 249688 kb
Host smart-19629390-654d-403a-b42c-e64601dd6bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246255797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1246255797
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1645937296
Short name T599
Test name
Test status
Simulation time 45418787235 ps
CPU time 44.66 seconds
Started Jul 28 05:32:11 PM PDT 24
Finished Jul 28 05:32:55 PM PDT 24
Peak memory 249364 kb
Host smart-612e8d0d-974a-4760-b026-23c2e564e974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645937296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1645937296
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.160741063
Short name T230
Test name
Test status
Simulation time 314889512371 ps
CPU time 258.16 seconds
Started Jul 28 05:32:05 PM PDT 24
Finished Jul 28 05:36:24 PM PDT 24
Peak memory 257152 kb
Host smart-38dfda90-cc2d-4c86-9398-6906e5e67cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160741063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
160741063
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1184983734
Short name T830
Test name
Test status
Simulation time 1977312072 ps
CPU time 7.34 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:32:16 PM PDT 24
Peak memory 232888 kb
Host smart-7ae49b53-555a-4167-a029-e47c93516f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184983734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1184983734
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1938027151
Short name T237
Test name
Test status
Simulation time 52983105 ps
CPU time 2.37 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:12 PM PDT 24
Peak memory 224584 kb
Host smart-a9903a2a-6f86-410f-a897-e75fdbae900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938027151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1938027151
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2786733694
Short name T287
Test name
Test status
Simulation time 3524668790 ps
CPU time 7.98 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:15 PM PDT 24
Peak memory 224688 kb
Host smart-85839fc2-9c06-4055-8ddc-4bd9d6532bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786733694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2786733694
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1752721954
Short name T862
Test name
Test status
Simulation time 162133829 ps
CPU time 3.32 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:32:11 PM PDT 24
Peak memory 224616 kb
Host smart-70dd408a-d2b7-4f35-a1b3-07a8a71f5ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752721954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1752721954
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1553706604
Short name T927
Test name
Test status
Simulation time 26500774076 ps
CPU time 20.65 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:28 PM PDT 24
Peak memory 223884 kb
Host smart-4f88eb63-ce08-48e3-b940-11fd22d0895e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1553706604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1553706604
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2786479483
Short name T66
Test name
Test status
Simulation time 251064920 ps
CPU time 1.01 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:32:09 PM PDT 24
Peak memory 235964 kb
Host smart-86ff6cd3-809c-4646-9bb9-175073b9277a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786479483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2786479483
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2976342329
Short name T586
Test name
Test status
Simulation time 27465125415 ps
CPU time 61.3 seconds
Started Jul 28 05:32:10 PM PDT 24
Finished Jul 28 05:33:11 PM PDT 24
Peak memory 234112 kb
Host smart-b60edc01-8d81-4bf8-a1f2-7d23101d7a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976342329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2976342329
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.695780349
Short name T588
Test name
Test status
Simulation time 2127437935 ps
CPU time 4.27 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:10 PM PDT 24
Peak memory 216432 kb
Host smart-31fa1c28-ced5-4de0-abcc-92688f985195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695780349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.695780349
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1589805222
Short name T359
Test name
Test status
Simulation time 1515757316 ps
CPU time 5.18 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:14 PM PDT 24
Peak memory 216308 kb
Host smart-8ac89e78-64f2-4d87-bff6-94e9402a1012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589805222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1589805222
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2786063015
Short name T900
Test name
Test status
Simulation time 40217264 ps
CPU time 0.79 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 206116 kb
Host smart-49afe99a-c2e8-4e20-9716-db411b94f2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786063015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2786063015
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.998834913
Short name T486
Test name
Test status
Simulation time 122003460 ps
CPU time 0.84 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 206060 kb
Host smart-66d00869-5541-4e52-9c96-b4e1d613760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998834913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.998834913
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2339177515
Short name T485
Test name
Test status
Simulation time 3785822075 ps
CPU time 5.58 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:11 PM PDT 24
Peak memory 232928 kb
Host smart-ae130044-1e87-4f9e-8969-5c11b160c2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339177515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2339177515
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.737314143
Short name T385
Test name
Test status
Simulation time 31673685 ps
CPU time 0.73 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 204984 kb
Host smart-f4a729e4-410e-4924-b2ff-b7991be5a3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737314143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.737314143
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3222085446
Short name T245
Test name
Test status
Simulation time 404758105 ps
CPU time 3.29 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:11 PM PDT 24
Peak memory 224676 kb
Host smart-5ac6d2c2-d07d-47cb-b1b5-835ad3165235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222085446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3222085446
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2755948979
Short name T341
Test name
Test status
Simulation time 14718817 ps
CPU time 0.84 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:07 PM PDT 24
Peak memory 206664 kb
Host smart-d9bf72c4-416b-4045-aab3-0e13aefa6351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755948979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2755948979
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3818587327
Short name T869
Test name
Test status
Simulation time 22517024983 ps
CPU time 94.64 seconds
Started Jul 28 05:32:08 PM PDT 24
Finished Jul 28 05:33:43 PM PDT 24
Peak memory 251424 kb
Host smart-f43e4c7d-ca97-4935-86d7-5309ee00502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818587327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3818587327
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.508637577
Short name T960
Test name
Test status
Simulation time 5368270737 ps
CPU time 90.16 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:33:40 PM PDT 24
Peak memory 249284 kb
Host smart-64d7466d-4364-4b8d-939a-0194a361f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508637577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
508637577
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.873219476
Short name T300
Test name
Test status
Simulation time 626119835 ps
CPU time 13.11 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:23 PM PDT 24
Peak memory 224588 kb
Host smart-dd7b3605-18fb-4bd3-ad1f-60b264ed112c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873219476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.873219476
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3334252616
Short name T406
Test name
Test status
Simulation time 25198285 ps
CPU time 0.78 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 215868 kb
Host smart-d1a5d077-48ff-41ea-9152-f47ccebb5e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334252616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3334252616
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2664882819
Short name T619
Test name
Test status
Simulation time 4073624230 ps
CPU time 13.5 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:21 PM PDT 24
Peak memory 232964 kb
Host smart-c421066f-2cca-4524-bd40-0947ca890d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664882819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2664882819
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3943111848
Short name T217
Test name
Test status
Simulation time 64451509416 ps
CPU time 51.39 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 232976 kb
Host smart-fcb1f521-2c44-4e19-9f3c-9b6d6866248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943111848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3943111848
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1839703417
Short name T808
Test name
Test status
Simulation time 245916400 ps
CPU time 2.95 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:10 PM PDT 24
Peak memory 232836 kb
Host smart-f4ecb97c-2c1d-4591-a010-b69987c0e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839703417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1839703417
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2809187959
Short name T239
Test name
Test status
Simulation time 994531225 ps
CPU time 3.64 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:11 PM PDT 24
Peak memory 224532 kb
Host smart-48a4631e-5fc0-40e2-a577-6869b65c868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809187959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2809187959
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1717552119
Short name T615
Test name
Test status
Simulation time 3131407849 ps
CPU time 7.41 seconds
Started Jul 28 05:32:09 PM PDT 24
Finished Jul 28 05:32:17 PM PDT 24
Peak memory 222848 kb
Host smart-16c5b8e2-e837-43d8-9c91-a680ae5116c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1717552119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1717552119
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.436462381
Short name T65
Test name
Test status
Simulation time 390039494 ps
CPU time 0.97 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:08 PM PDT 24
Peak memory 235740 kb
Host smart-5d52fddd-bb8e-4d2b-b466-f74669218cff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436462381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.436462381
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2500619654
Short name T1005
Test name
Test status
Simulation time 2371466093 ps
CPU time 20.11 seconds
Started Jul 28 05:32:11 PM PDT 24
Finished Jul 28 05:32:31 PM PDT 24
Peak memory 216152 kb
Host smart-3d90e1a0-a52d-4b86-8286-cdd1536a3974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500619654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2500619654
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3625522274
Short name T786
Test name
Test status
Simulation time 4933238030 ps
CPU time 10.02 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:17 PM PDT 24
Peak memory 216404 kb
Host smart-42f075ea-202a-4795-a8cc-7ad5c5b043f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625522274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3625522274
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.346568156
Short name T783
Test name
Test status
Simulation time 178623527 ps
CPU time 3.1 seconds
Started Jul 28 05:32:07 PM PDT 24
Finished Jul 28 05:32:10 PM PDT 24
Peak memory 216388 kb
Host smart-d662296c-3bbb-4f02-b07a-2838f0e4292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346568156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.346568156
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.604356618
Short name T818
Test name
Test status
Simulation time 79296579 ps
CPU time 0.95 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:07 PM PDT 24
Peak memory 206100 kb
Host smart-9dfdc461-f375-49de-ab80-34b9c0219f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604356618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.604356618
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.934312493
Short name T726
Test name
Test status
Simulation time 2733963673 ps
CPU time 7.78 seconds
Started Jul 28 05:32:06 PM PDT 24
Finished Jul 28 05:32:14 PM PDT 24
Peak memory 224644 kb
Host smart-b01ac7da-553a-456b-b4b1-14e0b8d85a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934312493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.934312493
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.867811628
Short name T955
Test name
Test status
Simulation time 11468245 ps
CPU time 0.77 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 204900 kb
Host smart-40922b12-4f9f-44f4-9dad-5fbe4f9d70f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867811628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.867811628
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2172230642
Short name T705
Test name
Test status
Simulation time 78518434 ps
CPU time 2.47 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 224664 kb
Host smart-cebe2d4c-9741-44d1-ba75-af57a736dcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172230642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2172230642
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3832899659
Short name T395
Test name
Test status
Simulation time 34662155 ps
CPU time 0.76 seconds
Started Jul 28 05:32:37 PM PDT 24
Finished Jul 28 05:32:38 PM PDT 24
Peak memory 206652 kb
Host smart-7f34aed4-e77f-4d4c-aeab-ea1d681f19f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832899659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3832899659
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1745806064
Short name T527
Test name
Test status
Simulation time 3631153821 ps
CPU time 90.19 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:34:18 PM PDT 24
Peak memory 256304 kb
Host smart-9a17b6a2-3976-4655-940b-ac2bb31afae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745806064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1745806064
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.706904251
Short name T333
Test name
Test status
Simulation time 645133360 ps
CPU time 8.44 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:32:57 PM PDT 24
Peak memory 249276 kb
Host smart-f0873929-7bd2-4c3c-8dd6-7d65f049c989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706904251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.706904251
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1783742284
Short name T47
Test name
Test status
Simulation time 2380113667 ps
CPU time 31.92 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:33:22 PM PDT 24
Peak memory 241176 kb
Host smart-65d0af7d-dc34-4bea-9e44-892892a76485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783742284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1783742284
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.92834694
Short name T573
Test name
Test status
Simulation time 1599070764 ps
CPU time 3.79 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 232824 kb
Host smart-a132f75e-f7bf-40bc-b2ec-1c5062f3a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92834694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.92834694
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1598560996
Short name T243
Test name
Test status
Simulation time 95834403935 ps
CPU time 55.13 seconds
Started Jul 28 05:32:38 PM PDT 24
Finished Jul 28 05:33:33 PM PDT 24
Peak memory 224740 kb
Host smart-21cd2877-fd45-4596-b69e-ccc5a03173b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598560996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1598560996
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4077640353
Short name T559
Test name
Test status
Simulation time 85153532 ps
CPU time 2.71 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:32:48 PM PDT 24
Peak memory 232940 kb
Host smart-8cc71beb-c208-4bb8-9bc2-6c48422a1723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077640353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4077640353
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3809499980
Short name T457
Test name
Test status
Simulation time 3275636510 ps
CPU time 11.51 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 224700 kb
Host smart-3f6fc7b5-7984-4c4d-a0d8-80db621b81db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809499980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3809499980
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4123118590
Short name T930
Test name
Test status
Simulation time 483167021 ps
CPU time 6.29 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:54 PM PDT 24
Peak memory 223108 kb
Host smart-11e68be9-ecbf-48fd-a8fd-7eb0a2813985
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4123118590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4123118590
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1189210861
Short name T220
Test name
Test status
Simulation time 11218911395 ps
CPU time 98.63 seconds
Started Jul 28 05:32:45 PM PDT 24
Finished Jul 28 05:34:24 PM PDT 24
Peak memory 253328 kb
Host smart-3cbe19d7-de47-4656-b9ca-d32ee40ceab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189210861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1189210861
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2173515645
Short name T425
Test name
Test status
Simulation time 3697814024 ps
CPU time 22.2 seconds
Started Jul 28 05:32:38 PM PDT 24
Finished Jul 28 05:33:00 PM PDT 24
Peak memory 216456 kb
Host smart-e381008c-be3d-4644-8103-3ddcb4a5a049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173515645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2173515645
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2875475072
Short name T567
Test name
Test status
Simulation time 1362162122 ps
CPU time 4.26 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 216420 kb
Host smart-63dc5cf3-832e-4f4a-8e8d-fa861166c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875475072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2875475072
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.719448294
Short name T318
Test name
Test status
Simulation time 471567577 ps
CPU time 2.29 seconds
Started Jul 28 05:32:52 PM PDT 24
Finished Jul 28 05:32:55 PM PDT 24
Peak memory 216436 kb
Host smart-8a6ba6a9-8713-4f91-9365-d804907c39a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719448294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.719448294
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1788483106
Short name T26
Test name
Test status
Simulation time 17730098 ps
CPU time 0.75 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 206088 kb
Host smart-145a3584-d714-43aa-9577-b1495fcb0688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788483106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1788483106
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2531112633
Short name T931
Test name
Test status
Simulation time 208889060 ps
CPU time 5.76 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:56 PM PDT 24
Peak memory 232816 kb
Host smart-e2a99bce-e2a8-4d44-9d50-bce9aaa8fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531112633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2531112633
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1418965107
Short name T922
Test name
Test status
Simulation time 95895530 ps
CPU time 0.71 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 204992 kb
Host smart-8a5833d9-4377-40e2-9ab6-36640277a70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418965107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1418965107
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2385381455
Short name T455
Test name
Test status
Simulation time 644380881 ps
CPU time 8.57 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 232876 kb
Host smart-690df8e3-bc37-4e5f-b093-02aa179b7710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385381455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2385381455
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1788060852
Short name T958
Test name
Test status
Simulation time 16428318 ps
CPU time 0.82 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 207052 kb
Host smart-29773828-3a94-4e9b-a813-f638bf672089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788060852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1788060852
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.483331047
Short name T112
Test name
Test status
Simulation time 123755078616 ps
CPU time 227.08 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:36:36 PM PDT 24
Peak memory 249256 kb
Host smart-fe25af1e-ec3b-4506-bb4d-0a64f693f6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483331047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.483331047
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2844917219
Short name T890
Test name
Test status
Simulation time 292501942568 ps
CPU time 717.02 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:44:44 PM PDT 24
Peak memory 255024 kb
Host smart-d13db560-2c0f-40d3-9b05-783b16cf0d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844917219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2844917219
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3086529592
Short name T70
Test name
Test status
Simulation time 20406967870 ps
CPU time 108.78 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:34:39 PM PDT 24
Peak memory 261060 kb
Host smart-3ba215a8-cd14-42e8-99e0-cb1df8519ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086529592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3086529592
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.209998945
Short name T130
Test name
Test status
Simulation time 6973061860 ps
CPU time 17.44 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:33:08 PM PDT 24
Peak memory 232912 kb
Host smart-d9be433b-7235-4751-8c59-1286c9eb956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209998945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.209998945
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3556742337
Short name T149
Test name
Test status
Simulation time 31143293438 ps
CPU time 43.64 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:33:33 PM PDT 24
Peak memory 234424 kb
Host smart-f5969967-34b1-4c6d-bde6-d372d24b2427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556742337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3556742337
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1511683947
Short name T986
Test name
Test status
Simulation time 7691150785 ps
CPU time 21.9 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:33:11 PM PDT 24
Peak memory 232976 kb
Host smart-ce3c68ae-12fd-44ab-b877-8c8b51f38e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511683947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1511683947
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2063887767
Short name T816
Test name
Test status
Simulation time 1325499465 ps
CPU time 7.96 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:57 PM PDT 24
Peak memory 224688 kb
Host smart-84c9d37f-1d12-44b2-b1b8-9f5ebde40500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063887767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2063887767
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4102678057
Short name T850
Test name
Test status
Simulation time 112179604 ps
CPU time 2.65 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 232484 kb
Host smart-5a0e0553-28f5-4ac6-9dfa-f4e7fa34fe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102678057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4102678057
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4003655685
Short name T256
Test name
Test status
Simulation time 182976109 ps
CPU time 2.57 seconds
Started Jul 28 05:32:48 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 224504 kb
Host smart-4f6dc5c8-8356-468a-8301-a2b8fa0e4b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003655685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4003655685
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2216218567
Short name T127
Test name
Test status
Simulation time 117220884 ps
CPU time 3.79 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 219424 kb
Host smart-4ce4a73c-d62d-4862-88f3-caea1152cd87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2216218567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2216218567
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3349856337
Short name T719
Test name
Test status
Simulation time 13318889904 ps
CPU time 84.55 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 268012 kb
Host smart-2671765f-f854-4b5d-95f5-0a69a6463486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349856337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3349856337
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.414331973
Short name T1010
Test name
Test status
Simulation time 380884107 ps
CPU time 2.51 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 216292 kb
Host smart-b51be4a4-1358-4f12-8117-f0b26041ceb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414331973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.414331973
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.297709144
Short name T520
Test name
Test status
Simulation time 25233325 ps
CPU time 0.91 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:49 PM PDT 24
Peak memory 206696 kb
Host smart-36173c9b-f265-4ca6-ba02-4557e4169f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297709144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.297709144
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2290726267
Short name T648
Test name
Test status
Simulation time 55070637 ps
CPU time 0.76 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 206052 kb
Host smart-99209fa1-6e52-4f2b-a7aa-f41e35aaca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290726267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2290726267
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1206094796
Short name T343
Test name
Test status
Simulation time 53540630 ps
CPU time 1.93 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 223772 kb
Host smart-c6f4c1c5-e912-44f4-baf5-28fc630dcefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206094796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1206094796
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2412883442
Short name T652
Test name
Test status
Simulation time 14357450 ps
CPU time 0.72 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:32:58 PM PDT 24
Peak memory 204976 kb
Host smart-88536180-ffc0-4810-a7d4-94c6fbb04c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412883442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2412883442
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3765029811
Short name T854
Test name
Test status
Simulation time 3074787013 ps
CPU time 18.2 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:33:07 PM PDT 24
Peak memory 224744 kb
Host smart-05eaafbd-a871-4c44-b28f-3e29a0414291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765029811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3765029811
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2286689631
Short name T918
Test name
Test status
Simulation time 20479218 ps
CPU time 0.77 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:50 PM PDT 24
Peak memory 206972 kb
Host smart-73b4858a-60ee-4304-bd21-3583bccb0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286689631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2286689631
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3123999309
Short name T649
Test name
Test status
Simulation time 1895217304 ps
CPU time 13.44 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:33:03 PM PDT 24
Peak memory 224616 kb
Host smart-182381da-1137-4b28-9504-7ca61875efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123999309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3123999309
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2443451355
Short name T213
Test name
Test status
Simulation time 19772048720 ps
CPU time 131.74 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 264556 kb
Host smart-782f8b24-b0f6-45fb-9111-c9cfe1d09657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443451355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2443451355
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2485807629
Short name T221
Test name
Test status
Simulation time 879640566 ps
CPU time 5.66 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:55 PM PDT 24
Peak memory 224692 kb
Host smart-c7c91d7c-ac4e-4cb4-9846-9f6ee64c5013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485807629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2485807629
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3406442583
Short name T276
Test name
Test status
Simulation time 189664708800 ps
CPU time 220.34 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:36:31 PM PDT 24
Peak memory 251608 kb
Host smart-f296ab5e-7fe3-4ad0-9d74-04aad4c2ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406442583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3406442583
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.215834591
Short name T987
Test name
Test status
Simulation time 58972634902 ps
CPU time 26.17 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:33:15 PM PDT 24
Peak memory 224700 kb
Host smart-d33a5e2d-26e8-4028-bbdd-ea38cb43924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215834591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.215834591
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1333140169
Short name T677
Test name
Test status
Simulation time 4325694236 ps
CPU time 7.43 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:57 PM PDT 24
Peak memory 232892 kb
Host smart-c8c8d6ff-0213-4f14-b1a8-d643e9ed6a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333140169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1333140169
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2182950126
Short name T992
Test name
Test status
Simulation time 2828211147 ps
CPU time 7.32 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 232904 kb
Host smart-a1fad571-ecf5-4dd8-b0a0-a999f2b2c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182950126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2182950126
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2568626864
Short name T917
Test name
Test status
Simulation time 3131680352 ps
CPU time 5.05 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:56 PM PDT 24
Peak memory 222812 kb
Host smart-1bb7ef47-6288-4217-8bf9-9f8b4ccfb0d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2568626864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2568626864
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.580316888
Short name T141
Test name
Test status
Simulation time 63645649 ps
CPU time 1.01 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 206976 kb
Host smart-e42049d8-961a-4757-a048-f5ea44010358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580316888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.580316888
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.864977616
Short name T487
Test name
Test status
Simulation time 45391280 ps
CPU time 0.71 seconds
Started Jul 28 05:32:45 PM PDT 24
Finished Jul 28 05:32:46 PM PDT 24
Peak memory 205796 kb
Host smart-7693a511-972f-41d5-9b1e-406394b7f7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864977616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.864977616
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.768784036
Short name T741
Test name
Test status
Simulation time 37796574 ps
CPU time 0.93 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:50 PM PDT 24
Peak memory 207140 kb
Host smart-5e6549b3-3bf3-4260-bd19-266f5a572bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768784036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.768784036
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3545634297
Short name T725
Test name
Test status
Simulation time 29644182 ps
CPU time 0.71 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 206100 kb
Host smart-b4c16c1e-3d2a-4196-b716-e1f7249dfc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545634297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3545634297
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1291503030
Short name T269
Test name
Test status
Simulation time 3612523870 ps
CPU time 8.55 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:58 PM PDT 24
Peak memory 232824 kb
Host smart-4628974f-c4c8-4a6b-95ba-f6394f944b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291503030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1291503030
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.72936957
Short name T6
Test name
Test status
Simulation time 4532354163 ps
CPU time 10.24 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 224756 kb
Host smart-3e584fe1-7f90-4927-a5c4-98087c64f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72936957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.72936957
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2814158619
Short name T342
Test name
Test status
Simulation time 21830923 ps
CPU time 0.83 seconds
Started Jul 28 05:32:52 PM PDT 24
Finished Jul 28 05:32:53 PM PDT 24
Peak memory 206660 kb
Host smart-bb44c4f9-8344-43c1-b9d8-877f69e3c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814158619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2814158619
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2058723807
Short name T857
Test name
Test status
Simulation time 9850979653 ps
CPU time 28.05 seconds
Started Jul 28 05:32:53 PM PDT 24
Finished Jul 28 05:33:22 PM PDT 24
Peak memory 241020 kb
Host smart-6486ccc8-f706-4ae9-a7d8-3aaa45b43a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058723807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2058723807
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3517680214
Short name T828
Test name
Test status
Simulation time 2134288710 ps
CPU time 19.97 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:33:15 PM PDT 24
Peak memory 241060 kb
Host smart-3b71ee41-1290-4786-b277-2076f9b002f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517680214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3517680214
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1445455224
Short name T296
Test name
Test status
Simulation time 11654159049 ps
CPU time 47.94 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:33:43 PM PDT 24
Peak memory 233940 kb
Host smart-799e4408-9a39-4779-a521-440a8a5c0788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445455224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1445455224
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1885640289
Short name T484
Test name
Test status
Simulation time 37520008485 ps
CPU time 128.78 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 254400 kb
Host smart-eeab5fae-a385-480d-8fbe-7b0f0cc81456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885640289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1885640289
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1761384314
Short name T328
Test name
Test status
Simulation time 29105681 ps
CPU time 2.51 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:32:58 PM PDT 24
Peak memory 232480 kb
Host smart-3f51a3f4-d10b-4834-9ee4-66113136c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761384314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1761384314
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2947365823
Short name T445
Test name
Test status
Simulation time 4094530818 ps
CPU time 37.27 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 238036 kb
Host smart-4301de36-c16b-4255-8a27-017ce49d5fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947365823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2947365823
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1106898988
Short name T989
Test name
Test status
Simulation time 1398684421 ps
CPU time 6.81 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:57 PM PDT 24
Peak memory 232744 kb
Host smart-de503d1c-c19b-465f-a289-198ca60d1a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106898988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1106898988
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1238050944
Short name T267
Test name
Test status
Simulation time 1576212316 ps
CPU time 6.9 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:58 PM PDT 24
Peak memory 240164 kb
Host smart-f6b0b641-2cdb-4916-9d2d-e0ded4b345db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238050944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1238050944
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.869855602
Short name T458
Test name
Test status
Simulation time 5175352966 ps
CPU time 10.85 seconds
Started Jul 28 05:32:55 PM PDT 24
Finished Jul 28 05:33:06 PM PDT 24
Peak memory 223360 kb
Host smart-d8f857fe-8504-4687-9c00-1df2ce7b1494
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=869855602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.869855602
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3831147324
Short name T944
Test name
Test status
Simulation time 300889793 ps
CPU time 1.23 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 207220 kb
Host smart-5817090d-7355-4a12-ba62-f5f3faa92bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831147324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3831147324
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1972636412
Short name T314
Test name
Test status
Simulation time 5865744631 ps
CPU time 12.59 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:33:04 PM PDT 24
Peak memory 216544 kb
Host smart-97aef423-6d5d-4198-a089-f5302343763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972636412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1972636412
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1748274606
Short name T337
Test name
Test status
Simulation time 5345676056 ps
CPU time 10.97 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:33:02 PM PDT 24
Peak memory 216528 kb
Host smart-9489a5ed-64ad-4571-a653-5c35aad12818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748274606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1748274606
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3466211492
Short name T347
Test name
Test status
Simulation time 124581930 ps
CPU time 4.1 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 216428 kb
Host smart-f083dda1-3041-431b-86fd-588d880fdd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466211492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3466211492
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3287074393
Short name T820
Test name
Test status
Simulation time 17743740 ps
CPU time 0.78 seconds
Started Jul 28 05:33:04 PM PDT 24
Finished Jul 28 05:33:05 PM PDT 24
Peak memory 206080 kb
Host smart-cd78758c-14fc-4f7e-a856-679422f95090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287074393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3287074393
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3439580518
Short name T789
Test name
Test status
Simulation time 48653439 ps
CPU time 2.39 seconds
Started Jul 28 05:33:04 PM PDT 24
Finished Jul 28 05:33:07 PM PDT 24
Peak memory 217488 kb
Host smart-7d7d9c4e-f22b-494a-84f6-d08f8d124ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439580518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3439580518
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3492968687
Short name T438
Test name
Test status
Simulation time 11744949 ps
CPU time 0.72 seconds
Started Jul 28 05:33:00 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 205016 kb
Host smart-39a6e4e1-1d56-407b-964f-4e889e036998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492968687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3492968687
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3714021002
Short name T671
Test name
Test status
Simulation time 119800562 ps
CPU time 2.67 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 232828 kb
Host smart-a6a5d453-145d-4371-9a3f-86401476c6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714021002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3714021002
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1110226500
Short name T865
Test name
Test status
Simulation time 13629878 ps
CPU time 0.79 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:32:58 PM PDT 24
Peak memory 206684 kb
Host smart-1c7f8a9b-51d5-4a62-9ed8-c917a57112aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110226500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1110226500
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1689813948
Short name T40
Test name
Test status
Simulation time 21349179288 ps
CPU time 49.55 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:33:56 PM PDT 24
Peak memory 241064 kb
Host smart-001d6516-2c45-433d-a533-622c1e87f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689813948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1689813948
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.420254503
Short name T667
Test name
Test status
Simulation time 41681962547 ps
CPU time 186.71 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:36:04 PM PDT 24
Peak memory 266752 kb
Host smart-fd88d998-73eb-4900-ac7f-7a2d998d0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420254503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.420254503
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2737299591
Short name T461
Test name
Test status
Simulation time 83468019349 ps
CPU time 91.4 seconds
Started Jul 28 05:33:00 PM PDT 24
Finished Jul 28 05:34:31 PM PDT 24
Peak memory 241140 kb
Host smart-60370071-6253-4d1a-b340-2a7a3d216d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737299591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2737299591
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2863257482
Short name T302
Test name
Test status
Simulation time 1157093773 ps
CPU time 9.82 seconds
Started Jul 28 05:33:10 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 240508 kb
Host smart-52308682-7c9d-4613-b645-941cded5836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863257482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2863257482
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1897047221
Short name T212
Test name
Test status
Simulation time 3252188936 ps
CPU time 43.06 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:42 PM PDT 24
Peak memory 249428 kb
Host smart-49f5647d-6559-4053-93a2-0410647d46e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897047221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1897047221
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.175638941
Short name T193
Test name
Test status
Simulation time 79906540 ps
CPU time 3.43 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:03 PM PDT 24
Peak memory 232828 kb
Host smart-37294064-9a33-4d86-a2b2-64a2b4faf403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175638941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.175638941
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2670411449
Short name T503
Test name
Test status
Simulation time 569697995 ps
CPU time 2.88 seconds
Started Jul 28 05:33:02 PM PDT 24
Finished Jul 28 05:33:05 PM PDT 24
Peak memory 224652 kb
Host smart-bae9d75c-ef97-4ba3-8c29-6033efa44209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670411449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2670411449
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.951451913
Short name T197
Test name
Test status
Simulation time 2136668533 ps
CPU time 12.39 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:11 PM PDT 24
Peak memory 240748 kb
Host smart-1a8b69d7-4790-435f-8f0f-0d5abbf3c539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951451913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.951451913
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2365343654
Short name T715
Test name
Test status
Simulation time 287872559 ps
CPU time 7.18 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:06 PM PDT 24
Peak memory 240708 kb
Host smart-c26e4314-e3c2-4f07-9ce9-7dcb53012a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365343654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2365343654
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.310774972
Short name T680
Test name
Test status
Simulation time 683262548 ps
CPU time 4.06 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:02 PM PDT 24
Peak memory 218956 kb
Host smart-6554b0b2-915d-4674-b275-a86d583a48c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310774972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.310774972
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2449998215
Short name T448
Test name
Test status
Simulation time 5402241540 ps
CPU time 36.64 seconds
Started Jul 28 05:33:00 PM PDT 24
Finished Jul 28 05:33:37 PM PDT 24
Peak memory 216612 kb
Host smart-47ffec23-a60c-4114-bb89-0b5c0261d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449998215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2449998215
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.147153299
Short name T405
Test name
Test status
Simulation time 1470732458 ps
CPU time 4.64 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:03 PM PDT 24
Peak memory 216332 kb
Host smart-626334dc-0ec2-47d3-be32-803bb5e0f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147153299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.147153299
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3214741538
Short name T616
Test name
Test status
Simulation time 482450155 ps
CPU time 8.05 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:06 PM PDT 24
Peak memory 216452 kb
Host smart-a1d9f3be-13d6-4bd8-9a9c-bd07a6e06939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214741538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3214741538
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2923728962
Short name T926
Test name
Test status
Simulation time 30932952 ps
CPU time 0.72 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 206088 kb
Host smart-2de48fa1-1c4b-455c-93bb-0edefbf3ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923728962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2923728962
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.23858605
Short name T580
Test name
Test status
Simulation time 1869512837 ps
CPU time 8.97 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:07 PM PDT 24
Peak memory 232812 kb
Host smart-657c96bf-a932-4969-8d94-04d0fe491bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23858605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.23858605
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1495458367
Short name T413
Test name
Test status
Simulation time 14293055 ps
CPU time 0.72 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:33:07 PM PDT 24
Peak memory 205532 kb
Host smart-06227c7d-a8e0-469f-9323-bd1bfd600f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495458367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1495458367
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2800750998
Short name T687
Test name
Test status
Simulation time 111672147 ps
CPU time 2.56 seconds
Started Jul 28 05:32:57 PM PDT 24
Finished Jul 28 05:33:00 PM PDT 24
Peak memory 232828 kb
Host smart-28c8a31a-e037-49a7-b5ca-0a86b3749980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800750998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2800750998
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.19769133
Short name T754
Test name
Test status
Simulation time 34453467 ps
CPU time 0.81 seconds
Started Jul 28 05:33:00 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 206996 kb
Host smart-922e0bed-046a-49a0-a5f5-1ccb080da55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19769133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.19769133
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3041375412
Short name T998
Test name
Test status
Simulation time 4431817073 ps
CPU time 31.45 seconds
Started Jul 28 05:33:07 PM PDT 24
Finished Jul 28 05:33:39 PM PDT 24
Peak memory 249652 kb
Host smart-1a529d23-56dd-4a35-9bff-1dae52777297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041375412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3041375412
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.890481573
Short name T52
Test name
Test status
Simulation time 9954895312 ps
CPU time 127.31 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:35:14 PM PDT 24
Peak memory 272912 kb
Host smart-11623e3b-879f-4706-88b0-9a66fdb7a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890481573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.890481573
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2136346129
Short name T411
Test name
Test status
Simulation time 177462775559 ps
CPU time 182.62 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:36:09 PM PDT 24
Peak memory 255292 kb
Host smart-3adaa6f4-e74e-461c-87bf-bdfd52e929a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136346129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2136346129
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2553656741
Short name T298
Test name
Test status
Simulation time 200055038 ps
CPU time 6.46 seconds
Started Jul 28 05:33:07 PM PDT 24
Finished Jul 28 05:33:13 PM PDT 24
Peak memory 224612 kb
Host smart-edc49c73-e6c1-4cfa-a6b7-8046041d50fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553656741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2553656741
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3141977309
Short name T817
Test name
Test status
Simulation time 66262165888 ps
CPU time 476.48 seconds
Started Jul 28 05:33:04 PM PDT 24
Finished Jul 28 05:41:01 PM PDT 24
Peak memory 257468 kb
Host smart-257987ad-2d22-4915-a053-fe8b0a3cff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141977309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3141977309
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4219313621
Short name T633
Test name
Test status
Simulation time 733181845 ps
CPU time 9.31 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:08 PM PDT 24
Peak memory 232864 kb
Host smart-0a108998-20d0-4ffb-ac4d-64d27859fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219313621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4219313621
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1698702711
Short name T708
Test name
Test status
Simulation time 36248317613 ps
CPU time 48.13 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 236976 kb
Host smart-d2c692e1-994d-45f9-816d-82f92e77da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698702711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1698702711
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2766266631
Short name T454
Test name
Test status
Simulation time 1024405886 ps
CPU time 4.4 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:03 PM PDT 24
Peak memory 224612 kb
Host smart-5c97c3b6-2a67-4545-9e75-a5358eb38c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766266631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2766266631
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3399272819
Short name T452
Test name
Test status
Simulation time 257753144 ps
CPU time 2.1 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:02 PM PDT 24
Peak memory 223004 kb
Host smart-bdd1e315-f9ca-4a95-b33d-9f37175d6fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399272819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3399272819
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1439842877
Short name T655
Test name
Test status
Simulation time 330829223 ps
CPU time 6.13 seconds
Started Jul 28 05:33:04 PM PDT 24
Finished Jul 28 05:33:10 PM PDT 24
Peak memory 223052 kb
Host smart-90ade6c8-80ff-4eed-8c33-57c9ceea4571
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1439842877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1439842877
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2145140716
Short name T773
Test name
Test status
Simulation time 78879995668 ps
CPU time 224.56 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 254412 kb
Host smart-ffe0c63b-30a8-43a3-9094-a6faa540ddef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145140716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2145140716
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3535138178
Short name T882
Test name
Test status
Simulation time 5938320314 ps
CPU time 17.38 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:17 PM PDT 24
Peak memory 216528 kb
Host smart-84ef3855-3c12-4349-9beb-aae802fc5413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535138178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3535138178
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3118089866
Short name T952
Test name
Test status
Simulation time 644785881 ps
CPU time 3.63 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:02 PM PDT 24
Peak memory 216436 kb
Host smart-b5222c4a-df9c-46bf-8f43-0bf78989b22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118089866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3118089866
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1728397607
Short name T908
Test name
Test status
Simulation time 272984102 ps
CPU time 1.44 seconds
Started Jul 28 05:32:59 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 216320 kb
Host smart-de748eac-65ae-4318-8000-cbd54ee73e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728397607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1728397607
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2792516096
Short name T877
Test name
Test status
Simulation time 152054080 ps
CPU time 0.91 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 207124 kb
Host smart-9766c9f4-6649-4bc5-9a16-d5f6867c96ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792516096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2792516096
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3564769418
Short name T199
Test name
Test status
Simulation time 380149642 ps
CPU time 4.38 seconds
Started Jul 28 05:32:58 PM PDT 24
Finished Jul 28 05:33:02 PM PDT 24
Peak memory 232844 kb
Host smart-d50dc444-9481-4b23-810b-f2c508078790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564769418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3564769418
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2993987111
Short name T410
Test name
Test status
Simulation time 11899983 ps
CPU time 0.71 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:13 PM PDT 24
Peak memory 205544 kb
Host smart-7123d99a-518e-44a6-8e7b-96478fe6daa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993987111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2993987111
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3005134278
Short name T247
Test name
Test status
Simulation time 23542144113 ps
CPU time 11.76 seconds
Started Jul 28 05:33:09 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 232836 kb
Host smart-58a0523e-4150-4ddd-a829-a082434910bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005134278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3005134278
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1838728756
Short name T606
Test name
Test status
Simulation time 63429156 ps
CPU time 0.77 seconds
Started Jul 28 05:33:07 PM PDT 24
Finished Jul 28 05:33:08 PM PDT 24
Peak memory 205692 kb
Host smart-d7dd2d58-ac64-49fc-a268-59bb23f676d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838728756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1838728756
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2544981982
Short name T971
Test name
Test status
Simulation time 18972473 ps
CPU time 0.77 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:33:07 PM PDT 24
Peak memory 215780 kb
Host smart-af45b9b6-43e4-43b5-af18-cc631b2ac40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544981982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2544981982
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1415815361
Short name T806
Test name
Test status
Simulation time 41391636752 ps
CPU time 227.93 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 256104 kb
Host smart-6808c339-5522-45b6-8a03-29f4ae07b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415815361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1415815361
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.128941056
Short name T489
Test name
Test status
Simulation time 20898043067 ps
CPU time 199.63 seconds
Started Jul 28 05:33:04 PM PDT 24
Finished Jul 28 05:36:24 PM PDT 24
Peak memory 250368 kb
Host smart-7d13498d-ba70-44b1-a584-b1f9696ae969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128941056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.128941056
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2182305524
Short name T476
Test name
Test status
Simulation time 1174331799 ps
CPU time 19.66 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 237168 kb
Host smart-a720ded3-5794-4996-85a9-f365be3ce50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182305524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2182305524
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3539816449
Short name T623
Test name
Test status
Simulation time 19982329051 ps
CPU time 103.58 seconds
Started Jul 28 05:33:03 PM PDT 24
Finished Jul 28 05:34:47 PM PDT 24
Peak memory 257480 kb
Host smart-df93a8b8-e8e3-4fdf-9a53-7f73ae3feee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539816449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3539816449
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3785978025
Short name T811
Test name
Test status
Simulation time 243831789 ps
CPU time 6.61 seconds
Started Jul 28 05:33:07 PM PDT 24
Finished Jul 28 05:33:14 PM PDT 24
Peak memory 232836 kb
Host smart-fd0fbe3a-ca4f-492a-91e3-0935ec246e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785978025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3785978025
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.405502202
Short name T236
Test name
Test status
Simulation time 21677451155 ps
CPU time 82.47 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 233700 kb
Host smart-c927e724-f17f-469b-962b-68ba8432eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405502202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.405502202
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1407602824
Short name T208
Test name
Test status
Simulation time 26705707337 ps
CPU time 9.64 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:33:16 PM PDT 24
Peak memory 233124 kb
Host smart-87aa0a9a-c55d-4e5e-8bcf-61a18a29f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407602824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1407602824
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2407667273
Short name T640
Test name
Test status
Simulation time 2662507301 ps
CPU time 5.43 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:33:16 PM PDT 24
Peak memory 224708 kb
Host smart-985fb2d7-3597-46db-96e2-f261b9029933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407667273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2407667273
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2679192580
Short name T979
Test name
Test status
Simulation time 3869020359 ps
CPU time 6.82 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:33:12 PM PDT 24
Peak memory 219332 kb
Host smart-4d20c9fa-b5d8-4a55-8a40-a2948c919bf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2679192580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2679192580
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.452998020
Short name T1012
Test name
Test status
Simulation time 34657585764 ps
CPU time 116.89 seconds
Started Jul 28 05:33:04 PM PDT 24
Finished Jul 28 05:35:01 PM PDT 24
Peak memory 249360 kb
Host smart-d2f613b0-2750-4827-b976-bfe77a26ab9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452998020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.452998020
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2889306604
Short name T310
Test name
Test status
Simulation time 13620444457 ps
CPU time 16.52 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:33:23 PM PDT 24
Peak memory 216732 kb
Host smart-84250a8c-fc86-4bba-8913-2edaf3ad76e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889306604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2889306604
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4036224820
Short name T417
Test name
Test status
Simulation time 2400830536 ps
CPU time 5.11 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:33:10 PM PDT 24
Peak memory 216484 kb
Host smart-c515d756-20e6-4b37-8d7a-611c4f20450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036224820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4036224820
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1575097116
Short name T956
Test name
Test status
Simulation time 103383688 ps
CPU time 0.9 seconds
Started Jul 28 05:33:08 PM PDT 24
Finished Jul 28 05:33:09 PM PDT 24
Peak memory 206120 kb
Host smart-6bb4dd36-f5b6-4ce0-980c-c0151ca12a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575097116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1575097116
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3607816145
Short name T909
Test name
Test status
Simulation time 115563804 ps
CPU time 0.83 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:33:06 PM PDT 24
Peak memory 207124 kb
Host smart-5a7f570d-b1a8-47bf-a450-18b30883182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607816145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3607816145
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.387176506
Short name T499
Test name
Test status
Simulation time 8235845688 ps
CPU time 17.2 seconds
Started Jul 28 05:33:06 PM PDT 24
Finished Jul 28 05:33:24 PM PDT 24
Peak memory 226192 kb
Host smart-234389cc-f444-4ae0-b6e6-d1ea39d70492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387176506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.387176506
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1130867966
Short name T784
Test name
Test status
Simulation time 16559599 ps
CPU time 0.73 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:14 PM PDT 24
Peak memory 205880 kb
Host smart-352d2131-8e35-427c-b28d-1f0048b31720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130867966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1130867966
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3534746349
Short name T651
Test name
Test status
Simulation time 146320340 ps
CPU time 4.47 seconds
Started Jul 28 05:33:14 PM PDT 24
Finished Jul 28 05:33:19 PM PDT 24
Peak memory 224644 kb
Host smart-ea5330ea-b7ba-4a48-98ae-a41c6450624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534746349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3534746349
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3502890173
Short name T415
Test name
Test status
Simulation time 30487606 ps
CPU time 0.85 seconds
Started Jul 28 05:33:05 PM PDT 24
Finished Jul 28 05:33:06 PM PDT 24
Peak memory 206652 kb
Host smart-cac53a24-019b-495b-8980-c00a28138e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502890173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3502890173
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.243837494
Short name T584
Test name
Test status
Simulation time 62179694192 ps
CPU time 73.27 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:34:27 PM PDT 24
Peak memory 241140 kb
Host smart-a9113ecb-8f40-4cb6-be5f-d2a0bd2d94a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243837494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.243837494
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2037858366
Short name T121
Test name
Test status
Simulation time 127353696517 ps
CPU time 172.34 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:36:04 PM PDT 24
Peak memory 250716 kb
Host smart-013bb2af-fe99-44b2-a4c0-9ede6a1f61fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037858366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2037858366
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.695297813
Short name T49
Test name
Test status
Simulation time 95114018403 ps
CPU time 443.54 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:40:35 PM PDT 24
Peak memory 265744 kb
Host smart-775ec795-753f-497d-92a6-f80559745148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695297813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.695297813
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1758364683
Short name T126
Test name
Test status
Simulation time 565968979 ps
CPU time 3.89 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:16 PM PDT 24
Peak memory 224636 kb
Host smart-be540999-4bcc-4e14-b3c6-6daf13998028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758364683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1758364683
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2735585859
Short name T165
Test name
Test status
Simulation time 35532626079 ps
CPU time 89.52 seconds
Started Jul 28 05:33:10 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 256004 kb
Host smart-9e044af2-1005-4bea-bbdc-8f8c10516ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735585859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2735585859
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.8789650
Short name T564
Test name
Test status
Simulation time 558344437 ps
CPU time 8.09 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 232868 kb
Host smart-78da8576-5c2f-4a46-b7e9-9d83d80c3100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8789650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.8789650
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.796325880
Short name T999
Test name
Test status
Simulation time 4353819540 ps
CPU time 22 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:35 PM PDT 24
Peak memory 250724 kb
Host smart-f7cec659-5ed7-4204-be74-57fe29a615c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796325880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.796325880
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1212285484
Short name T463
Test name
Test status
Simulation time 863107075 ps
CPU time 2.95 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:16 PM PDT 24
Peak memory 232744 kb
Host smart-80d8fb2c-edb8-4bd8-bbf2-0b17375fd140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212285484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1212285484
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.774305464
Short name T264
Test name
Test status
Simulation time 33877858600 ps
CPU time 16.95 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:30 PM PDT 24
Peak memory 224636 kb
Host smart-d1f50dc6-6ee9-435a-909b-8a52ab6a7b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774305464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.774305464
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1308783597
Short name T853
Test name
Test status
Simulation time 1928984856 ps
CPU time 13.57 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:33:25 PM PDT 24
Peak memory 222232 kb
Host smart-3b1bfc34-28e3-42b8-bf65-e1b115585ed1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308783597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1308783597
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.407963573
Short name T968
Test name
Test status
Simulation time 53801737694 ps
CPU time 455.59 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:40:47 PM PDT 24
Peak memory 264468 kb
Host smart-98905bd3-7d3e-4a79-825c-593a488ffe9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407963573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.407963573
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1451265696
Short name T978
Test name
Test status
Simulation time 4384988513 ps
CPU time 19.67 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 216452 kb
Host smart-bc97e388-efef-4a2f-b4c9-a914053c91d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451265696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1451265696
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3439709162
Short name T657
Test name
Test status
Simulation time 15455310732 ps
CPU time 12.59 seconds
Started Jul 28 05:33:07 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 216480 kb
Host smart-db7f3a10-f3eb-424a-88dd-d6bcd43ac935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439709162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3439709162
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.606534076
Short name T801
Test name
Test status
Simulation time 1383661593 ps
CPU time 3.8 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:33:15 PM PDT 24
Peak memory 216416 kb
Host smart-bda508b3-98f3-473f-9b3b-469eed36773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606534076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.606534076
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3450951733
Short name T514
Test name
Test status
Simulation time 211344075 ps
CPU time 1.13 seconds
Started Jul 28 05:33:14 PM PDT 24
Finished Jul 28 05:33:16 PM PDT 24
Peak memory 206556 kb
Host smart-46c63535-7531-47d9-8e31-e72a56cb2064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450951733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3450951733
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.90660771
Short name T665
Test name
Test status
Simulation time 868308796 ps
CPU time 2.54 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:33:14 PM PDT 24
Peak memory 224292 kb
Host smart-62162dce-00e5-448f-95bf-9e63362a5ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90660771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.90660771
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1789012015
Short name T766
Test name
Test status
Simulation time 25909594 ps
CPU time 0.76 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 205884 kb
Host smart-695c4248-6d81-429f-adea-f8b7a7b9921f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789012015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1789012015
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2068097527
Short name T490
Test name
Test status
Simulation time 138758626 ps
CPU time 3.13 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:16 PM PDT 24
Peak memory 224576 kb
Host smart-ba215955-e9ab-40ce-b9fd-9a8451faca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068097527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2068097527
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2826940732
Short name T788
Test name
Test status
Simulation time 14488606 ps
CPU time 0.79 seconds
Started Jul 28 05:33:10 PM PDT 24
Finished Jul 28 05:33:11 PM PDT 24
Peak memory 206728 kb
Host smart-2fafe69f-d86a-4221-895a-47b5f3b9bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826940732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2826940732
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1544695593
Short name T39
Test name
Test status
Simulation time 1303867570 ps
CPU time 14.38 seconds
Started Jul 28 05:33:20 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 237516 kb
Host smart-77fcba45-e385-412d-a374-c65241292e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544695593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1544695593
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2854107949
Short name T223
Test name
Test status
Simulation time 39920115938 ps
CPU time 387.9 seconds
Started Jul 28 05:33:18 PM PDT 24
Finished Jul 28 05:39:46 PM PDT 24
Peak memory 255460 kb
Host smart-babfe318-47b9-4fd7-b6e3-3fd94f1ebd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854107949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2854107949
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1635977193
Short name T620
Test name
Test status
Simulation time 19792473493 ps
CPU time 87.03 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:34:46 PM PDT 24
Peak memory 249308 kb
Host smart-206b2bc9-c107-4120-b4c6-e95c1ceaa3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635977193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1635977193
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3260045420
Short name T795
Test name
Test status
Simulation time 3832402843 ps
CPU time 8 seconds
Started Jul 28 05:33:21 PM PDT 24
Finished Jul 28 05:33:29 PM PDT 24
Peak memory 232912 kb
Host smart-e2507e3b-d83f-426c-a29f-6528b399d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260045420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3260045420
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2314031489
Short name T416
Test name
Test status
Simulation time 99228317 ps
CPU time 3.39 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:15 PM PDT 24
Peak memory 224644 kb
Host smart-afb06761-eb87-4cf9-965f-9aad4a08375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314031489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2314031489
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.588478299
Short name T593
Test name
Test status
Simulation time 609447287 ps
CPU time 10.88 seconds
Started Jul 28 05:33:12 PM PDT 24
Finished Jul 28 05:33:23 PM PDT 24
Peak memory 228844 kb
Host smart-185c75f9-b351-4605-9198-591a2f892f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588478299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.588478299
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3418915161
Short name T928
Test name
Test status
Simulation time 28158109883 ps
CPU time 24.89 seconds
Started Jul 28 05:33:14 PM PDT 24
Finished Jul 28 05:33:39 PM PDT 24
Peak memory 239496 kb
Host smart-8500fd85-1fc6-44eb-8c96-a8f8c59de1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418915161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3418915161
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3513805346
Short name T459
Test name
Test status
Simulation time 1481463890 ps
CPU time 5.05 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:33:17 PM PDT 24
Peak memory 232796 kb
Host smart-4280a335-0690-4568-98ed-68af88475f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513805346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3513805346
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2687638075
Short name T125
Test name
Test status
Simulation time 2633207459 ps
CPU time 6.45 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:33:25 PM PDT 24
Peak memory 220784 kb
Host smart-9540c3a5-8ef1-40a6-b42e-2a9db8eb7bbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2687638075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2687638075
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1150958928
Short name T530
Test name
Test status
Simulation time 6297314120 ps
CPU time 23.18 seconds
Started Jul 28 05:33:11 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 219984 kb
Host smart-22b1ee03-224c-448d-9075-9c28b3d36e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150958928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1150958928
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3555974764
Short name T604
Test name
Test status
Simulation time 1823225633 ps
CPU time 6.59 seconds
Started Jul 28 05:33:15 PM PDT 24
Finished Jul 28 05:33:22 PM PDT 24
Peak memory 216408 kb
Host smart-20753433-8d58-488b-ab5e-6f2ed9fee35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555974764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3555974764
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.283384683
Short name T364
Test name
Test status
Simulation time 446967957 ps
CPU time 1.4 seconds
Started Jul 28 05:33:16 PM PDT 24
Finished Jul 28 05:33:17 PM PDT 24
Peak memory 207924 kb
Host smart-e63cb110-01b5-49e1-a637-24182cd5d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283384683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.283384683
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1876224708
Short name T117
Test name
Test status
Simulation time 104799415 ps
CPU time 0.83 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:13 PM PDT 24
Peak memory 206096 kb
Host smart-92b2922f-1936-429f-be4a-73ff723c1f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876224708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1876224708
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.464248479
Short name T903
Test name
Test status
Simulation time 2136077858 ps
CPU time 7.59 seconds
Started Jul 28 05:33:13 PM PDT 24
Finished Jul 28 05:33:20 PM PDT 24
Peak memory 224564 kb
Host smart-4e0ac1a5-27b6-431d-b66f-3c36b21ffe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464248479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.464248479
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3708984162
Short name T331
Test name
Test status
Simulation time 38068339 ps
CPU time 0.76 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:29 PM PDT 24
Peak memory 205028 kb
Host smart-4d1549ab-5a96-4372-9ffe-8a5bb0913980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708984162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3708984162
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.75315599
Short name T483
Test name
Test status
Simulation time 3501600839 ps
CPU time 33.01 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 232908 kb
Host smart-e62dba03-fe44-4d02-b861-b71f99b069cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75315599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.75315599
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2845725506
Short name T626
Test name
Test status
Simulation time 19691948 ps
CPU time 0.8 seconds
Started Jul 28 05:33:20 PM PDT 24
Finished Jul 28 05:33:21 PM PDT 24
Peak memory 207016 kb
Host smart-c56ffdb8-3af0-4f5e-b050-c9163110ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845725506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2845725506
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2838137801
Short name T382
Test name
Test status
Simulation time 38136400 ps
CPU time 0.72 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:33:31 PM PDT 24
Peak memory 215912 kb
Host smart-20990055-6ac4-4986-90e2-54088d508873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838137801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2838137801
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3028176574
Short name T827
Test name
Test status
Simulation time 27211734526 ps
CPU time 198.17 seconds
Started Jul 28 05:33:26 PM PDT 24
Finished Jul 28 05:36:45 PM PDT 24
Peak memory 257544 kb
Host smart-7f3cea40-2666-4284-b7eb-cf2533e881fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028176574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3028176574
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3202693142
Short name T533
Test name
Test status
Simulation time 33530754036 ps
CPU time 150.03 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:36:00 PM PDT 24
Peak memory 257500 kb
Host smart-4a74d1a5-5eb7-44f8-befc-110631d58e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202693142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3202693142
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.625490669
Short name T16
Test name
Test status
Simulation time 247274626 ps
CPU time 5.85 seconds
Started Jul 28 05:33:19 PM PDT 24
Finished Jul 28 05:33:25 PM PDT 24
Peak memory 232884 kb
Host smart-b6c916bf-a377-49c0-aefd-e4f9d8001726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625490669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.625490669
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1094646455
Short name T419
Test name
Test status
Simulation time 1111323175 ps
CPU time 27.63 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:56 PM PDT 24
Peak memory 239024 kb
Host smart-1ff52173-98aa-4077-b644-ebcb57fb2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094646455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1094646455
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2195673840
Short name T575
Test name
Test status
Simulation time 3261200501 ps
CPU time 10.19 seconds
Started Jul 28 05:33:17 PM PDT 24
Finished Jul 28 05:33:27 PM PDT 24
Peak memory 224696 kb
Host smart-be334408-2945-46db-aabc-a50a15b29220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195673840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2195673840
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1470799019
Short name T702
Test name
Test status
Simulation time 19830492587 ps
CPU time 53.95 seconds
Started Jul 28 05:33:21 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 233316 kb
Host smart-d57e5252-35a1-499b-8f4e-d0f42800a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470799019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1470799019
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2898045832
Short name T792
Test name
Test status
Simulation time 68312492 ps
CPU time 2.73 seconds
Started Jul 28 05:33:18 PM PDT 24
Finished Jul 28 05:33:21 PM PDT 24
Peak memory 232568 kb
Host smart-48da2564-2f5c-41ac-bc7c-724d31774bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898045832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2898045832
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2855854506
Short name T218
Test name
Test status
Simulation time 1729894154 ps
CPU time 10.27 seconds
Started Jul 28 05:33:49 PM PDT 24
Finished Jul 28 05:33:59 PM PDT 24
Peak memory 232900 kb
Host smart-6b79044a-a353-458f-acc3-83caf0792a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855854506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2855854506
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.441827476
Short name T601
Test name
Test status
Simulation time 153188753 ps
CPU time 4.59 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 220848 kb
Host smart-fa30c1a2-4e92-4dd5-86f9-fc1dd36c8104
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=441827476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.441827476
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1996792424
Short name T18
Test name
Test status
Simulation time 42916974 ps
CPU time 1.03 seconds
Started Jul 28 05:33:27 PM PDT 24
Finished Jul 28 05:33:28 PM PDT 24
Peak memory 207212 kb
Host smart-d9d4ceee-0468-45bd-adef-75a03fcbf14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996792424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1996792424
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1577031270
Short name T634
Test name
Test status
Simulation time 14617224 ps
CPU time 0.76 seconds
Started Jul 28 05:33:20 PM PDT 24
Finished Jul 28 05:33:21 PM PDT 24
Peak memory 205744 kb
Host smart-58eed49c-66b0-47d9-9e5d-87473cdf750e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577031270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1577031270
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3486830244
Short name T614
Test name
Test status
Simulation time 4805879156 ps
CPU time 12.59 seconds
Started Jul 28 05:33:20 PM PDT 24
Finished Jul 28 05:33:33 PM PDT 24
Peak memory 216644 kb
Host smart-9ca6d85d-a751-4ee1-8404-57a7822df716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486830244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3486830244
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3634889076
Short name T881
Test name
Test status
Simulation time 33111436 ps
CPU time 1.23 seconds
Started Jul 28 05:33:21 PM PDT 24
Finished Jul 28 05:33:22 PM PDT 24
Peak memory 208168 kb
Host smart-b23805d4-bc26-4ff2-b37d-522d1304a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634889076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3634889076
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1072418573
Short name T329
Test name
Test status
Simulation time 143518606 ps
CPU time 0.97 seconds
Started Jul 28 05:33:20 PM PDT 24
Finished Jul 28 05:33:21 PM PDT 24
Peak memory 207120 kb
Host smart-4ef0635a-4bb4-47e8-9818-b23e696c0f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072418573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1072418573
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1809169047
Short name T428
Test name
Test status
Simulation time 6903501488 ps
CPU time 17.99 seconds
Started Jul 28 05:33:20 PM PDT 24
Finished Jul 28 05:33:38 PM PDT 24
Peak memory 224760 kb
Host smart-852b5f9f-fffd-4a9b-a8e5-49c6cfea305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809169047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1809169047
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.12012756
Short name T785
Test name
Test status
Simulation time 109080852 ps
CPU time 0.83 seconds
Started Jul 28 05:32:19 PM PDT 24
Finished Jul 28 05:32:20 PM PDT 24
Peak memory 205860 kb
Host smart-03936db0-825c-4005-b77a-01966d860339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12012756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.12012756
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.271672264
Short name T630
Test name
Test status
Simulation time 282743808 ps
CPU time 2.67 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:20 PM PDT 24
Peak memory 224552 kb
Host smart-0e4e11c7-f4f4-4060-9293-5fb8f95667d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271672264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.271672264
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.516517045
Short name T456
Test name
Test status
Simulation time 49866142 ps
CPU time 0.84 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:18 PM PDT 24
Peak memory 207048 kb
Host smart-024f551e-67a4-4ef5-8016-311b0e52a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516517045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.516517045
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3193098019
Short name T481
Test name
Test status
Simulation time 28393567703 ps
CPU time 52.67 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:33:08 PM PDT 24
Peak memory 249296 kb
Host smart-a45b10d6-8713-45b0-a73b-93b10f1a5b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193098019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3193098019
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3801277346
Short name T187
Test name
Test status
Simulation time 395521222261 ps
CPU time 478.51 seconds
Started Jul 28 05:32:19 PM PDT 24
Finished Jul 28 05:40:18 PM PDT 24
Peak memory 257436 kb
Host smart-0951d4a2-a6a0-4b98-8750-e6b11b333e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801277346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3801277346
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1221814214
Short name T694
Test name
Test status
Simulation time 35340524 ps
CPU time 2.55 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:17 PM PDT 24
Peak memory 224684 kb
Host smart-04da68fd-1fa5-4e94-b959-df143d3e0b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221814214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1221814214
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2473264155
Short name T805
Test name
Test status
Simulation time 22586492649 ps
CPU time 165.68 seconds
Started Jul 28 05:32:19 PM PDT 24
Finished Jul 28 05:35:05 PM PDT 24
Peak memory 250968 kb
Host smart-a8172f89-079a-4e9b-827a-1c55958f7102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473264155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2473264155
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2635423950
Short name T910
Test name
Test status
Simulation time 803595017 ps
CPU time 11.81 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:26 PM PDT 24
Peak memory 232848 kb
Host smart-38b2d7b8-b836-4e8c-91de-6059d3c64e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635423950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2635423950
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1951371543
Short name T904
Test name
Test status
Simulation time 36133003043 ps
CPU time 85.22 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:33:41 PM PDT 24
Peak memory 240152 kb
Host smart-9126c3d6-1321-4f1c-a109-41e243a34077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951371543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1951371543
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1017755775
Short name T594
Test name
Test status
Simulation time 730136514 ps
CPU time 6.8 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:23 PM PDT 24
Peak memory 233852 kb
Host smart-203cf789-cf6a-4d3e-b5ca-a35fc12bd22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017755775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1017755775
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4249051111
Short name T472
Test name
Test status
Simulation time 846281075 ps
CPU time 5.43 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:32:20 PM PDT 24
Peak memory 232812 kb
Host smart-59a8f2cb-86dd-496c-b837-ed2259935690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249051111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4249051111
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3980567095
Short name T469
Test name
Test status
Simulation time 4327062107 ps
CPU time 13.07 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 220396 kb
Host smart-e2bfda95-4bdb-4660-812d-6b0149590557
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980567095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3980567095
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.243027244
Short name T67
Test name
Test status
Simulation time 321551291 ps
CPU time 1.13 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:18 PM PDT 24
Peak memory 237076 kb
Host smart-efa451f8-6e89-4f1c-b27d-ba1c9f5465aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243027244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.243027244
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1860749157
Short name T887
Test name
Test status
Simulation time 28851109 ps
CPU time 0.69 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:14 PM PDT 24
Peak memory 205812 kb
Host smart-819686bb-c788-47a6-9d75-edd7aa55d660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860749157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1860749157
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.783118524
Short name T446
Test name
Test status
Simulation time 25872633661 ps
CPU time 18.97 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:32:34 PM PDT 24
Peak memory 217424 kb
Host smart-66937b57-7ac9-4475-8f8b-b4afea1a6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783118524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.783118524
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3792796573
Short name T403
Test name
Test status
Simulation time 69854318 ps
CPU time 1.14 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:18 PM PDT 24
Peak memory 207684 kb
Host smart-9c419088-7102-4cf3-b5d0-e418f253e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792796573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3792796573
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.873986597
Short name T716
Test name
Test status
Simulation time 37025988 ps
CPU time 0.82 seconds
Started Jul 28 05:32:13 PM PDT 24
Finished Jul 28 05:32:15 PM PDT 24
Peak memory 206020 kb
Host smart-bccdd6b7-102b-4149-9a9b-f2d6a1f44f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873986597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.873986597
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.704702396
Short name T632
Test name
Test status
Simulation time 5222803386 ps
CPU time 24.51 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:41 PM PDT 24
Peak memory 249248 kb
Host smart-266897f4-da68-435e-92f6-f62a16e66c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704702396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.704702396
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3624894525
Short name T642
Test name
Test status
Simulation time 42139858 ps
CPU time 0.76 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:33:31 PM PDT 24
Peak memory 205868 kb
Host smart-4e796a24-8e19-44b2-9f01-d26cfaa95e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624894525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3624894525
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3404164311
Short name T669
Test name
Test status
Simulation time 44812019 ps
CPU time 2.38 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:31 PM PDT 24
Peak memory 232552 kb
Host smart-f080ca9d-68a1-41cd-8e84-2689657d87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404164311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3404164311
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2255077610
Short name T847
Test name
Test status
Simulation time 104630394 ps
CPU time 0.75 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:30 PM PDT 24
Peak memory 207004 kb
Host smart-20c1450f-5ba6-41c4-be08-882f0fc539dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255077610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2255077610
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1869996298
Short name T901
Test name
Test status
Simulation time 50286558 ps
CPU time 0.76 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:29 PM PDT 24
Peak memory 215840 kb
Host smart-a0831ecd-4627-4d96-a784-ffde75d24b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869996298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1869996298
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.402774056
Short name T409
Test name
Test status
Simulation time 19992272384 ps
CPU time 191.11 seconds
Started Jul 28 05:33:27 PM PDT 24
Finished Jul 28 05:36:38 PM PDT 24
Peak memory 252020 kb
Host smart-f3925f41-2ce7-491d-b43a-bb364bf93056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402774056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.402774056
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.265153894
Short name T282
Test name
Test status
Simulation time 10468928754 ps
CPU time 165.73 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:36:14 PM PDT 24
Peak memory 265736 kb
Host smart-6f3467a4-9b8d-4294-98ae-6f6397ca4ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265153894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.265153894
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.798779433
Short name T129
Test name
Test status
Simulation time 1153151472 ps
CPU time 18.13 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:47 PM PDT 24
Peak memory 241072 kb
Host smart-d6bee8fd-93af-41e0-ab49-5969616bf4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798779433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.798779433
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2697361948
Short name T982
Test name
Test status
Simulation time 11871115995 ps
CPU time 25.75 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:33:56 PM PDT 24
Peak memory 249144 kb
Host smart-65ff648c-4200-4961-b613-34863cab959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697361948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2697361948
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.926576277
Short name T350
Test name
Test status
Simulation time 272269452 ps
CPU time 2.49 seconds
Started Jul 28 05:33:26 PM PDT 24
Finished Jul 28 05:33:29 PM PDT 24
Peak memory 232488 kb
Host smart-8c95e91d-6fd4-4f75-a8c2-a57fdacf3c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926576277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.926576277
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2685147283
Short name T263
Test name
Test status
Simulation time 1236276899 ps
CPU time 14.71 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 241100 kb
Host smart-9122a7d9-f362-4ca5-9fed-f4f4721c4887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685147283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2685147283
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1157386137
Short name T288
Test name
Test status
Simulation time 423407126 ps
CPU time 2.67 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:33:33 PM PDT 24
Peak memory 224604 kb
Host smart-3532c855-fc67-47ed-ac04-35733d6a2b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157386137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1157386137
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.210609068
Short name T546
Test name
Test status
Simulation time 251626072 ps
CPU time 3.2 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:31 PM PDT 24
Peak memory 224612 kb
Host smart-23b81bdf-a614-4db6-9198-553137c5fe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210609068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.210609068
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4099330413
Short name T636
Test name
Test status
Simulation time 318755802 ps
CPU time 3.87 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 223384 kb
Host smart-284ed48c-fd7b-4806-a41e-9cd127cab3ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4099330413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4099330413
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1569536323
Short name T303
Test name
Test status
Simulation time 6279686625 ps
CPU time 22.04 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:51 PM PDT 24
Peak memory 216812 kb
Host smart-853caeb6-dc43-45ae-9d51-029d9d33cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569536323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1569536323
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1728663724
Short name T839
Test name
Test status
Simulation time 1387202614 ps
CPU time 7.4 seconds
Started Jul 28 05:33:27 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 216432 kb
Host smart-e26b57a9-0614-4caf-b25a-937614915c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728663724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1728663724
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.714171555
Short name T430
Test name
Test status
Simulation time 1450724488 ps
CPU time 1.98 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 216336 kb
Host smart-e6b83608-16e8-4949-bcc2-4ff96c616812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714171555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.714171555
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1704621300
Short name T641
Test name
Test status
Simulation time 81302311 ps
CPU time 0.79 seconds
Started Jul 28 05:33:27 PM PDT 24
Finished Jul 28 05:33:27 PM PDT 24
Peak memory 206040 kb
Host smart-ebc2587d-32b9-41c1-a77d-5b51cf841925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704621300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1704621300
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3952161903
Short name T565
Test name
Test status
Simulation time 4314530222 ps
CPU time 9.91 seconds
Started Jul 28 05:33:27 PM PDT 24
Finished Jul 28 05:33:37 PM PDT 24
Peak memory 238144 kb
Host smart-214cf4fb-8867-4e7f-812d-f30a52c7a2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952161903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3952161903
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.231836562
Short name T762
Test name
Test status
Simulation time 20786670 ps
CPU time 0.71 seconds
Started Jul 28 05:33:39 PM PDT 24
Finished Jul 28 05:33:40 PM PDT 24
Peak memory 205780 kb
Host smart-f0e46c1f-caab-4ac1-a7d6-2e9e6d7161ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231836562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.231836562
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3362316694
Short name T355
Test name
Test status
Simulation time 266496611 ps
CPU time 4.01 seconds
Started Jul 28 05:33:34 PM PDT 24
Finished Jul 28 05:33:38 PM PDT 24
Peak memory 224672 kb
Host smart-bb263fe7-e121-404f-9bb7-b1351114e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362316694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3362316694
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1934409366
Short name T742
Test name
Test status
Simulation time 40137831 ps
CPU time 0.75 seconds
Started Jul 28 05:33:30 PM PDT 24
Finished Jul 28 05:33:31 PM PDT 24
Peak memory 205660 kb
Host smart-370222c6-c6f0-463b-8e19-907cc9352486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934409366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1934409366
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1224700860
Short name T253
Test name
Test status
Simulation time 37049126968 ps
CPU time 102.54 seconds
Started Jul 28 05:33:35 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 257352 kb
Host smart-f003716b-072b-4398-8cd7-3442aa48f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224700860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1224700860
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.6707927
Short name T774
Test name
Test status
Simulation time 26832904958 ps
CPU time 91.62 seconds
Started Jul 28 05:33:32 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 263060 kb
Host smart-23ab033e-e2e0-45f3-baec-0cff38542bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6707927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.6707927
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4186669747
Short name T779
Test name
Test status
Simulation time 136292973184 ps
CPU time 405.9 seconds
Started Jul 28 05:33:36 PM PDT 24
Finished Jul 28 05:40:22 PM PDT 24
Peak memory 273000 kb
Host smart-873af33f-686a-4e12-9f74-d8b9e17fd0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186669747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4186669747
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1099518289
Short name T519
Test name
Test status
Simulation time 1042092344 ps
CPU time 15.46 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:48 PM PDT 24
Peak memory 224700 kb
Host smart-28162be9-4893-47db-a518-dd96230c537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099518289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1099518289
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2760030376
Short name T290
Test name
Test status
Simulation time 6176635148 ps
CPU time 76.08 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 250364 kb
Host smart-84154154-a367-4e82-b01a-e3bbf2a6d3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760030376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2760030376
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2160745709
Short name T970
Test name
Test status
Simulation time 1424318364 ps
CPU time 5.74 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:39 PM PDT 24
Peak memory 232868 kb
Host smart-ffa2e738-cd26-493e-a57e-679aba3979b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160745709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2160745709
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3991209743
Short name T793
Test name
Test status
Simulation time 139452204 ps
CPU time 3.18 seconds
Started Jul 28 05:33:34 PM PDT 24
Finished Jul 28 05:33:37 PM PDT 24
Peak memory 232792 kb
Host smart-42f858ca-ebc8-488c-b34c-81d939bf4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991209743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3991209743
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3959789398
Short name T202
Test name
Test status
Simulation time 4069464144 ps
CPU time 15.73 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 232800 kb
Host smart-bc96b8e8-e976-4b9d-aebc-a3ec4cb23086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959789398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3959789398
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.947264215
Short name T545
Test name
Test status
Simulation time 184117431 ps
CPU time 2.88 seconds
Started Jul 28 05:33:29 PM PDT 24
Finished Jul 28 05:33:33 PM PDT 24
Peak memory 232836 kb
Host smart-dbb09143-9224-4ba4-9861-0271623ba179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947264215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.947264215
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3824817608
Short name T782
Test name
Test status
Simulation time 283514428 ps
CPU time 3.77 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:37 PM PDT 24
Peak memory 220852 kb
Host smart-9d5ce0bf-a8a5-4dba-8ef3-d81d98c3cd19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3824817608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3824817608
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4090965017
Short name T139
Test name
Test status
Simulation time 39317613935 ps
CPU time 122.28 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:35:39 PM PDT 24
Peak memory 249396 kb
Host smart-cd8ae01c-93cc-42a6-8a75-ea414674ce9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090965017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4090965017
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.165110690
Short name T315
Test name
Test status
Simulation time 1351293470 ps
CPU time 6.9 seconds
Started Jul 28 05:33:27 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 216408 kb
Host smart-b734c7b2-bfc0-4118-ba79-70b659231225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165110690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.165110690
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.532426125
Short name T684
Test name
Test status
Simulation time 3715377612 ps
CPU time 5.83 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 216472 kb
Host smart-b55cfef6-d9d9-4a3a-8f55-1a926bb2e34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532426125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.532426125
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.197202965
Short name T981
Test name
Test status
Simulation time 38553796 ps
CPU time 1.22 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:29 PM PDT 24
Peak memory 208168 kb
Host smart-e2d9be27-f109-45db-87a0-84eb26da5afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197202965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.197202965
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1785955937
Short name T427
Test name
Test status
Simulation time 14126801 ps
CPU time 0.73 seconds
Started Jul 28 05:33:28 PM PDT 24
Finished Jul 28 05:33:29 PM PDT 24
Peak memory 206116 kb
Host smart-826cb97e-81e7-456e-a5b7-ee18d75df642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785955937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1785955937
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4044609448
Short name T840
Test name
Test status
Simulation time 296350987 ps
CPU time 5.15 seconds
Started Jul 28 05:33:35 PM PDT 24
Finished Jul 28 05:33:40 PM PDT 24
Peak memory 232804 kb
Host smart-4b5d4d5e-d8ea-4187-89b5-9896c8e07935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044609448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4044609448
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2760403448
Short name T691
Test name
Test status
Simulation time 50991786 ps
CPU time 0.82 seconds
Started Jul 28 05:33:39 PM PDT 24
Finished Jul 28 05:33:40 PM PDT 24
Peak memory 204964 kb
Host smart-b07fce58-8c6f-49f0-8730-cd91c54844e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760403448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2760403448
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1042847199
Short name T450
Test name
Test status
Simulation time 675454950 ps
CPU time 2.54 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:36 PM PDT 24
Peak memory 232848 kb
Host smart-c7762df2-3d97-4aa4-a26c-0b6383d5e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042847199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1042847199
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3191353661
Short name T345
Test name
Test status
Simulation time 45077016 ps
CPU time 0.78 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:33:38 PM PDT 24
Peak memory 205572 kb
Host smart-fe65cfbd-0ea2-4af6-8f3c-57bd9488efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191353661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3191353661
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2104048508
Short name T675
Test name
Test status
Simulation time 13401082915 ps
CPU time 55.68 seconds
Started Jul 28 05:33:34 PM PDT 24
Finished Jul 28 05:34:30 PM PDT 24
Peak memory 264092 kb
Host smart-da803e55-0bb7-4602-9231-0671675d0da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104048508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2104048508
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4270817007
Short name T396
Test name
Test status
Simulation time 2879335981 ps
CPU time 53.05 seconds
Started Jul 28 05:33:35 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 249380 kb
Host smart-e23b3900-3b47-43fc-bc32-3b3dc57c77a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270817007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4270817007
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1975582704
Short name T215
Test name
Test status
Simulation time 22906865692 ps
CPU time 298.02 seconds
Started Jul 28 05:33:35 PM PDT 24
Finished Jul 28 05:38:33 PM PDT 24
Peak memory 268312 kb
Host smart-353c7685-21c6-462f-8e30-024469623c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975582704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1975582704
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4294033715
Short name T547
Test name
Test status
Simulation time 1201584138 ps
CPU time 10.74 seconds
Started Jul 28 05:33:36 PM PDT 24
Finished Jul 28 05:33:47 PM PDT 24
Peak memory 249244 kb
Host smart-3f6ce063-f9b1-4111-98bc-4a2a93f598cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294033715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4294033715
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2911381541
Short name T592
Test name
Test status
Simulation time 900079318 ps
CPU time 13.26 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 234940 kb
Host smart-936bf7a6-63fe-4762-b7ac-fe648b8fb9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911381541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2911381541
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.832497159
Short name T761
Test name
Test status
Simulation time 216993364 ps
CPU time 2.73 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:36 PM PDT 24
Peak memory 232828 kb
Host smart-b7622004-7fc9-4755-bb02-5572ec9cf9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832497159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.832497159
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3168325789
Short name T148
Test name
Test status
Simulation time 1751088918 ps
CPU time 9.94 seconds
Started Jul 28 05:33:34 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 232900 kb
Host smart-650e4c10-e46c-46d4-936f-1edf21aee38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168325789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3168325789
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2146394019
Short name T262
Test name
Test status
Simulation time 10943393242 ps
CPU time 9.14 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 240788 kb
Host smart-493cd65c-90f9-47bd-8ebc-cb3ddd40884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146394019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2146394019
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1645137066
Short name T233
Test name
Test status
Simulation time 1414812372 ps
CPU time 4.44 seconds
Started Jul 28 05:33:39 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 224812 kb
Host smart-7b673865-8aa8-4958-b64d-2db7f40c5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645137066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1645137066
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.446882482
Short name T730
Test name
Test status
Simulation time 2027958590 ps
CPU time 3.61 seconds
Started Jul 28 05:33:35 PM PDT 24
Finished Jul 28 05:33:39 PM PDT 24
Peak memory 219936 kb
Host smart-28ebaa13-e1e2-4901-beab-8c31321b1733
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=446882482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.446882482
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4246362681
Short name T744
Test name
Test status
Simulation time 24329965357 ps
CPU time 222.13 seconds
Started Jul 28 05:33:36 PM PDT 24
Finished Jul 28 05:37:19 PM PDT 24
Peak memory 256872 kb
Host smart-e093ce09-d334-4f4b-8dd8-abef81a801c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246362681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4246362681
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1557762632
Short name T729
Test name
Test status
Simulation time 7250088414 ps
CPU time 15.01 seconds
Started Jul 28 05:33:40 PM PDT 24
Finished Jul 28 05:33:55 PM PDT 24
Peak memory 216720 kb
Host smart-a6f07cab-f011-48e2-aba8-ba30faf225ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557762632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1557762632
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4183223197
Short name T701
Test name
Test status
Simulation time 1202873199 ps
CPU time 3.48 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:33:41 PM PDT 24
Peak memory 216272 kb
Host smart-2d5bb763-50f1-4a2d-9f7e-c3bffa24f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183223197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4183223197
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3775070406
Short name T873
Test name
Test status
Simulation time 291272415 ps
CPU time 3.6 seconds
Started Jul 28 05:33:36 PM PDT 24
Finished Jul 28 05:33:40 PM PDT 24
Peak memory 216344 kb
Host smart-1a937a8c-ce51-43df-b9e6-aa3b31024355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775070406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3775070406
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.385783001
Short name T115
Test name
Test status
Simulation time 16200519 ps
CPU time 0.73 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 206088 kb
Host smart-122b5169-6b77-4fda-97ce-542ec0ace596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385783001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.385783001
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2524152406
Short name T643
Test name
Test status
Simulation time 3643624747 ps
CPU time 13.32 seconds
Started Jul 28 05:33:34 PM PDT 24
Finished Jul 28 05:33:47 PM PDT 24
Peak memory 232916 kb
Host smart-415b9b9f-2ebc-4a07-b9e5-77b42b2a3c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524152406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2524152406
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3867144997
Short name T418
Test name
Test status
Simulation time 16059407 ps
CPU time 0.71 seconds
Started Jul 28 05:33:40 PM PDT 24
Finished Jul 28 05:33:41 PM PDT 24
Peak memory 204964 kb
Host smart-567b4e1d-b220-4ec2-9f56-25e5171590f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867144997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3867144997
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2023484201
Short name T772
Test name
Test status
Simulation time 75996027 ps
CPU time 3.25 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:45 PM PDT 24
Peak memory 232820 kb
Host smart-a4b30fd2-3ac4-428e-a5ea-6efa6814fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023484201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2023484201
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1747751012
Short name T392
Test name
Test status
Simulation time 41267757 ps
CPU time 0.78 seconds
Started Jul 28 05:33:36 PM PDT 24
Finished Jul 28 05:33:37 PM PDT 24
Peak memory 205660 kb
Host smart-ff334137-5ecd-4a9e-a42f-c31a737f19a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747751012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1747751012
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3389320480
Short name T279
Test name
Test status
Simulation time 108148890592 ps
CPU time 242.02 seconds
Started Jul 28 05:33:40 PM PDT 24
Finished Jul 28 05:37:42 PM PDT 24
Peak memory 255672 kb
Host smart-8a505725-3bf1-43b4-a36b-3e85de7849aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389320480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3389320480
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2374806346
Short name T274
Test name
Test status
Simulation time 107273503130 ps
CPU time 225.29 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:37:27 PM PDT 24
Peak memory 251772 kb
Host smart-d5b2db79-ea3d-4f6b-9988-21e54c8a030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374806346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2374806346
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3850214186
Short name T38
Test name
Test status
Simulation time 60393861099 ps
CPU time 188.44 seconds
Started Jul 28 05:33:44 PM PDT 24
Finished Jul 28 05:36:53 PM PDT 24
Peak memory 272524 kb
Host smart-cdb76917-ec31-4e1a-9ccb-9036b4f4f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850214186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3850214186
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1261305281
Short name T36
Test name
Test status
Simulation time 4620164256 ps
CPU time 70.88 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 252616 kb
Host smart-ad4bd12d-5d03-4828-869f-730dc601b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261305281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1261305281
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2126997371
Short name T507
Test name
Test status
Simulation time 240953784 ps
CPU time 1.01 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:42 PM PDT 24
Peak memory 216052 kb
Host smart-8224ad34-d298-4fff-a25f-8a98acb5ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126997371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2126997371
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1002956091
Short name T896
Test name
Test status
Simulation time 58746256 ps
CPU time 3.07 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 232896 kb
Host smart-f5ad2f10-4f8b-4dee-800f-d0d3e80faa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002956091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1002956091
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.757557375
Short name T836
Test name
Test status
Simulation time 3143183511 ps
CPU time 44.85 seconds
Started Jul 28 05:33:43 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 234476 kb
Host smart-9d31e49e-9f80-4a1a-9a3e-8982c684c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757557375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.757557375
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2681109782
Short name T553
Test name
Test status
Simulation time 9311393533 ps
CPU time 7.02 seconds
Started Jul 28 05:33:36 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 224688 kb
Host smart-1c61a16b-458b-40a0-a2e3-6cb32bde127c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681109782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2681109782
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1192068271
Short name T743
Test name
Test status
Simulation time 2201556470 ps
CPU time 7.28 seconds
Started Jul 28 05:33:37 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 224616 kb
Host smart-9e88a595-35a0-4be2-962f-06f550111c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192068271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1192068271
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3048636229
Short name T769
Test name
Test status
Simulation time 281435788 ps
CPU time 7.04 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:49 PM PDT 24
Peak memory 220828 kb
Host smart-c00f96c4-7135-4085-83b1-8f91e992e45f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3048636229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3048636229
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1232712282
Short name T560
Test name
Test status
Simulation time 51477362 ps
CPU time 1.09 seconds
Started Jul 28 05:33:43 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 207240 kb
Host smart-c78d49b5-d692-41b5-ad5a-bff0f3c03a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232712282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1232712282
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3222926480
Short name T1009
Test name
Test status
Simulation time 122798286412 ps
CPU time 36.73 seconds
Started Jul 28 05:33:35 PM PDT 24
Finished Jul 28 05:34:12 PM PDT 24
Peak memory 216368 kb
Host smart-e426eb50-1e2f-486e-84e7-9642945c2903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222926480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3222926480
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.767119550
Short name T453
Test name
Test status
Simulation time 16612161415 ps
CPU time 8.35 seconds
Started Jul 28 05:33:40 PM PDT 24
Finished Jul 28 05:33:48 PM PDT 24
Peak memory 217776 kb
Host smart-45f3402d-1187-488d-a38e-01a05616fcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767119550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.767119550
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1014520381
Short name T737
Test name
Test status
Simulation time 275226067 ps
CPU time 3.69 seconds
Started Jul 28 05:33:34 PM PDT 24
Finished Jul 28 05:33:38 PM PDT 24
Peak memory 216444 kb
Host smart-3c06136c-1677-44f3-a722-f7a703444ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014520381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1014520381
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.464409345
Short name T875
Test name
Test status
Simulation time 40105002 ps
CPU time 0.78 seconds
Started Jul 28 05:33:33 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 206072 kb
Host smart-878a9612-0e8a-4c7e-9eb5-09e688986d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464409345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.464409345
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3661260276
Short name T216
Test name
Test status
Simulation time 512080424 ps
CPU time 6.01 seconds
Started Jul 28 05:33:44 PM PDT 24
Finished Jul 28 05:33:50 PM PDT 24
Peak memory 239176 kb
Host smart-c02b658c-ccbf-4a45-a84a-34e66acc219d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661260276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3661260276
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1210849225
Short name T498
Test name
Test status
Simulation time 41094050 ps
CPU time 0.69 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:42 PM PDT 24
Peak memory 205564 kb
Host smart-63410f32-aafe-42e7-b464-e4c024f5198d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210849225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1210849225
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2729312563
Short name T244
Test name
Test status
Simulation time 84611413 ps
CPU time 2.9 seconds
Started Jul 28 05:33:43 PM PDT 24
Finished Jul 28 05:33:47 PM PDT 24
Peak memory 232872 kb
Host smart-f7534e3f-7e4d-4ed0-9071-52517fde2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729312563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2729312563
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.586479240
Short name T398
Test name
Test status
Simulation time 69094516 ps
CPU time 0.77 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:43 PM PDT 24
Peak memory 206672 kb
Host smart-d3bb6759-ae3a-407b-ac86-d6a6037e47e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586479240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.586479240
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3855276050
Short name T733
Test name
Test status
Simulation time 45571098437 ps
CPU time 168.98 seconds
Started Jul 28 05:33:47 PM PDT 24
Finished Jul 28 05:36:36 PM PDT 24
Peak memory 251752 kb
Host smart-6293464b-af92-4eab-9013-5b57eff1f8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855276050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3855276050
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.308286165
Short name T120
Test name
Test status
Simulation time 59953313066 ps
CPU time 88.1 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 266516 kb
Host smart-26ee1d2f-9005-440b-8b01-66d8b580e45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308286165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.308286165
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2124584002
Short name T965
Test name
Test status
Simulation time 14415060711 ps
CPU time 102.47 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:35:25 PM PDT 24
Peak memory 256836 kb
Host smart-5bc51186-b81f-450b-a35d-f506a104b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124584002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2124584002
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.443008585
Short name T993
Test name
Test status
Simulation time 1239277939 ps
CPU time 22.11 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:34:04 PM PDT 24
Peak memory 236928 kb
Host smart-78202dcc-9c4e-4c6f-bd62-c03e30217201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443008585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.443008585
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1934458943
Short name T752
Test name
Test status
Simulation time 2587041303 ps
CPU time 54.18 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:34:37 PM PDT 24
Peak memory 249272 kb
Host smart-4f128b52-465f-4224-803f-63e720765824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934458943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1934458943
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.558745192
Short name T211
Test name
Test status
Simulation time 1653397442 ps
CPU time 13.55 seconds
Started Jul 28 05:33:44 PM PDT 24
Finished Jul 28 05:33:58 PM PDT 24
Peak memory 232880 kb
Host smart-942e5341-ff05-407e-aa6f-1eda3e3cf5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558745192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.558745192
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1147159362
Short name T644
Test name
Test status
Simulation time 6226839618 ps
CPU time 42.25 seconds
Started Jul 28 05:33:40 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 240424 kb
Host smart-43c073dd-5d0c-41f8-924f-787b123f7bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147159362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1147159362
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1715373225
Short name T870
Test name
Test status
Simulation time 1858648186 ps
CPU time 7.38 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:50 PM PDT 24
Peak memory 232868 kb
Host smart-07e1c1ee-35fe-4280-b08d-77ecdd098c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715373225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1715373225
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2771259688
Short name T983
Test name
Test status
Simulation time 5771610283 ps
CPU time 10.6 seconds
Started Jul 28 05:33:44 PM PDT 24
Finished Jul 28 05:33:54 PM PDT 24
Peak memory 232928 kb
Host smart-dbcb2e32-b866-4a24-8484-76cd534577e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771259688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2771259688
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3269007457
Short name T852
Test name
Test status
Simulation time 7065574123 ps
CPU time 13.7 seconds
Started Jul 28 05:33:44 PM PDT 24
Finished Jul 28 05:33:58 PM PDT 24
Peak memory 223160 kb
Host smart-dc6b783b-28f0-4a50-8235-df82a0ab90e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3269007457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3269007457
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.425808216
Short name T143
Test name
Test status
Simulation time 98485407085 ps
CPU time 234.78 seconds
Started Jul 28 05:33:46 PM PDT 24
Finished Jul 28 05:37:41 PM PDT 24
Peak memory 253044 kb
Host smart-94145611-6128-44f1-b198-1cff01ba3cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425808216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.425808216
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1711923417
Short name T311
Test name
Test status
Simulation time 5942551157 ps
CPU time 6.15 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:49 PM PDT 24
Peak memory 216424 kb
Host smart-8694f741-cae6-4861-ad02-a627c3e0f152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711923417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1711923417
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1752344892
Short name T781
Test name
Test status
Simulation time 1261317611 ps
CPU time 2.81 seconds
Started Jul 28 05:33:43 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 207940 kb
Host smart-60fab640-65af-4b2a-bd24-6ff8c249dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752344892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1752344892
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3063316662
Short name T356
Test name
Test status
Simulation time 34561990 ps
CPU time 0.7 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:42 PM PDT 24
Peak memory 205776 kb
Host smart-dedb573f-d5c4-41ab-90f7-e6633f2a0a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063316662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3063316662
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2591819175
Short name T371
Test name
Test status
Simulation time 416595064 ps
CPU time 1.01 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:43 PM PDT 24
Peak memory 206488 kb
Host smart-c3994da4-9ece-4b5d-98bc-c7bce7260929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591819175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2591819175
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2087464694
Short name T478
Test name
Test status
Simulation time 13617389351 ps
CPU time 12.54 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:54 PM PDT 24
Peak memory 232852 kb
Host smart-d7eab01d-eb99-43d1-9e59-3ff3b669ae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087464694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2087464694
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3858291119
Short name T884
Test name
Test status
Simulation time 17217643 ps
CPU time 0.71 seconds
Started Jul 28 05:33:46 PM PDT 24
Finished Jul 28 05:33:47 PM PDT 24
Peak memory 204872 kb
Host smart-713fbff9-42ee-4948-ae03-44d92a52122c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858291119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3858291119
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3764345934
Short name T921
Test name
Test status
Simulation time 866402089 ps
CPU time 4.19 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:33:52 PM PDT 24
Peak memory 224652 kb
Host smart-878e5d58-4ef8-49a1-b27b-1ccc97ec9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764345934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3764345934
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3761984989
Short name T360
Test name
Test status
Simulation time 75372168 ps
CPU time 0.81 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:43 PM PDT 24
Peak memory 206720 kb
Host smart-3698db37-2233-45fd-999a-574f347e0bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761984989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3761984989
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3441143803
Short name T768
Test name
Test status
Simulation time 66940475838 ps
CPU time 31.91 seconds
Started Jul 28 05:33:50 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 238436 kb
Host smart-7fc54080-036e-461b-b963-71995c57856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441143803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3441143803
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2224886328
Short name T898
Test name
Test status
Simulation time 5255525323 ps
CPU time 84.88 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:35:13 PM PDT 24
Peak memory 249364 kb
Host smart-816ebf3d-8dcc-4256-a8ab-39438da1c832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224886328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2224886328
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1409762874
Short name T845
Test name
Test status
Simulation time 132527930 ps
CPU time 3.55 seconds
Started Jul 28 05:33:50 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 224612 kb
Host smart-208e74b4-2d05-4394-b84d-c824f0e2e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409762874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1409762874
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.886723306
Short name T190
Test name
Test status
Simulation time 4163177352 ps
CPU time 67.44 seconds
Started Jul 28 05:33:47 PM PDT 24
Finished Jul 28 05:34:55 PM PDT 24
Peak memory 252432 kb
Host smart-445b7916-a0fd-4541-a5e2-0916fcce6f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886723306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.886723306
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1931338900
Short name T482
Test name
Test status
Simulation time 84948071 ps
CPU time 2.48 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 232880 kb
Host smart-ba1457d5-ed8d-4c4c-931a-452159877d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931338900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1931338900
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2572432767
Short name T250
Test name
Test status
Simulation time 213350691 ps
CPU time 3.52 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 224684 kb
Host smart-b125a007-dc59-49db-811b-fe787a23cc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572432767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2572432767
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.64153735
Short name T222
Test name
Test status
Simulation time 514435734 ps
CPU time 3.91 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 224632 kb
Host smart-8777266e-4e42-49fe-a322-631c13a515d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64153735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.64153735
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.97061446
Short name T437
Test name
Test status
Simulation time 1992118598 ps
CPU time 7.41 seconds
Started Jul 28 05:33:45 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 234788 kb
Host smart-a69926e5-4895-48ca-9b7a-446c11a53bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97061446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.97061446
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1492644154
Short name T468
Test name
Test status
Simulation time 480359419 ps
CPU time 4.57 seconds
Started Jul 28 05:33:51 PM PDT 24
Finished Jul 28 05:33:55 PM PDT 24
Peak memory 222912 kb
Host smart-b554b9bd-587f-497b-a884-8dbbff144435
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1492644154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1492644154
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4230488292
Short name T897
Test name
Test status
Simulation time 76850526880 ps
CPU time 116.06 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:35:44 PM PDT 24
Peak memory 250428 kb
Host smart-1608d6ce-88af-4753-be04-75f540637777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230488292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4230488292
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2038613189
Short name T390
Test name
Test status
Simulation time 2106802161 ps
CPU time 6.36 seconds
Started Jul 28 05:33:39 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 216328 kb
Host smart-e580534c-f3ab-4e42-a20c-f3ccbfda81b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038613189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2038613189
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.322537566
Short name T829
Test name
Test status
Simulation time 357039662 ps
CPU time 1.37 seconds
Started Jul 28 05:33:43 PM PDT 24
Finished Jul 28 05:33:45 PM PDT 24
Peak memory 207968 kb
Host smart-a245c57a-35d2-46ba-b353-8ab1f3dd2fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322537566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.322537566
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1024905871
Short name T397
Test name
Test status
Simulation time 1510874020 ps
CPU time 4.09 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:46 PM PDT 24
Peak memory 216412 kb
Host smart-eb167372-2067-47c4-a8e0-e28aaa5553b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024905871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1024905871
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.365573773
Short name T543
Test name
Test status
Simulation time 100493861 ps
CPU time 0.99 seconds
Started Jul 28 05:33:42 PM PDT 24
Finished Jul 28 05:33:44 PM PDT 24
Peak memory 206096 kb
Host smart-215f5f32-86dd-4517-8b30-c662e3f891e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365573773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.365573773
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2798908207
Short name T268
Test name
Test status
Simulation time 80061989 ps
CPU time 2.25 seconds
Started Jul 28 05:33:41 PM PDT 24
Finished Jul 28 05:33:43 PM PDT 24
Peak memory 224556 kb
Host smart-e92d8620-d89d-403a-9d6e-b4d519bc4748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798908207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2798908207
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1186536323
Short name T387
Test name
Test status
Simulation time 22610012 ps
CPU time 0.72 seconds
Started Jul 28 05:33:44 PM PDT 24
Finished Jul 28 05:33:45 PM PDT 24
Peak memory 205012 kb
Host smart-399a4fdb-ae89-4478-a077-8fa802a6b755
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186536323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1186536323
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2910021590
Short name T770
Test name
Test status
Simulation time 606848941 ps
CPU time 3.58 seconds
Started Jul 28 05:33:50 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 224620 kb
Host smart-cf289ac8-539c-46d3-a6c6-c7e80b0f3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910021590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2910021590
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1195374630
Short name T912
Test name
Test status
Simulation time 32857631 ps
CPU time 0.77 seconds
Started Jul 28 05:33:47 PM PDT 24
Finished Jul 28 05:33:47 PM PDT 24
Peak memory 207024 kb
Host smart-84868d75-9e4d-4fbb-ae82-30142469eee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195374630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1195374630
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.626766991
Short name T969
Test name
Test status
Simulation time 2886879775 ps
CPU time 20.04 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:34:08 PM PDT 24
Peak memory 234540 kb
Host smart-334c180f-6955-4bce-bf83-ba11bb170bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626766991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.626766991
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3042372101
Short name T444
Test name
Test status
Simulation time 1386535197 ps
CPU time 7.53 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:33:56 PM PDT 24
Peak memory 217608 kb
Host smart-9fd74b43-5145-4d40-99a8-17197eb6f9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042372101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3042372101
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3044540055
Short name T959
Test name
Test status
Simulation time 52874116295 ps
CPU time 136.69 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:36:09 PM PDT 24
Peak memory 261884 kb
Host smart-a32bd011-e35c-47da-9f1a-613bf1399af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044540055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3044540055
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.879726101
Short name T335
Test name
Test status
Simulation time 985499253 ps
CPU time 7.84 seconds
Started Jul 28 05:33:51 PM PDT 24
Finished Jul 28 05:33:59 PM PDT 24
Peak memory 224684 kb
Host smart-fcfcfe36-1916-47a6-bd1f-3a33a6122842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879726101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.879726101
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3897719136
Short name T544
Test name
Test status
Simulation time 140348672597 ps
CPU time 101.2 seconds
Started Jul 28 05:33:46 PM PDT 24
Finished Jul 28 05:35:27 PM PDT 24
Peak memory 240228 kb
Host smart-e67ec255-0e54-473c-bf7c-8c7126870dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897719136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3897719136
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3106492431
Short name T759
Test name
Test status
Simulation time 10596145394 ps
CPU time 12.54 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:34:01 PM PDT 24
Peak memory 232912 kb
Host smart-dd1a06b2-95a1-438d-aba3-e36be4f26c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106492431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3106492431
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.491454234
Short name T579
Test name
Test status
Simulation time 1913943410 ps
CPU time 17.03 seconds
Started Jul 28 05:33:47 PM PDT 24
Finished Jul 28 05:34:04 PM PDT 24
Peak memory 224652 kb
Host smart-1f521fce-7a45-4416-b594-e7fdcbd4710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491454234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.491454234
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3658563983
Short name T825
Test name
Test status
Simulation time 19720845424 ps
CPU time 16.08 seconds
Started Jul 28 05:33:51 PM PDT 24
Finished Jul 28 05:34:08 PM PDT 24
Peak memory 240124 kb
Host smart-488a24a0-61f3-49c2-b41b-2fb301e24639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658563983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3658563983
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1890833080
Short name T537
Test name
Test status
Simulation time 1468510771 ps
CPU time 7.58 seconds
Started Jul 28 05:33:46 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 232760 kb
Host smart-889adfc8-87d3-4e20-afd9-a6e1eb8e335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890833080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1890833080
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.975658618
Short name T549
Test name
Test status
Simulation time 2451246532 ps
CPU time 15.7 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:34:04 PM PDT 24
Peak memory 219412 kb
Host smart-240fda18-8313-4e75-9332-e86ff59c514e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=975658618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.975658618
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.67817805
Short name T736
Test name
Test status
Simulation time 7117445648 ps
CPU time 59.45 seconds
Started Jul 28 05:33:48 PM PDT 24
Finished Jul 28 05:34:47 PM PDT 24
Peak memory 251760 kb
Host smart-1ff58592-a0c3-4a7c-8caa-07c82670c53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67817805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.67817805
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4061113668
Short name T59
Test name
Test status
Simulation time 8863527576 ps
CPU time 26.59 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:34:19 PM PDT 24
Peak memory 221092 kb
Host smart-12ace06d-cceb-4bc7-9d47-96f5c54c0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061113668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4061113668
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.696900296
Short name T321
Test name
Test status
Simulation time 2967625145 ps
CPU time 5.26 seconds
Started Jul 28 05:33:47 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 216384 kb
Host smart-9ee63ff2-3e5d-420e-868e-6afd3a6d120f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696900296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.696900296
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3132754601
Short name T501
Test name
Test status
Simulation time 26152808 ps
CPU time 1.3 seconds
Started Jul 28 05:33:46 PM PDT 24
Finished Jul 28 05:33:48 PM PDT 24
Peak memory 216368 kb
Host smart-26f8e648-f9c5-42ce-baeb-d6a8a4a5a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132754601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3132754601
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3637180727
Short name T699
Test name
Test status
Simulation time 158441793 ps
CPU time 0.81 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 206080 kb
Host smart-ad9fd75c-4ae0-497b-819b-da5f9c1a5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637180727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3637180727
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4083613299
Short name T654
Test name
Test status
Simulation time 1908163777 ps
CPU time 3.92 seconds
Started Jul 28 05:33:49 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 224652 kb
Host smart-b869ce03-d775-49f4-93c0-a79689384d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083613299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4083613299
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4007635416
Short name T370
Test name
Test status
Simulation time 41418696 ps
CPU time 0.69 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:33:53 PM PDT 24
Peak memory 205472 kb
Host smart-9ab1012a-3653-49c0-b607-8bab0a8cac91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007635416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4007635416
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1649812358
Short name T388
Test name
Test status
Simulation time 3725065768 ps
CPU time 12.05 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:34:07 PM PDT 24
Peak memory 232832 kb
Host smart-d4d55c5c-97de-4479-8376-043cb104e400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649812358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1649812358
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4076214554
Short name T369
Test name
Test status
Simulation time 16552274 ps
CPU time 0.75 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:33:54 PM PDT 24
Peak memory 205688 kb
Host smart-ac34c9ad-bca5-491a-93ea-e943aa1d0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076214554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4076214554
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3533043350
Short name T703
Test name
Test status
Simulation time 37575990035 ps
CPU time 245.53 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:37:59 PM PDT 24
Peak memory 249296 kb
Host smart-53bf7bef-2842-4982-b474-700a44268f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533043350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3533043350
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1975845647
Short name T319
Test name
Test status
Simulation time 5495388133 ps
CPU time 85.01 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 249384 kb
Host smart-8a48bddf-0bef-4282-8be8-624f21a3547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975845647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1975845647
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3982409743
Short name T732
Test name
Test status
Simulation time 127319094686 ps
CPU time 268.64 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:38:21 PM PDT 24
Peak memory 265688 kb
Host smart-0cd879af-35df-4707-9506-75b198f3464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982409743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3982409743
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1965677523
Short name T301
Test name
Test status
Simulation time 312614182 ps
CPU time 9.47 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:34:04 PM PDT 24
Peak memory 232852 kb
Host smart-a6635786-ef80-46d3-9988-94b25ca4738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965677523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1965677523
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.413943723
Short name T189
Test name
Test status
Simulation time 19233329142 ps
CPU time 189.99 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 256912 kb
Host smart-bd002ece-f502-435c-83e1-bba51bf7e4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413943723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.413943723
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4109264277
Short name T861
Test name
Test status
Simulation time 796779296 ps
CPU time 9.76 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:34:03 PM PDT 24
Peak memory 232828 kb
Host smart-ac4bb9dc-3eeb-46d7-a525-239a3595d6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109264277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4109264277
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3349142802
Short name T990
Test name
Test status
Simulation time 2439486102 ps
CPU time 4.05 seconds
Started Jul 28 05:33:55 PM PDT 24
Finished Jul 28 05:33:59 PM PDT 24
Peak memory 224644 kb
Host smart-da52541d-fbd3-4330-8e0b-19fe5d4567af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349142802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3349142802
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1402958879
Short name T400
Test name
Test status
Simulation time 17890927948 ps
CPU time 9.32 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:34:01 PM PDT 24
Peak memory 224708 kb
Host smart-b5c5991e-bb94-47e5-a954-6f80cb23f0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402958879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1402958879
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4078413098
Short name T663
Test name
Test status
Simulation time 502659537 ps
CPU time 6.72 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:34:01 PM PDT 24
Peak memory 221296 kb
Host smart-4b9a1a8a-0c8e-406c-a5f5-c5697ee0b31b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4078413098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4078413098
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3108168016
Short name T291
Test name
Test status
Simulation time 12390278374 ps
CPU time 119.19 seconds
Started Jul 28 05:33:51 PM PDT 24
Finished Jul 28 05:35:50 PM PDT 24
Peak memory 257416 kb
Host smart-dec5d15d-67c3-48b0-a6c1-21338d25d479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108168016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3108168016
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2213074310
Short name T13
Test name
Test status
Simulation time 9090123017 ps
CPU time 48.25 seconds
Started Jul 28 05:33:51 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 216492 kb
Host smart-36b88402-e4eb-4bcf-bc51-62c298a7eebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213074310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2213074310
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.368281478
Short name T713
Test name
Test status
Simulation time 8486672299 ps
CPU time 24.92 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:34:18 PM PDT 24
Peak memory 216424 kb
Host smart-9f44cfe7-b1ac-48fa-8619-29bb98dbf339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368281478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.368281478
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.521981985
Short name T598
Test name
Test status
Simulation time 19517293 ps
CPU time 0.7 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:33:54 PM PDT 24
Peak memory 205736 kb
Host smart-f51498d8-b6cf-46d4-8e5c-1fe94dfa6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521981985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.521981985
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3466055609
Short name T670
Test name
Test status
Simulation time 104127125 ps
CPU time 1 seconds
Started Jul 28 05:33:57 PM PDT 24
Finished Jul 28 05:33:58 PM PDT 24
Peak memory 207100 kb
Host smart-c895daa3-3628-409a-a80f-eee65e727c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466055609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3466055609
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1483955680
Short name T800
Test name
Test status
Simulation time 4812096945 ps
CPU time 7.91 seconds
Started Jul 28 05:33:52 PM PDT 24
Finished Jul 28 05:34:00 PM PDT 24
Peak memory 224636 kb
Host smart-e8f19969-ed22-47cb-bf83-c068f525def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483955680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1483955680
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4051079812
Short name T524
Test name
Test status
Simulation time 13892309 ps
CPU time 0.73 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:34:01 PM PDT 24
Peak memory 205832 kb
Host smart-83a5a14f-1526-44d8-a0ae-c3daa513bede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051079812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4051079812
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.893243537
Short name T372
Test name
Test status
Simulation time 1881825086 ps
CPU time 6.56 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:09 PM PDT 24
Peak memory 232836 kb
Host smart-9d2b99e2-1e6d-4f4a-a2d1-b61ecc257c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893243537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.893243537
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3519659389
Short name T466
Test name
Test status
Simulation time 56153959 ps
CPU time 0.8 seconds
Started Jul 28 05:33:53 PM PDT 24
Finished Jul 28 05:33:54 PM PDT 24
Peak memory 206892 kb
Host smart-dd4feb0d-28a2-402e-8b9e-000bc676fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519659389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3519659389
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2632998559
Short name T506
Test name
Test status
Simulation time 3315627297 ps
CPU time 12.81 seconds
Started Jul 28 05:33:59 PM PDT 24
Finished Jul 28 05:34:12 PM PDT 24
Peak memory 234340 kb
Host smart-3024a557-3fd2-4b4f-a803-bc3ba53cbb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632998559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2632998559
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.374208233
Short name T421
Test name
Test status
Simulation time 11367657645 ps
CPU time 33.8 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:36 PM PDT 24
Peak memory 232988 kb
Host smart-fb794405-d9f6-465d-ad42-86e039c4ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374208233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.374208233
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1428795339
Short name T173
Test name
Test status
Simulation time 14701538650 ps
CPU time 183.44 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:37:06 PM PDT 24
Peak memory 251356 kb
Host smart-219c1b89-f1fb-4023-8bbd-5b39c6003a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428795339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1428795339
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3628602242
Short name T393
Test name
Test status
Simulation time 207278103 ps
CPU time 3.14 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:34:04 PM PDT 24
Peak memory 224644 kb
Host smart-eea19712-5ebb-4adc-8dd8-fe41f141150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628602242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3628602242
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.326373923
Short name T76
Test name
Test status
Simulation time 45824020045 ps
CPU time 305.83 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:39:07 PM PDT 24
Peak memory 256800 kb
Host smart-48f9fadb-1ac1-4df3-96da-a1a76c916b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326373923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.326373923
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2202651698
Short name T185
Test name
Test status
Simulation time 1160752724 ps
CPU time 6.43 seconds
Started Jul 28 05:34:00 PM PDT 24
Finished Jul 28 05:34:07 PM PDT 24
Peak memory 224632 kb
Host smart-bd281eb3-0336-4754-8b1b-f6c729a68b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202651698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2202651698
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3504125989
Short name T846
Test name
Test status
Simulation time 38555268205 ps
CPU time 27.32 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:29 PM PDT 24
Peak memory 239924 kb
Host smart-0a5bb38d-34d6-40f6-b7ba-2cbbb5053812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504125989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3504125989
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3265346652
Short name T656
Test name
Test status
Simulation time 5291398749 ps
CPU time 18.92 seconds
Started Jul 28 05:34:03 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 232872 kb
Host smart-bac780a7-f435-4f15-882d-21338479613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265346652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3265346652
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1800089174
Short name T849
Test name
Test status
Simulation time 5837207503 ps
CPU time 12.26 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:14 PM PDT 24
Peak memory 232852 kb
Host smart-8ef2489d-89e8-48a4-ae33-a0dd2e55f034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800089174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1800089174
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3016449902
Short name T465
Test name
Test status
Simulation time 1401086537 ps
CPU time 13.42 seconds
Started Jul 28 05:34:03 PM PDT 24
Finished Jul 28 05:34:16 PM PDT 24
Peak memory 222728 kb
Host smart-372fd526-4f35-4c72-9553-7090538bf1aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3016449902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3016449902
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4134306112
Short name T583
Test name
Test status
Simulation time 3534380005 ps
CPU time 5.53 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:34:00 PM PDT 24
Peak memory 216456 kb
Host smart-580ee166-12c2-4a18-a414-5e22ddeceba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134306112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4134306112
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.738086543
Short name T802
Test name
Test status
Simulation time 73604225 ps
CPU time 1.14 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:34:02 PM PDT 24
Peak memory 207476 kb
Host smart-5f66bb2d-650b-477f-935f-53deb0ad4ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738086543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.738086543
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.110430532
Short name T511
Test name
Test status
Simulation time 383849232 ps
CPU time 0.83 seconds
Started Jul 28 05:33:54 PM PDT 24
Finished Jul 28 05:33:55 PM PDT 24
Peak memory 206020 kb
Host smart-68b8865f-fff0-4dcd-9716-941c8ac92f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110430532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.110430532
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.4233881169
Short name T916
Test name
Test status
Simulation time 1791597338 ps
CPU time 8.05 seconds
Started Jul 28 05:34:00 PM PDT 24
Finished Jul 28 05:34:08 PM PDT 24
Peak memory 232844 kb
Host smart-a6f2b8b1-93cf-46a7-886c-8b6e76b91960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233881169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4233881169
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.569065180
Short name T728
Test name
Test status
Simulation time 46056184 ps
CPU time 0.72 seconds
Started Jul 28 05:34:06 PM PDT 24
Finished Jul 28 05:34:06 PM PDT 24
Peak memory 205600 kb
Host smart-81e6e05e-ce1e-48a7-848d-24af97f4ec44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569065180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.569065180
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2540029201
Short name T923
Test name
Test status
Simulation time 67915443 ps
CPU time 3.12 seconds
Started Jul 28 05:34:08 PM PDT 24
Finished Jul 28 05:34:11 PM PDT 24
Peak memory 232856 kb
Host smart-b4f4f994-4be6-4ece-9cd7-2c8e1198550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540029201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2540029201
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3693566752
Short name T612
Test name
Test status
Simulation time 51202430 ps
CPU time 0.79 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:03 PM PDT 24
Peak memory 207012 kb
Host smart-9ba2a7b1-1484-436e-81c4-28eabfc6bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693566752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3693566752
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.854147152
Short name T985
Test name
Test status
Simulation time 1306216333 ps
CPU time 14.03 seconds
Started Jul 28 05:34:09 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 240744 kb
Host smart-7f18ec00-8c46-49a3-b269-66cab1f297cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854147152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.854147152
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3299884283
Short name T50
Test name
Test status
Simulation time 22536359047 ps
CPU time 133.86 seconds
Started Jul 28 05:34:06 PM PDT 24
Finished Jul 28 05:36:20 PM PDT 24
Peak memory 273256 kb
Host smart-e24a8d41-7afe-4e4c-a659-1a9d81e75a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299884283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3299884283
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3196673386
Short name T540
Test name
Test status
Simulation time 364358132 ps
CPU time 9.01 seconds
Started Jul 28 05:34:07 PM PDT 24
Finished Jul 28 05:34:17 PM PDT 24
Peak memory 224624 kb
Host smart-7c39f502-371c-420d-9b49-5131d678adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196673386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3196673386
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3311026350
Short name T201
Test name
Test status
Simulation time 18140145864 ps
CPU time 161.04 seconds
Started Jul 28 05:34:08 PM PDT 24
Finished Jul 28 05:36:49 PM PDT 24
Peak memory 255304 kb
Host smart-6dccaabb-5128-4e42-ae72-ada567095176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311026350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3311026350
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1815795707
Short name T363
Test name
Test status
Simulation time 34831657 ps
CPU time 2.88 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:34:04 PM PDT 24
Peak memory 232840 kb
Host smart-6c88e1e6-9b71-4aa6-8490-5718dfbefad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815795707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1815795707
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1462883793
Short name T344
Test name
Test status
Simulation time 82644858 ps
CPU time 2.59 seconds
Started Jul 28 05:34:06 PM PDT 24
Finished Jul 28 05:34:09 PM PDT 24
Peak memory 224656 kb
Host smart-98f8944b-74d6-4578-abe1-d37f954c4fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462883793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1462883793
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2946599139
Short name T10
Test name
Test status
Simulation time 38628076038 ps
CPU time 15.08 seconds
Started Jul 28 05:34:00 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 232908 kb
Host smart-bff9e0e7-4b22-4086-a617-8de135a5f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946599139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2946599139
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.988675712
Short name T1003
Test name
Test status
Simulation time 10728542822 ps
CPU time 26.51 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 224680 kb
Host smart-5c920389-f9b5-4fee-9283-3e567ea53ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988675712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.988675712
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.668032683
Short name T905
Test name
Test status
Simulation time 1653551006 ps
CPU time 6.97 seconds
Started Jul 28 05:34:10 PM PDT 24
Finished Jul 28 05:34:17 PM PDT 24
Peak memory 220708 kb
Host smart-6ca91708-7148-40ed-8766-8015a34af935
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=668032683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.668032683
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2275565199
Short name T563
Test name
Test status
Simulation time 93106985654 ps
CPU time 157.28 seconds
Started Jul 28 05:34:10 PM PDT 24
Finished Jul 28 05:36:48 PM PDT 24
Peak memory 255120 kb
Host smart-8d997cf1-5532-4b2e-b140-96d8c673363a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275565199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2275565199
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2825518485
Short name T317
Test name
Test status
Simulation time 763204123 ps
CPU time 7.87 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:10 PM PDT 24
Peak memory 216720 kb
Host smart-e2df07b0-25c3-4eee-9307-53e2770a075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825518485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2825518485
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.127704301
Short name T645
Test name
Test status
Simulation time 3199644006 ps
CPU time 6.69 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:34:08 PM PDT 24
Peak memory 216484 kb
Host smart-a704d5a3-c73a-4614-aad0-1ae58750aaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127704301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.127704301
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3702821206
Short name T366
Test name
Test status
Simulation time 13034943 ps
CPU time 0.78 seconds
Started Jul 28 05:34:02 PM PDT 24
Finished Jul 28 05:34:03 PM PDT 24
Peak memory 205740 kb
Host smart-4d34e5f1-ed3f-4957-bc1d-8ee2552d4614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702821206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3702821206
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1553693507
Short name T352
Test name
Test status
Simulation time 27135564 ps
CPU time 0.79 seconds
Started Jul 28 05:34:01 PM PDT 24
Finished Jul 28 05:34:02 PM PDT 24
Peak memory 206104 kb
Host smart-0ddc6129-30ec-4a01-bfcd-d3735cd6f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553693507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1553693507
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3063821216
Short name T179
Test name
Test status
Simulation time 3849570042 ps
CPU time 14.37 seconds
Started Jul 28 05:34:06 PM PDT 24
Finished Jul 28 05:34:21 PM PDT 24
Peak memory 232932 kb
Host smart-9a0a21ac-c008-4ec4-8cdd-c9d09b9ce8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063821216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3063821216
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.794162194
Short name T3
Test name
Test status
Simulation time 11884090 ps
CPU time 0.7 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:15 PM PDT 24
Peak memory 205012 kb
Host smart-e6cd3582-3820-42db-a92f-c65f3daacec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794162194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.794162194
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2767801201
Short name T58
Test name
Test status
Simulation time 389798093 ps
CPU time 2.29 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:19 PM PDT 24
Peak memory 224636 kb
Host smart-79ef548a-2280-4f9d-a6b9-7ed4bc8db744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767801201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2767801201
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3288274559
Short name T758
Test name
Test status
Simulation time 113739301 ps
CPU time 0.78 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:32:15 PM PDT 24
Peak memory 205644 kb
Host smart-110f362b-3e56-4f55-9046-cc614c2cd79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288274559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3288274559
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.284675235
Short name T471
Test name
Test status
Simulation time 3350010729 ps
CPU time 22.04 seconds
Started Jul 28 05:32:13 PM PDT 24
Finished Jul 28 05:32:35 PM PDT 24
Peak memory 235668 kb
Host smart-2fc1472b-1c44-420b-bef9-a008deff0098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284675235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.284675235
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.220257888
Short name T286
Test name
Test status
Simulation time 31866680070 ps
CPU time 132.79 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:34:27 PM PDT 24
Peak memory 249284 kb
Host smart-9c2f5d27-eee5-450f-adaf-daf43d5a04df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220257888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
220257888
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2690756571
Short name T949
Test name
Test status
Simulation time 29747258271 ps
CPU time 42.59 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 232872 kb
Host smart-36a1cb12-3d78-48b9-9d4b-79b5c0305c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690756571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2690756571
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2000257098
Short name T500
Test name
Test status
Simulation time 6606130212 ps
CPU time 24.83 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:42 PM PDT 24
Peak memory 251336 kb
Host smart-f1b47d09-4281-4048-9639-63da13e4d2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000257098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2000257098
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.511356089
Short name T622
Test name
Test status
Simulation time 585125836 ps
CPU time 4.84 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:22 PM PDT 24
Peak memory 224652 kb
Host smart-125c8699-7973-41c3-b671-3a095933e3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511356089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.511356089
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4104614157
Short name T248
Test name
Test status
Simulation time 13946813352 ps
CPU time 62.15 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:33:18 PM PDT 24
Peak memory 232828 kb
Host smart-7d23f954-ee95-4705-abc9-4a4250c17dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104614157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4104614157
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1637754732
Short name T778
Test name
Test status
Simulation time 2007404869 ps
CPU time 6.53 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:32:22 PM PDT 24
Peak memory 232828 kb
Host smart-e68ac4d3-31ce-4e67-94f2-c90988e17e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637754732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1637754732
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.835417911
Short name T224
Test name
Test status
Simulation time 1410784865 ps
CPU time 9.44 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:24 PM PDT 24
Peak memory 232844 kb
Host smart-d9d1e4bf-4b67-4755-af0f-fb167fc47562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835417911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.835417911
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.355782492
Short name T576
Test name
Test status
Simulation time 396094986 ps
CPU time 4.2 seconds
Started Jul 28 05:32:13 PM PDT 24
Finished Jul 28 05:32:18 PM PDT 24
Peak memory 219456 kb
Host smart-16451b36-e9bf-43b8-8d23-ceadcc4480f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355782492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.355782492
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.91484987
Short name T68
Test name
Test status
Simulation time 36868691 ps
CPU time 1.07 seconds
Started Jul 28 05:32:18 PM PDT 24
Finished Jul 28 05:32:19 PM PDT 24
Peak memory 236456 kb
Host smart-15ee922f-9e1a-4ce2-ac44-815efe580e90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91484987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.91484987
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2548351441
Short name T312
Test name
Test status
Simulation time 2620137104 ps
CPU time 13.46 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:30 PM PDT 24
Peak memory 216464 kb
Host smart-e26b335d-a0eb-414d-af29-37fb2d6026aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548351441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2548351441
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1991866303
Short name T902
Test name
Test status
Simulation time 39045471384 ps
CPU time 15.23 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:31 PM PDT 24
Peak memory 216420 kb
Host smart-b748c4c1-ca9a-4a88-9dcf-0530166466d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991866303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1991866303
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2326819231
Short name T913
Test name
Test status
Simulation time 131756714 ps
CPU time 1.79 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:32:17 PM PDT 24
Peak memory 216408 kb
Host smart-0e6b7d7d-0564-467e-8c46-f757913aacb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326819231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2326819231
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.964288285
Short name T872
Test name
Test status
Simulation time 63728793 ps
CPU time 0.76 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:32:16 PM PDT 24
Peak memory 206076 kb
Host smart-19cefc82-c4e7-4e1b-a0fe-2871444b4ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964288285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.964288285
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1555839296
Short name T919
Test name
Test status
Simulation time 6938874170 ps
CPU time 22.71 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:40 PM PDT 24
Peak memory 234636 kb
Host smart-a605ad6a-b466-4c70-b3f5-1dcdfe6acb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555839296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1555839296
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3823848448
Short name T842
Test name
Test status
Simulation time 35960473 ps
CPU time 0.69 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 205000 kb
Host smart-f7ba228c-29cb-497b-ab4b-8dab679696b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823848448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3823848448
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3611138805
Short name T843
Test name
Test status
Simulation time 3418169769 ps
CPU time 34.29 seconds
Started Jul 28 05:34:12 PM PDT 24
Finished Jul 28 05:34:47 PM PDT 24
Peak memory 224712 kb
Host smart-6fd2997a-fe71-4c34-b340-5b454fd28b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611138805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3611138805
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1428951352
Short name T334
Test name
Test status
Simulation time 35729910 ps
CPU time 0.77 seconds
Started Jul 28 05:34:08 PM PDT 24
Finished Jul 28 05:34:09 PM PDT 24
Peak memory 206660 kb
Host smart-6880eae0-173a-4de5-838c-45efb7b8fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428951352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1428951352
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2885751376
Short name T722
Test name
Test status
Simulation time 117411764936 ps
CPU time 179.9 seconds
Started Jul 28 05:34:09 PM PDT 24
Finished Jul 28 05:37:09 PM PDT 24
Peak memory 249304 kb
Host smart-147ec132-807c-4263-a7a7-60b85c13902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885751376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2885751376
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.262644393
Short name T528
Test name
Test status
Simulation time 7614012466 ps
CPU time 24.55 seconds
Started Jul 28 05:34:09 PM PDT 24
Finished Jul 28 05:34:33 PM PDT 24
Peak memory 217740 kb
Host smart-7ebdb1fa-3d44-4541-921b-27aa95433b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262644393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.262644393
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2983872357
Short name T879
Test name
Test status
Simulation time 2784396744 ps
CPU time 47.08 seconds
Started Jul 28 05:34:05 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 224684 kb
Host smart-277fc08e-5401-4860-95be-7a4476efe9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983872357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2983872357
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2312196788
Short name T46
Test name
Test status
Simulation time 326908191954 ps
CPU time 166.31 seconds
Started Jul 28 05:34:12 PM PDT 24
Finished Jul 28 05:36:59 PM PDT 24
Peak memory 236120 kb
Host smart-7e354893-e4b7-4dcd-8e22-3e362800b55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312196788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2312196788
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1785998815
Short name T464
Test name
Test status
Simulation time 164577826 ps
CPU time 3.45 seconds
Started Jul 28 05:34:08 PM PDT 24
Finished Jul 28 05:34:12 PM PDT 24
Peak memory 232892 kb
Host smart-e2cb1f9f-fb14-4a06-adfd-1ed7c7612eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785998815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1785998815
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.748823358
Short name T673
Test name
Test status
Simulation time 259529036 ps
CPU time 3.88 seconds
Started Jul 28 05:34:09 PM PDT 24
Finished Jul 28 05:34:13 PM PDT 24
Peak memory 224708 kb
Host smart-b30f0763-11d0-4de4-8a83-a6244035824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748823358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.748823358
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.848254791
Short name T153
Test name
Test status
Simulation time 29668353067 ps
CPU time 20.83 seconds
Started Jul 28 05:34:07 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 232960 kb
Host smart-1329c2b6-0628-48be-996f-ea27f7a8dbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848254791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.848254791
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1907577471
Short name T858
Test name
Test status
Simulation time 3263674631 ps
CPU time 10.09 seconds
Started Jul 28 05:34:04 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 232792 kb
Host smart-79a51ef1-fd83-4896-a232-c25f1aa767bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907577471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1907577471
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.392848047
Short name T871
Test name
Test status
Simulation time 1147852270 ps
CPU time 11.33 seconds
Started Jul 28 05:34:12 PM PDT 24
Finished Jul 28 05:34:24 PM PDT 24
Peak memory 219636 kb
Host smart-64f90bea-7aed-45c0-a94d-cacc135c5112
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=392848047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.392848047
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1137203067
Short name T662
Test name
Test status
Simulation time 30723921805 ps
CPU time 45.23 seconds
Started Jul 28 05:34:07 PM PDT 24
Finished Jul 28 05:34:52 PM PDT 24
Peak memory 216632 kb
Host smart-e353be38-460c-4a35-a876-537e7dd7e555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137203067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1137203067
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4147134644
Short name T809
Test name
Test status
Simulation time 737618354 ps
CPU time 2.58 seconds
Started Jul 28 05:34:13 PM PDT 24
Finished Jul 28 05:34:16 PM PDT 24
Peak memory 216344 kb
Host smart-94ebd77a-dcc1-4894-a0b8-665b85273707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147134644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4147134644
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1058836510
Short name T934
Test name
Test status
Simulation time 45371465 ps
CPU time 0.74 seconds
Started Jul 28 05:34:09 PM PDT 24
Finished Jul 28 05:34:10 PM PDT 24
Peak memory 206088 kb
Host smart-45b8b12a-b2c3-4936-a829-7f8f70d5bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058836510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1058836510
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.118035724
Short name T740
Test name
Test status
Simulation time 54429059 ps
CPU time 0.76 seconds
Started Jul 28 05:34:07 PM PDT 24
Finished Jul 28 05:34:08 PM PDT 24
Peak memory 206096 kb
Host smart-290f817e-a57a-4d62-a2ad-45dc5e96ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118035724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.118035724
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1088305242
Short name T735
Test name
Test status
Simulation time 2889522328 ps
CPU time 7.41 seconds
Started Jul 28 05:34:07 PM PDT 24
Finished Jul 28 05:34:14 PM PDT 24
Peak memory 232940 kb
Host smart-d43116eb-7404-4329-bb59-a3ed36796268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088305242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1088305242
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4199264998
Short name T362
Test name
Test status
Simulation time 14200307 ps
CPU time 0.72 seconds
Started Jul 28 05:34:17 PM PDT 24
Finished Jul 28 05:34:18 PM PDT 24
Peak memory 205508 kb
Host smart-e63fac6c-ed44-4c71-8a9c-a4abba0a325a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199264998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4199264998
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3000574169
Short name T590
Test name
Test status
Simulation time 170287683 ps
CPU time 4.38 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:18 PM PDT 24
Peak memory 224712 kb
Host smart-0eeb2caf-36cb-44ce-91eb-3162cf9c004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000574169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3000574169
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.105880651
Short name T1
Test name
Test status
Simulation time 21488708 ps
CPU time 0.8 seconds
Started Jul 28 05:34:17 PM PDT 24
Finished Jul 28 05:34:17 PM PDT 24
Peak memory 206692 kb
Host smart-932aee8c-d90a-42a2-a732-8ae4427d5805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105880651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.105880651
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3901642772
Short name T281
Test name
Test status
Simulation time 13294104485 ps
CPU time 137.82 seconds
Started Jul 28 05:34:13 PM PDT 24
Finished Jul 28 05:36:31 PM PDT 24
Peak memory 266568 kb
Host smart-d700e143-945c-43a3-85ee-b350956b2c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901642772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3901642772
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1594215728
Short name T692
Test name
Test status
Simulation time 105350323406 ps
CPU time 119.43 seconds
Started Jul 28 05:34:15 PM PDT 24
Finished Jul 28 05:36:15 PM PDT 24
Peak memory 241316 kb
Host smart-011adacf-a656-4a10-b590-30cde73be8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594215728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1594215728
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4238298463
Short name T629
Test name
Test status
Simulation time 27223766682 ps
CPU time 230.87 seconds
Started Jul 28 05:34:15 PM PDT 24
Finished Jul 28 05:38:06 PM PDT 24
Peak memory 266388 kb
Host smart-c2e6efd3-646f-4502-82b3-36f0a6b91c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238298463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4238298463
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4095501883
Short name T389
Test name
Test status
Simulation time 1665543009 ps
CPU time 3.47 seconds
Started Jul 28 05:34:17 PM PDT 24
Finished Jul 28 05:34:20 PM PDT 24
Peak memory 224648 kb
Host smart-e5cb8f2f-6547-44b3-b10e-d0c41b28f574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095501883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4095501883
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.877971427
Short name T407
Test name
Test status
Simulation time 12569075666 ps
CPU time 103.87 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:35:58 PM PDT 24
Peak memory 250408 kb
Host smart-c6c69187-49ff-42b5-8da7-95c954c474f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877971427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.877971427
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4087173087
Short name T957
Test name
Test status
Simulation time 265983366 ps
CPU time 5.68 seconds
Started Jul 28 05:34:17 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 232804 kb
Host smart-3a04e5e8-d4e6-4f33-8bf2-51bc668ea30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087173087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4087173087
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1011330603
Short name T325
Test name
Test status
Simulation time 11840366115 ps
CPU time 82.66 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:35:36 PM PDT 24
Peak memory 232936 kb
Host smart-b079fa1a-cbad-4542-bd5b-763781819a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011330603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1011330603
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.913359197
Short name T554
Test name
Test status
Simulation time 1662291899 ps
CPU time 7.95 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 232776 kb
Host smart-f158ee45-aefb-43f6-86f9-bbf5ee64d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913359197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.913359197
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1097250868
Short name T424
Test name
Test status
Simulation time 1262403903 ps
CPU time 7.69 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 224620 kb
Host smart-8568064f-4de8-4ce1-826b-b9fe3924efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097250868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1097250868
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3436980559
Short name T627
Test name
Test status
Simulation time 538999033 ps
CPU time 3.61 seconds
Started Jul 28 05:34:16 PM PDT 24
Finished Jul 28 05:34:19 PM PDT 24
Peak memory 219640 kb
Host smart-81bac7bb-879a-48f7-82ea-301f9d9c3b2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3436980559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3436980559
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.758740987
Short name T145
Test name
Test status
Simulation time 43789142382 ps
CPU time 129.49 seconds
Started Jul 28 05:34:17 PM PDT 24
Finished Jul 28 05:36:26 PM PDT 24
Peak memory 266444 kb
Host smart-c75b5bf3-8ca8-482f-81cd-f1056e4c2738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758740987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.758740987
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1906709180
Short name T474
Test name
Test status
Simulation time 1699230370 ps
CPU time 19.68 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:34 PM PDT 24
Peak memory 216364 kb
Host smart-96d22e84-36cd-43cc-bd78-1988c41d9b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906709180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1906709180
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3286489325
Short name T973
Test name
Test status
Simulation time 1151477966 ps
CPU time 7.12 seconds
Started Jul 28 05:34:15 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 216444 kb
Host smart-d9460d7d-8ba5-4e0d-be5b-6ee4883eaea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286489325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3286489325
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3464945166
Short name T551
Test name
Test status
Simulation time 76196772 ps
CPU time 1.94 seconds
Started Jul 28 05:34:20 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 208208 kb
Host smart-5324fd20-72e7-432a-9063-e210901e07fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464945166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3464945166
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2764538839
Short name T116
Test name
Test status
Simulation time 80412157 ps
CPU time 1 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 206080 kb
Host smart-a473ab31-e5ac-4489-a96f-8fa518e45c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764538839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2764538839
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3513748108
Short name T41
Test name
Test status
Simulation time 37842053 ps
CPU time 2.7 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:17 PM PDT 24
Peak memory 224304 kb
Host smart-bb3c6bcf-2da3-4b9b-b737-bf4350a34212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513748108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3513748108
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4222440183
Short name T477
Test name
Test status
Simulation time 12342495 ps
CPU time 0.74 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:21 PM PDT 24
Peak memory 204916 kb
Host smart-9288357a-e45f-4bf9-8402-38dcab869784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222440183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4222440183
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.850818288
Short name T426
Test name
Test status
Simulation time 58309346 ps
CPU time 2.75 seconds
Started Jul 28 05:34:23 PM PDT 24
Finished Jul 28 05:34:26 PM PDT 24
Peak memory 232868 kb
Host smart-0fbd1d43-8671-4e31-92af-048c1535ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850818288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.850818288
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4281453750
Short name T374
Test name
Test status
Simulation time 32468244 ps
CPU time 0.8 seconds
Started Jul 28 05:34:16 PM PDT 24
Finished Jul 28 05:34:17 PM PDT 24
Peak memory 205980 kb
Host smart-c0d6c8de-599c-44b5-bce9-67c179b750f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281453750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4281453750
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1022911906
Short name T176
Test name
Test status
Simulation time 17084105584 ps
CPU time 102.13 seconds
Started Jul 28 05:34:25 PM PDT 24
Finished Jul 28 05:36:07 PM PDT 24
Peak memory 249120 kb
Host smart-5ed6ba46-8e42-4410-8d37-10fdb9c955c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022911906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1022911906
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2541061325
Short name T835
Test name
Test status
Simulation time 49819871420 ps
CPU time 120.99 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:36:22 PM PDT 24
Peak memory 265984 kb
Host smart-613a8445-a778-44b6-882d-521ccd087c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541061325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2541061325
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1190116023
Short name T653
Test name
Test status
Simulation time 45170978938 ps
CPU time 84.77 seconds
Started Jul 28 05:34:20 PM PDT 24
Finished Jul 28 05:35:45 PM PDT 24
Peak memory 240804 kb
Host smart-595ed8f7-2b6e-437a-9575-df1371086bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190116023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1190116023
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3600103163
Short name T589
Test name
Test status
Simulation time 3053732749 ps
CPU time 58.56 seconds
Started Jul 28 05:34:23 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 249484 kb
Host smart-4f6853c5-cb17-44d3-8105-c4ca64bacbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600103163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3600103163
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.592618312
Short name T228
Test name
Test status
Simulation time 4127394304 ps
CPU time 9.14 seconds
Started Jul 28 05:34:24 PM PDT 24
Finished Jul 28 05:34:33 PM PDT 24
Peak memory 224724 kb
Host smart-b6a44819-9cdd-4c4c-ab94-40752f12b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592618312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.592618312
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1933602991
Short name T196
Test name
Test status
Simulation time 40551633123 ps
CPU time 26.1 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:48 PM PDT 24
Peak memory 232920 kb
Host smart-0594d4f7-fd6d-43ad-bc2f-ef9420441228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933602991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1933602991
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4115508359
Short name T182
Test name
Test status
Simulation time 1073656687 ps
CPU time 4.99 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:27 PM PDT 24
Peak memory 224608 kb
Host smart-3eef639d-0274-4c99-be04-1e821b321f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115508359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4115508359
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2318117597
Short name T118
Test name
Test status
Simulation time 1631100674 ps
CPU time 7.87 seconds
Started Jul 28 05:34:24 PM PDT 24
Finished Jul 28 05:34:32 PM PDT 24
Peak memory 240400 kb
Host smart-38c10491-ff17-42f5-baaf-0eaf6261dd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318117597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2318117597
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4116057870
Short name T431
Test name
Test status
Simulation time 297620989 ps
CPU time 4.49 seconds
Started Jul 28 05:34:25 PM PDT 24
Finished Jul 28 05:34:30 PM PDT 24
Peak memory 220588 kb
Host smart-91bd65db-b0a5-4e7b-838b-afb8bba93659
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4116057870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4116057870
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.864202844
Short name T711
Test name
Test status
Simulation time 15094728655 ps
CPU time 25.89 seconds
Started Jul 28 05:34:19 PM PDT 24
Finished Jul 28 05:34:45 PM PDT 24
Peak memory 224696 kb
Host smart-25538af8-dda4-45ba-a5b6-d57a37b892e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864202844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.864202844
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.479253332
Short name T304
Test name
Test status
Simulation time 6151538247 ps
CPU time 27.43 seconds
Started Jul 28 05:34:15 PM PDT 24
Finished Jul 28 05:34:42 PM PDT 24
Peak memory 216756 kb
Host smart-9a542e64-6f0a-46dd-8c1e-efbbb931b6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479253332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.479253332
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.479530665
Short name T823
Test name
Test status
Simulation time 3239920933 ps
CPU time 7.98 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 216436 kb
Host smart-4f710765-4c1c-4679-bb99-d0408bb12055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479530665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.479530665
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2596333787
Short name T493
Test name
Test status
Simulation time 106624835 ps
CPU time 1.84 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:16 PM PDT 24
Peak memory 216404 kb
Host smart-87409886-dec1-4421-861f-d62cd9b78c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596333787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2596333787
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1563866872
Short name T320
Test name
Test status
Simulation time 33401478 ps
CPU time 0.72 seconds
Started Jul 28 05:34:14 PM PDT 24
Finished Jul 28 05:34:15 PM PDT 24
Peak memory 206052 kb
Host smart-cf5b739a-40ba-4cba-96ac-379446cb6821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563866872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1563866872
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4011120887
Short name T229
Test name
Test status
Simulation time 1793550271 ps
CPU time 7.15 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:30 PM PDT 24
Peak memory 232980 kb
Host smart-5dbbaed6-47ee-4a64-b891-5f9e6be80e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011120887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4011120887
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4019892439
Short name T796
Test name
Test status
Simulation time 13879288 ps
CPU time 0.7 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:22 PM PDT 24
Peak memory 205468 kb
Host smart-1c278a60-f0ba-4457-b46b-b5e01ba8c4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019892439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4019892439
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1892207593
Short name T807
Test name
Test status
Simulation time 1171701503 ps
CPU time 8.74 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:31 PM PDT 24
Peak memory 232868 kb
Host smart-8f4e918e-aa89-4cd8-92cd-1c9ee41e83b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892207593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1892207593
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4034185221
Short name T757
Test name
Test status
Simulation time 17372143 ps
CPU time 0.81 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 207012 kb
Host smart-ae415f20-be8c-4541-8ab0-108adc410965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034185221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4034185221
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3482093580
Short name T181
Test name
Test status
Simulation time 14069271125 ps
CPU time 95.13 seconds
Started Jul 28 05:34:25 PM PDT 24
Finished Jul 28 05:36:00 PM PDT 24
Peak memory 266096 kb
Host smart-a76dc995-a14f-4869-a99c-17bb9fba58c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482093580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3482093580
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2568937424
Short name T226
Test name
Test status
Simulation time 118100116270 ps
CPU time 220.25 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:38:03 PM PDT 24
Peak memory 252300 kb
Host smart-1c4e6102-d1a7-4462-8e0a-19b88c80b34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568937424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2568937424
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2594249350
Short name T297
Test name
Test status
Simulation time 261185948 ps
CPU time 7.07 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 232796 kb
Host smart-90df4884-3dbb-4b21-a667-3f46309f794e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594249350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2594249350
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3304896219
Short name T166
Test name
Test status
Simulation time 65088349421 ps
CPU time 385.19 seconds
Started Jul 28 05:34:19 PM PDT 24
Finished Jul 28 05:40:44 PM PDT 24
Peak memory 256140 kb
Host smart-acf99217-1214-4eb9-ba70-9199ba77b440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304896219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3304896219
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1125751687
Short name T731
Test name
Test status
Simulation time 684568099 ps
CPU time 4.77 seconds
Started Jul 28 05:34:24 PM PDT 24
Finished Jul 28 05:34:29 PM PDT 24
Peak memory 224668 kb
Host smart-c3c1ba88-55e7-4144-b440-3c64f7ff3a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125751687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1125751687
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3371657916
Short name T682
Test name
Test status
Simulation time 2524459385 ps
CPU time 26.73 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:49 PM PDT 24
Peak memory 224688 kb
Host smart-0dfb1157-bf2b-48a8-a675-39cb9e35ae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371657916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3371657916
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3725694243
Short name T945
Test name
Test status
Simulation time 114898394 ps
CPU time 2.33 seconds
Started Jul 28 05:34:24 PM PDT 24
Finished Jul 28 05:34:27 PM PDT 24
Peak memory 232612 kb
Host smart-689cde29-f91d-4e69-ba2e-0223cf658893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725694243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3725694243
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.934624159
Short name T775
Test name
Test status
Simulation time 4775109522 ps
CPU time 18.67 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 224652 kb
Host smart-0fa44a6e-3878-4a4c-a9ed-922af85f8b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934624159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.934624159
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.226326869
Short name T436
Test name
Test status
Simulation time 7118841688 ps
CPU time 15.93 seconds
Started Jul 28 05:34:23 PM PDT 24
Finished Jul 28 05:34:39 PM PDT 24
Peak memory 220540 kb
Host smart-1fe817ee-91f4-4f58-80d5-099656d57c15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=226326869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.226326869
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1705214166
Short name T313
Test name
Test status
Simulation time 1124082640 ps
CPU time 11.96 seconds
Started Jul 28 05:34:23 PM PDT 24
Finished Jul 28 05:34:35 PM PDT 24
Peak memory 223660 kb
Host smart-5abd146a-d67b-4045-9ab0-7ae2bb675cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705214166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1705214166
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.484311084
Short name T309
Test name
Test status
Simulation time 824274588 ps
CPU time 13.06 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:34 PM PDT 24
Peak memory 216448 kb
Host smart-c25643dd-32ae-4aa4-b7a0-507028aec3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484311084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.484311084
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3886527530
Short name T531
Test name
Test status
Simulation time 1413404669 ps
CPU time 6.27 seconds
Started Jul 28 05:34:19 PM PDT 24
Finished Jul 28 05:34:26 PM PDT 24
Peak memory 216332 kb
Host smart-0e7a647a-db52-43c8-858a-4ecca9de7e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886527530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3886527530
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3300368478
Short name T751
Test name
Test status
Simulation time 85793102 ps
CPU time 1.81 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 216436 kb
Host smart-4fd5d428-eb5f-4292-862e-36ea1f8e8299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300368478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3300368478
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.977349045
Short name T1006
Test name
Test status
Simulation time 50286512 ps
CPU time 0.83 seconds
Started Jul 28 05:34:23 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 206032 kb
Host smart-893039e8-9229-41ad-bec1-cbd9365e9445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977349045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.977349045
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1536059941
Short name T261
Test name
Test status
Simulation time 73491101448 ps
CPU time 16.33 seconds
Started Jul 28 05:34:23 PM PDT 24
Finished Jul 28 05:34:39 PM PDT 24
Peak memory 232888 kb
Host smart-e5ca98fe-97d1-4739-aef9-ca0265464cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536059941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1536059941
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1895512548
Short name T523
Test name
Test status
Simulation time 53165828 ps
CPU time 0.77 seconds
Started Jul 28 05:34:31 PM PDT 24
Finished Jul 28 05:34:32 PM PDT 24
Peak memory 204992 kb
Host smart-05c42c60-a55a-48ed-ae37-692b1f531b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895512548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1895512548
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3531517744
Short name T689
Test name
Test status
Simulation time 896513352 ps
CPU time 3.45 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:25 PM PDT 24
Peak memory 232864 kb
Host smart-425dcdf0-24e0-409d-aaa3-95ea206b859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531517744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3531517744
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3184759469
Short name T518
Test name
Test status
Simulation time 14619801 ps
CPU time 0.8 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:23 PM PDT 24
Peak memory 205644 kb
Host smart-ecbef634-022d-4f03-b3af-79a1926545dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184759469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3184759469
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2894134128
Short name T152
Test name
Test status
Simulation time 74806003870 ps
CPU time 82.03 seconds
Started Jul 28 05:34:26 PM PDT 24
Finished Jul 28 05:35:48 PM PDT 24
Peak memory 241076 kb
Host smart-5f139bb6-df88-4697-be0d-5788e9411f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894134128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2894134128
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2544832951
Short name T571
Test name
Test status
Simulation time 80466234343 ps
CPU time 380.23 seconds
Started Jul 28 05:34:31 PM PDT 24
Finished Jul 28 05:40:51 PM PDT 24
Peak memory 266952 kb
Host smart-e9e311dd-5459-4ffc-8f86-afd604ca0972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544832951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2544832951
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3162376449
Short name T404
Test name
Test status
Simulation time 158352218 ps
CPU time 3.74 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:26 PM PDT 24
Peak memory 232904 kb
Host smart-9fc20ad6-0411-46b8-a967-0e10ff29c9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162376449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3162376449
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.4161230517
Short name T77
Test name
Test status
Simulation time 2144841958 ps
CPU time 14.03 seconds
Started Jul 28 05:34:27 PM PDT 24
Finished Jul 28 05:34:41 PM PDT 24
Peak memory 224684 kb
Host smart-c379ad6f-dbf2-43bd-b99e-87c1f86fb1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161230517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.4161230517
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2811887955
Short name T351
Test name
Test status
Simulation time 3010244086 ps
CPU time 8.27 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:30 PM PDT 24
Peak memory 232948 kb
Host smart-a455c283-41a5-4bd8-8179-30853f40afae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811887955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2811887955
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.414058782
Short name T258
Test name
Test status
Simulation time 826999167 ps
CPU time 12.63 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:35 PM PDT 24
Peak memory 224676 kb
Host smart-0be0c9e0-9fec-429b-8c56-42608f57dec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414058782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.414058782
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1770688259
Short name T412
Test name
Test status
Simulation time 1258325287 ps
CPU time 9.47 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:31 PM PDT 24
Peak memory 232872 kb
Host smart-39959938-df99-47ae-ad93-0130f173d241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770688259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1770688259
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2333230444
Short name T246
Test name
Test status
Simulation time 898125984 ps
CPU time 6.72 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:28 PM PDT 24
Peak memory 224628 kb
Host smart-63200629-192d-412e-9009-9ce1c204f499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333230444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2333230444
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3147002503
Short name T555
Test name
Test status
Simulation time 1788962284 ps
CPU time 15.83 seconds
Started Jul 28 05:34:28 PM PDT 24
Finished Jul 28 05:34:43 PM PDT 24
Peak memory 220656 kb
Host smart-c1bf8420-0547-4271-af04-035776d0f668
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3147002503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3147002503
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3080000195
Short name T610
Test name
Test status
Simulation time 68797872856 ps
CPU time 122.52 seconds
Started Jul 28 05:34:29 PM PDT 24
Finished Jul 28 05:36:31 PM PDT 24
Peak memory 249316 kb
Host smart-36689428-0152-4064-8643-c5d60a9527c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080000195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3080000195
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1045668159
Short name T745
Test name
Test status
Simulation time 1177931568 ps
CPU time 8.42 seconds
Started Jul 28 05:34:21 PM PDT 24
Finished Jul 28 05:34:30 PM PDT 24
Peak memory 216352 kb
Host smart-3be936b7-ba91-48c5-b23a-8e7b0f7a82e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045668159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1045668159
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3893604663
Short name T996
Test name
Test status
Simulation time 3165319369 ps
CPU time 11.43 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:34 PM PDT 24
Peak memory 216540 kb
Host smart-30e5b66a-1b42-4d3a-8512-8f5e53a71de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893604663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3893604663
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.417454457
Short name T841
Test name
Test status
Simulation time 280114107 ps
CPU time 3.19 seconds
Started Jul 28 05:34:22 PM PDT 24
Finished Jul 28 05:34:26 PM PDT 24
Peak memory 216452 kb
Host smart-e6fc705e-f061-4101-a27f-b92b795ddc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417454457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.417454457
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1261680708
Short name T572
Test name
Test status
Simulation time 270443332 ps
CPU time 0.81 seconds
Started Jul 28 05:34:20 PM PDT 24
Finished Jul 28 05:34:21 PM PDT 24
Peak memory 207096 kb
Host smart-5c18e8d7-dc31-4a6e-9981-1a25fb1e8277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261680708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1261680708
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2381453627
Short name T534
Test name
Test status
Simulation time 2803419908 ps
CPU time 6.23 seconds
Started Jul 28 05:34:20 PM PDT 24
Finished Jul 28 05:34:26 PM PDT 24
Peak memory 240936 kb
Host smart-ca534ae7-c157-4e5e-9e02-a6ba2e6fba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381453627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2381453627
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1546708375
Short name T894
Test name
Test status
Simulation time 45511977 ps
CPU time 0.76 seconds
Started Jul 28 05:34:38 PM PDT 24
Finished Jul 28 05:34:38 PM PDT 24
Peak memory 204976 kb
Host smart-8d8b4a0b-c451-4397-b999-88db38180d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546708375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1546708375
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1632213117
Short name T234
Test name
Test status
Simulation time 605658843 ps
CPU time 5.02 seconds
Started Jul 28 05:34:28 PM PDT 24
Finished Jul 28 05:34:33 PM PDT 24
Peak memory 224624 kb
Host smart-4765b5c0-cdca-47d3-980f-b66d3ecfc2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632213117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1632213117
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1389988274
Short name T660
Test name
Test status
Simulation time 51113040 ps
CPU time 0.78 seconds
Started Jul 28 05:34:28 PM PDT 24
Finished Jul 28 05:34:29 PM PDT 24
Peak memory 206740 kb
Host smart-b580fd93-325d-4162-8069-1ed966d22eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389988274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1389988274
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3284740614
Short name T883
Test name
Test status
Simulation time 81924275301 ps
CPU time 168.4 seconds
Started Jul 28 05:34:29 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 261604 kb
Host smart-f16eb3e6-bca5-4fc9-8d57-3585a37ea1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284740614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3284740614
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3817002594
Short name T787
Test name
Test status
Simulation time 7687426381 ps
CPU time 41.16 seconds
Started Jul 28 05:34:35 PM PDT 24
Finished Jul 28 05:35:16 PM PDT 24
Peak memory 252068 kb
Host smart-ec9521f0-9ee5-45d6-88d0-a78296a91760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817002594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3817002594
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2914544836
Short name T69
Test name
Test status
Simulation time 29488145007 ps
CPU time 122.62 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:36:39 PM PDT 24
Peak memory 251416 kb
Host smart-cd53d60f-7d06-4137-8e00-6e2ad5992d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914544836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2914544836
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1437735116
Short name T972
Test name
Test status
Simulation time 440944714 ps
CPU time 4.52 seconds
Started Jul 28 05:34:30 PM PDT 24
Finished Jul 28 05:34:35 PM PDT 24
Peak memory 235384 kb
Host smart-b134e499-f17b-46dc-9ba5-1bf3ba4c1069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437735116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1437735116
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3406340719
Short name T383
Test name
Test status
Simulation time 9455258643 ps
CPU time 64.75 seconds
Started Jul 28 05:34:27 PM PDT 24
Finished Jul 28 05:35:32 PM PDT 24
Peak memory 239468 kb
Host smart-271dda50-6f28-491c-ba44-6ac78e59044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406340719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3406340719
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4081124263
Short name T929
Test name
Test status
Simulation time 4522702800 ps
CPU time 10.87 seconds
Started Jul 28 05:34:29 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 232948 kb
Host smart-65f117d4-2584-4c54-928e-895f88507ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081124263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4081124263
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3260842019
Short name T895
Test name
Test status
Simulation time 15668311012 ps
CPU time 33.42 seconds
Started Jul 28 05:34:27 PM PDT 24
Finished Jul 28 05:35:00 PM PDT 24
Peak memory 248968 kb
Host smart-81659f93-d9d9-4c01-9905-77a6ed2a6d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260842019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3260842019
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.203427831
Short name T1000
Test name
Test status
Simulation time 4027615626 ps
CPU time 18.08 seconds
Started Jul 28 05:34:26 PM PDT 24
Finished Jul 28 05:34:45 PM PDT 24
Peak memory 232948 kb
Host smart-cf5d884f-4b7e-4df0-a3c4-02e944819ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203427831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.203427831
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1878203938
Short name T866
Test name
Test status
Simulation time 482050243 ps
CPU time 9.86 seconds
Started Jul 28 05:34:26 PM PDT 24
Finished Jul 28 05:34:36 PM PDT 24
Peak memory 218972 kb
Host smart-d93b8ff0-589a-49a0-a958-9bbadf7182cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1878203938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1878203938
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.638432430
Short name T704
Test name
Test status
Simulation time 27540321957 ps
CPU time 158.02 seconds
Started Jul 28 05:34:37 PM PDT 24
Finished Jul 28 05:37:15 PM PDT 24
Peak memory 267092 kb
Host smart-144374bb-c1df-45c6-99d1-6fe28d3ed57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638432430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.638432430
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1825099160
Short name T837
Test name
Test status
Simulation time 2604466660 ps
CPU time 22.7 seconds
Started Jul 28 05:34:29 PM PDT 24
Finished Jul 28 05:34:52 PM PDT 24
Peak memory 219728 kb
Host smart-9aee4a6c-980c-4ecc-b165-08eaf740b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825099160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1825099160
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3157679217
Short name T856
Test name
Test status
Simulation time 2710961673 ps
CPU time 4.72 seconds
Started Jul 28 05:34:27 PM PDT 24
Finished Jul 28 05:34:32 PM PDT 24
Peak memory 216376 kb
Host smart-0f585888-12c0-4755-8b30-619584c99b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157679217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3157679217
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3141873321
Short name T961
Test name
Test status
Simulation time 17371298 ps
CPU time 0.73 seconds
Started Jul 28 05:34:28 PM PDT 24
Finished Jul 28 05:34:29 PM PDT 24
Peak memory 205744 kb
Host smart-6cfeb324-c9da-4685-b4aa-38f0cbb7d50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141873321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3141873321
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.644525625
Short name T617
Test name
Test status
Simulation time 133473995 ps
CPU time 0.9 seconds
Started Jul 28 05:34:32 PM PDT 24
Finished Jul 28 05:34:33 PM PDT 24
Peak memory 206264 kb
Host smart-ecf17b8e-0deb-4375-bfc5-bf6b54eb94b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644525625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.644525625
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2571023720
Short name T451
Test name
Test status
Simulation time 3893002046 ps
CPU time 15.22 seconds
Started Jul 28 05:34:27 PM PDT 24
Finished Jul 28 05:34:42 PM PDT 24
Peak memory 232880 kb
Host smart-be4f404d-007a-41f0-819e-eb32a2a439eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571023720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2571023720
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.528642087
Short name T480
Test name
Test status
Simulation time 18964753 ps
CPU time 0.73 seconds
Started Jul 28 05:34:38 PM PDT 24
Finished Jul 28 05:34:39 PM PDT 24
Peak memory 205876 kb
Host smart-28f0e813-6445-49c1-82b9-fd31c6e68e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528642087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.528642087
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1543439965
Short name T638
Test name
Test status
Simulation time 253043726 ps
CPU time 5.22 seconds
Started Jul 28 05:34:33 PM PDT 24
Finished Jul 28 05:34:38 PM PDT 24
Peak memory 232856 kb
Host smart-9a8a09bf-306e-40b5-be68-980efad3d264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543439965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1543439965
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1855485210
Short name T864
Test name
Test status
Simulation time 53798407 ps
CPU time 0.8 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:34:37 PM PDT 24
Peak memory 206692 kb
Host smart-9e6deef4-126d-4e1a-8f34-f035f05c4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855485210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1855485210
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2677875125
Short name T953
Test name
Test status
Simulation time 3164734277 ps
CPU time 68.53 seconds
Started Jul 28 05:34:34 PM PDT 24
Finished Jul 28 05:35:43 PM PDT 24
Peak memory 268372 kb
Host smart-79057112-a83f-4f87-9c7f-e1f8c9c94f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677875125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2677875125
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.720815224
Short name T23
Test name
Test status
Simulation time 46617566420 ps
CPU time 115.36 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:36:32 PM PDT 24
Peak memory 249292 kb
Host smart-d7ab9cfa-9ed8-4fd6-ab36-b608f2234fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720815224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.720815224
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.933324105
Short name T399
Test name
Test status
Simulation time 49665259049 ps
CPU time 91.54 seconds
Started Jul 28 05:34:38 PM PDT 24
Finished Jul 28 05:36:09 PM PDT 24
Peak memory 249356 kb
Host smart-b01bfa30-1b9a-49ad-80ed-3dddf27c11fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933324105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.933324105
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2196668708
Short name T467
Test name
Test status
Simulation time 149340865 ps
CPU time 6.19 seconds
Started Jul 28 05:34:37 PM PDT 24
Finished Jul 28 05:34:43 PM PDT 24
Peak memory 249272 kb
Host smart-27ad6bda-a3e5-4815-ba8c-2f432c1af1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196668708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2196668708
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3826348448
Short name T937
Test name
Test status
Simulation time 27034359 ps
CPU time 0.74 seconds
Started Jul 28 05:34:35 PM PDT 24
Finished Jul 28 05:34:35 PM PDT 24
Peak memory 215824 kb
Host smart-09a85156-9273-406d-b843-ded430d44c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826348448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3826348448
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1515781871
Short name T354
Test name
Test status
Simulation time 106980202 ps
CPU time 2.35 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:34:38 PM PDT 24
Peak memory 224216 kb
Host smart-6fb68d19-6b10-4724-a519-09cd6211e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515781871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1515781871
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2326097054
Short name T12
Test name
Test status
Simulation time 480175522 ps
CPU time 4.38 seconds
Started Jul 28 05:34:35 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 224684 kb
Host smart-53baf689-f506-479a-96ff-548e61e7762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326097054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2326097054
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3158110451
Short name T254
Test name
Test status
Simulation time 19371655527 ps
CPU time 16.18 seconds
Started Jul 28 05:34:35 PM PDT 24
Finished Jul 28 05:34:51 PM PDT 24
Peak memory 240980 kb
Host smart-fc417542-64a1-4526-b225-9c8c1c78769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158110451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3158110451
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3434250757
Short name T516
Test name
Test status
Simulation time 30825722 ps
CPU time 2.51 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:34:39 PM PDT 24
Peak memory 232500 kb
Host smart-e3edd40f-c5c7-4480-b26e-7de12146a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434250757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3434250757
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1858835177
Short name T964
Test name
Test status
Simulation time 1605306611 ps
CPU time 6.07 seconds
Started Jul 28 05:34:34 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 220828 kb
Host smart-a84f984c-df79-49f5-bbb1-671f50637432
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1858835177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1858835177
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4290921248
Short name T307
Test name
Test status
Simulation time 9211886113 ps
CPU time 15.1 seconds
Started Jul 28 05:34:35 PM PDT 24
Finished Jul 28 05:34:50 PM PDT 24
Peak memory 216424 kb
Host smart-93cac626-2a8d-4461-a459-e322ed7df64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290921248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4290921248
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.38373564
Short name T822
Test name
Test status
Simulation time 1099526258 ps
CPU time 4.67 seconds
Started Jul 28 05:34:37 PM PDT 24
Finished Jul 28 05:34:41 PM PDT 24
Peak memory 216236 kb
Host smart-282a9272-fa26-4bcf-8b3c-3cd782d5f628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38373564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.38373564
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.583267062
Short name T635
Test name
Test status
Simulation time 654093057 ps
CPU time 2.74 seconds
Started Jul 28 05:34:35 PM PDT 24
Finished Jul 28 05:34:37 PM PDT 24
Peak memory 216352 kb
Host smart-5dae938e-a9c4-4668-b51e-5c9d436b88b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583267062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.583267062
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2797413086
Short name T860
Test name
Test status
Simulation time 65139065 ps
CPU time 0.82 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:34:37 PM PDT 24
Peak memory 206080 kb
Host smart-1d695d7e-380d-498e-b56c-b7dcf6a3fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797413086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2797413086
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.591806131
Short name T556
Test name
Test status
Simulation time 882876396 ps
CPU time 6.8 seconds
Started Jul 28 05:34:37 PM PDT 24
Finished Jul 28 05:34:44 PM PDT 24
Peak memory 232836 kb
Host smart-aeca494b-49b9-47d5-98a6-590c9458d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591806131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.591806131
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.955389496
Short name T349
Test name
Test status
Simulation time 29094221 ps
CPU time 0.71 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:34:43 PM PDT 24
Peak memory 205520 kb
Host smart-c36f4663-ae12-4ad8-bd26-4ccf54c1194f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955389496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.955389496
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4188149506
Short name T9
Test name
Test status
Simulation time 293726960 ps
CPU time 3.74 seconds
Started Jul 28 05:34:47 PM PDT 24
Finished Jul 28 05:34:50 PM PDT 24
Peak memory 224872 kb
Host smart-10a5b87c-b832-4ad2-9d6d-ac93090b1af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188149506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4188149506
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.883979728
Short name T899
Test name
Test status
Simulation time 52326117 ps
CPU time 0.79 seconds
Started Jul 28 05:34:34 PM PDT 24
Finished Jul 28 05:34:35 PM PDT 24
Peak memory 206712 kb
Host smart-c9a7289b-b886-4ac1-8ee2-4eba68d3dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883979728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.883979728
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1278490334
Short name T608
Test name
Test status
Simulation time 1376443219 ps
CPU time 11.85 seconds
Started Jul 28 05:34:41 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 238228 kb
Host smart-e5b2aaed-76ed-48e3-aab4-d2420569ebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278490334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1278490334
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1472254322
Short name T473
Test name
Test status
Simulation time 8728343566 ps
CPU time 99.89 seconds
Started Jul 28 05:34:48 PM PDT 24
Finished Jul 28 05:36:28 PM PDT 24
Peak memory 254440 kb
Host smart-1bf23ebd-d60e-4092-8c45-959610bcb07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472254322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1472254322
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3453742821
Short name T384
Test name
Test status
Simulation time 933520775 ps
CPU time 2.63 seconds
Started Jul 28 05:34:46 PM PDT 24
Finished Jul 28 05:34:49 PM PDT 24
Peak memory 217576 kb
Host smart-58f9a59d-8d82-45d7-92ed-5df792b9614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453742821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3453742821
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1418766473
Short name T1011
Test name
Test status
Simulation time 104571956 ps
CPU time 5.05 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:34:47 PM PDT 24
Peak memory 224680 kb
Host smart-2b1f85e6-318c-4879-bda9-c88e3dbac98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418766473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1418766473
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2454720610
Short name T855
Test name
Test status
Simulation time 18550282254 ps
CPU time 139.91 seconds
Started Jul 28 05:34:46 PM PDT 24
Finished Jul 28 05:37:06 PM PDT 24
Peak memory 254604 kb
Host smart-1f672948-2263-45c6-bfb3-f54fb76da4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454720610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2454720610
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.457968409
Short name T967
Test name
Test status
Simulation time 873715286 ps
CPU time 6.97 seconds
Started Jul 28 05:34:45 PM PDT 24
Finished Jul 28 05:34:52 PM PDT 24
Peak memory 224656 kb
Host smart-a9d294b2-24f9-4c80-81d6-a29416a3b7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457968409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.457968409
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3176321362
Short name T204
Test name
Test status
Simulation time 14905129440 ps
CPU time 82.03 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:36:05 PM PDT 24
Peak memory 232920 kb
Host smart-368e648f-67a2-4045-a086-020dae31201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176321362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3176321362
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.457430188
Short name T941
Test name
Test status
Simulation time 288288457 ps
CPU time 2.79 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:34:45 PM PDT 24
Peak memory 224704 kb
Host smart-e90690d2-54b6-44db-8d60-ea117a00811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457430188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.457430188
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1061596183
Short name T578
Test name
Test status
Simulation time 45558949957 ps
CPU time 30.31 seconds
Started Jul 28 05:34:46 PM PDT 24
Finished Jul 28 05:35:16 PM PDT 24
Peak memory 234956 kb
Host smart-144be51d-6128-45e6-8bb1-e4c62bb0f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061596183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1061596183
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2686807968
Short name T747
Test name
Test status
Simulation time 167177193 ps
CPU time 4.64 seconds
Started Jul 28 05:34:47 PM PDT 24
Finished Jul 28 05:34:52 PM PDT 24
Peak memory 222760 kb
Host smart-f4eb2436-5944-40f8-952e-0e9570df12e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686807968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2686807968
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3627147735
Short name T33
Test name
Test status
Simulation time 65844361563 ps
CPU time 531.82 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:43:34 PM PDT 24
Peak memory 266704 kb
Host smart-319fc4a2-f3c2-42a4-a24c-37cdd7692561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627147735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3627147735
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4076833293
Short name T568
Test name
Test status
Simulation time 3199165715 ps
CPU time 9.5 seconds
Started Jul 28 05:34:33 PM PDT 24
Finished Jul 28 05:34:42 PM PDT 24
Peak memory 220472 kb
Host smart-243c20f9-e1df-48e1-bd77-40eb55557dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076833293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4076833293
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.889961366
Short name T851
Test name
Test status
Simulation time 1297007787 ps
CPU time 7.01 seconds
Started Jul 28 05:34:36 PM PDT 24
Finished Jul 28 05:34:43 PM PDT 24
Peak memory 216396 kb
Host smart-e07f97a1-74f6-408c-80a8-f2400195715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889961366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.889961366
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3564983310
Short name T997
Test name
Test status
Simulation time 31885288 ps
CPU time 1.27 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:34:43 PM PDT 24
Peak memory 207936 kb
Host smart-e7b90176-c7f9-474f-abb5-a9c27a6968a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564983310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3564983310
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3903875513
Short name T429
Test name
Test status
Simulation time 25372059 ps
CPU time 0.76 seconds
Started Jul 28 05:34:37 PM PDT 24
Finished Jul 28 05:34:38 PM PDT 24
Peak memory 206088 kb
Host smart-b608bcef-f4cc-4f6e-8b97-4269d7daeb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903875513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3903875513
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3957825557
Short name T324
Test name
Test status
Simulation time 161717635 ps
CPU time 2.27 seconds
Started Jul 28 05:34:43 PM PDT 24
Finished Jul 28 05:34:45 PM PDT 24
Peak memory 224296 kb
Host smart-e9ecbfa8-761c-436d-926a-8c92b175553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957825557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3957825557
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.527411004
Short name T502
Test name
Test status
Simulation time 18588652 ps
CPU time 0.76 seconds
Started Jul 28 05:34:50 PM PDT 24
Finished Jul 28 05:34:51 PM PDT 24
Peak memory 205572 kb
Host smart-d8828a7c-4d5c-424e-bf6b-960e6ac3d68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527411004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.527411004
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.762163105
Short name T241
Test name
Test status
Simulation time 136711842 ps
CPU time 3.32 seconds
Started Jul 28 05:34:50 PM PDT 24
Finished Jul 28 05:34:54 PM PDT 24
Peak memory 224648 kb
Host smart-79d70974-82f8-47d6-98e7-ad73a6d7b64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762163105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.762163105
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3119136584
Short name T379
Test name
Test status
Simulation time 178710336 ps
CPU time 0.76 seconds
Started Jul 28 05:34:40 PM PDT 24
Finished Jul 28 05:34:41 PM PDT 24
Peak memory 206736 kb
Host smart-ba0b1500-8d72-4bf0-b364-2c2603d09e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119136584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3119136584
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2333720888
Short name T603
Test name
Test status
Simulation time 33257667854 ps
CPU time 108.86 seconds
Started Jul 28 05:34:48 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 249344 kb
Host smart-fab26bb9-93cd-4380-bc06-63612195ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333720888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2333720888
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3335593791
Short name T336
Test name
Test status
Simulation time 5008319197 ps
CPU time 25.57 seconds
Started Jul 28 05:34:49 PM PDT 24
Finished Jul 28 05:35:14 PM PDT 24
Peak memory 232864 kb
Host smart-40bf7ffe-d37f-4a96-86a8-b4c0a6bc5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335593791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3335593791
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.296973081
Short name T529
Test name
Test status
Simulation time 533019783 ps
CPU time 7.83 seconds
Started Jul 28 05:34:41 PM PDT 24
Finished Jul 28 05:34:49 PM PDT 24
Peak memory 224684 kb
Host smart-b2c82a6c-2ba1-4a55-bd6f-0e1c197848b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296973081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.296973081
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3422151330
Short name T764
Test name
Test status
Simulation time 4247433561 ps
CPU time 11.96 seconds
Started Jul 28 05:34:52 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 233068 kb
Host smart-05ff12ed-4395-447c-850d-8fadc6d6361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422151330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3422151330
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.114054173
Short name T548
Test name
Test status
Simulation time 327444893 ps
CPU time 2.1 seconds
Started Jul 28 05:34:43 PM PDT 24
Finished Jul 28 05:34:45 PM PDT 24
Peak memory 223856 kb
Host smart-969b66dd-c555-4b06-9519-615b75e822bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114054173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.114054173
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4175491388
Short name T609
Test name
Test status
Simulation time 424185970 ps
CPU time 6.6 seconds
Started Jul 28 05:34:47 PM PDT 24
Finished Jul 28 05:34:54 PM PDT 24
Peak memory 232772 kb
Host smart-5a484482-99c4-476a-bd5b-d8ca92c9957b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175491388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4175491388
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.733728908
Short name T131
Test name
Test status
Simulation time 1125743586 ps
CPU time 5.17 seconds
Started Jul 28 05:34:48 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 220808 kb
Host smart-6785eced-dfc1-4d34-8941-9d0768565bcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=733728908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.733728908
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.704839905
Short name T891
Test name
Test status
Simulation time 1486822764 ps
CPU time 14.4 seconds
Started Jul 28 05:34:42 PM PDT 24
Finished Jul 28 05:34:57 PM PDT 24
Peak memory 216372 kb
Host smart-324a4192-d9bd-4c81-a66c-3439d4ee4cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704839905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.704839905
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.379152483
Short name T326
Test name
Test status
Simulation time 2655703673 ps
CPU time 2.28 seconds
Started Jul 28 05:34:40 PM PDT 24
Finished Jul 28 05:34:43 PM PDT 24
Peak memory 208024 kb
Host smart-8f6c98bb-f268-42c6-9de4-7ed6d8184723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379152483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.379152483
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2631382892
Short name T915
Test name
Test status
Simulation time 44433313 ps
CPU time 1.84 seconds
Started Jul 28 05:34:45 PM PDT 24
Finished Jul 28 05:34:47 PM PDT 24
Peak memory 216388 kb
Host smart-32c41ef7-5078-45d5-9200-8d11fb4fdd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631382892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2631382892
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.680665494
Short name T505
Test name
Test status
Simulation time 56381015 ps
CPU time 0.77 seconds
Started Jul 28 05:34:41 PM PDT 24
Finished Jul 28 05:34:42 PM PDT 24
Peak memory 206104 kb
Host smart-2d70a226-b0ca-412d-b00e-673a74063c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680665494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.680665494
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4204631059
Short name T214
Test name
Test status
Simulation time 1915853713 ps
CPU time 3.22 seconds
Started Jul 28 05:34:46 PM PDT 24
Finished Jul 28 05:34:50 PM PDT 24
Peak memory 224664 kb
Host smart-acf44aa0-2691-472a-82ca-59b2d25e6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204631059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4204631059
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3200016815
Short name T799
Test name
Test status
Simulation time 41827587 ps
CPU time 0.73 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:05 PM PDT 24
Peak memory 204980 kb
Host smart-d70c8a5d-ae28-4d2c-b265-f1e3ad30a667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200016815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3200016815
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1560851029
Short name T948
Test name
Test status
Simulation time 2137563442 ps
CPU time 9.84 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:12 PM PDT 24
Peak memory 232820 kb
Host smart-61377c45-eab9-4c0d-ad0a-f8e32cfdbad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560851029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1560851029
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2997828790
Short name T508
Test name
Test status
Simulation time 26376483 ps
CPU time 0.79 seconds
Started Jul 28 05:34:51 PM PDT 24
Finished Jul 28 05:34:52 PM PDT 24
Peak memory 205696 kb
Host smart-4d3cc83b-5243-4a93-a28a-ab2f79830f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997828790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2997828790
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3653034381
Short name T48
Test name
Test status
Simulation time 41324927160 ps
CPU time 170.37 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:37:52 PM PDT 24
Peak memory 257424 kb
Host smart-881e69f7-f93c-4fde-90da-0fcf8f26c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653034381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3653034381
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2225286487
Short name T283
Test name
Test status
Simulation time 37587257012 ps
CPU time 195.54 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:38:18 PM PDT 24
Peak memory 252388 kb
Host smart-ee211070-2d85-419f-9d35-efeaf1961904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225286487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2225286487
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1028698207
Short name T794
Test name
Test status
Simulation time 4203971906 ps
CPU time 15.17 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:17 PM PDT 24
Peak memory 224700 kb
Host smart-941a4c54-63f0-45a2-a41c-51d2696190ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028698207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1028698207
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1024640884
Short name T402
Test name
Test status
Simulation time 790532938 ps
CPU time 7.7 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:10 PM PDT 24
Peak memory 224628 kb
Host smart-a1e2e52a-21cd-4517-b613-a05790ff79ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024640884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1024640884
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3116302529
Short name T566
Test name
Test status
Simulation time 2055366718 ps
CPU time 29.85 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:32 PM PDT 24
Peak memory 240760 kb
Host smart-8ce414df-a1ca-4710-af52-ab684fe119e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116302529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3116302529
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2327808441
Short name T525
Test name
Test status
Simulation time 526127169 ps
CPU time 5.95 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:10 PM PDT 24
Peak memory 228148 kb
Host smart-13bb0c27-8996-4aa0-8128-1ce078fbb8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327808441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2327808441
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2839365712
Short name T259
Test name
Test status
Simulation time 313297106 ps
CPU time 7.82 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:11 PM PDT 24
Peak memory 236424 kb
Host smart-927c2796-f962-4ee2-8f22-8b6e3935769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839365712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2839365712
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.19881758
Short name T512
Test name
Test status
Simulation time 2491311055 ps
CPU time 9.37 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:11 PM PDT 24
Peak memory 232928 kb
Host smart-33a80f6e-20fc-4622-ba39-8befa26fca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19881758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.19881758
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2074737419
Short name T815
Test name
Test status
Simulation time 880148258 ps
CPU time 3.44 seconds
Started Jul 28 05:34:49 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 232864 kb
Host smart-30a0a411-a900-44a2-976d-adc443078c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074737419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2074737419
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2823297174
Short name T646
Test name
Test status
Simulation time 326511861 ps
CPU time 5.59 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 223352 kb
Host smart-1e5a6764-36b8-4b30-851c-9bb56ae725fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2823297174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2823297174
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.830014599
Short name T475
Test name
Test status
Simulation time 18527259694 ps
CPU time 160.78 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:37:45 PM PDT 24
Peak memory 255180 kb
Host smart-e14d90d7-7142-4b7a-88f4-0eae8409f6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830014599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.830014599
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1091965181
Short name T550
Test name
Test status
Simulation time 6829089413 ps
CPU time 21.94 seconds
Started Jul 28 05:34:49 PM PDT 24
Finished Jul 28 05:35:11 PM PDT 24
Peak memory 216428 kb
Host smart-7e3746c1-fb83-45b6-8e31-1261ead9f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091965181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1091965181
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.76405256
Short name T338
Test name
Test status
Simulation time 843246391 ps
CPU time 4.38 seconds
Started Jul 28 05:34:49 PM PDT 24
Finished Jul 28 05:34:53 PM PDT 24
Peak memory 216440 kb
Host smart-31c4ec6f-23c2-4694-8a69-26f7d4f6d61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76405256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.76405256
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1901599685
Short name T767
Test name
Test status
Simulation time 35645315 ps
CPU time 1.16 seconds
Started Jul 28 05:34:48 PM PDT 24
Finished Jul 28 05:34:50 PM PDT 24
Peak memory 207816 kb
Host smart-61d4dc23-ac17-41e5-b339-2a1123cd52ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901599685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1901599685
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2932831332
Short name T833
Test name
Test status
Simulation time 43582627 ps
CPU time 0.91 seconds
Started Jul 28 05:34:51 PM PDT 24
Finished Jul 28 05:34:52 PM PDT 24
Peak memory 206104 kb
Host smart-6f4d1999-8911-4b5a-b58c-fb1b090e5281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932831332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2932831332
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1461053633
Short name T819
Test name
Test status
Simulation time 23704355964 ps
CPU time 8.54 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:13 PM PDT 24
Peak memory 232912 kb
Host smart-fe611a57-2fb8-4da2-a392-2da4e061c4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461053633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1461053633
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3699241989
Short name T611
Test name
Test status
Simulation time 12476509 ps
CPU time 0.73 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:32:24 PM PDT 24
Peak memory 205820 kb
Host smart-f0609ff6-e67f-46bc-a7f0-3fe16fb16cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699241989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
699241989
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1179093301
Short name T24
Test name
Test status
Simulation time 462284155 ps
CPU time 2.76 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:19 PM PDT 24
Peak memory 224560 kb
Host smart-4f4a1d29-3519-4387-a9a7-99d7bc0f7ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179093301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1179093301
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3267397788
Short name T368
Test name
Test status
Simulation time 33746162 ps
CPU time 0.79 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:18 PM PDT 24
Peak memory 206708 kb
Host smart-d1888c55-f10b-40a1-91db-f1a2979f5d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267397788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3267397788
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1938386618
Short name T219
Test name
Test status
Simulation time 80817413586 ps
CPU time 283.96 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:37:07 PM PDT 24
Peak memory 265872 kb
Host smart-909def83-79bb-4b0b-a418-918da4fe1b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938386618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1938386618
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2839241474
Short name T888
Test name
Test status
Simulation time 153651487557 ps
CPU time 452.24 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:39:56 PM PDT 24
Peak memory 265684 kb
Host smart-2c77956d-34c6-4ca8-be62-9b7b7d40202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839241474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2839241474
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.122946563
Short name T780
Test name
Test status
Simulation time 105795611628 ps
CPU time 497.93 seconds
Started Jul 28 05:32:21 PM PDT 24
Finished Jul 28 05:40:39 PM PDT 24
Peak memory 263608 kb
Host smart-58e3b289-a385-4ebe-a03a-30c72bbfcab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122946563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
122946563
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2093555111
Short name T880
Test name
Test status
Simulation time 3209618362 ps
CPU time 14.3 seconds
Started Jul 28 05:32:18 PM PDT 24
Finished Jul 28 05:32:33 PM PDT 24
Peak memory 224736 kb
Host smart-d195efa3-7f3e-4246-8c91-be855a1c2e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093555111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2093555111
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2451881259
Short name T724
Test name
Test status
Simulation time 38082669506 ps
CPU time 69.14 seconds
Started Jul 28 05:32:15 PM PDT 24
Finished Jul 28 05:33:24 PM PDT 24
Peak memory 249308 kb
Host smart-5e6f3eff-1284-4db7-a77b-92b3111a835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451881259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2451881259
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1756458724
Short name T878
Test name
Test status
Simulation time 715975762 ps
CPU time 10.26 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 232784 kb
Host smart-443d2f61-bf1b-43ec-9993-73478f211f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756458724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1756458724
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1598661541
Short name T479
Test name
Test status
Simulation time 292970177 ps
CPU time 5.81 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:23 PM PDT 24
Peak memory 240188 kb
Host smart-248ef312-d36c-4169-b0bc-eddc60ccef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598661541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1598661541
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1236361366
Short name T844
Test name
Test status
Simulation time 3508853985 ps
CPU time 13.14 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:29 PM PDT 24
Peak memory 232908 kb
Host smart-8b499173-c485-4cee-b84e-59ab9159094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236361366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1236361366
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1180777512
Short name T249
Test name
Test status
Simulation time 204016269 ps
CPU time 3.01 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:19 PM PDT 24
Peak memory 232760 kb
Host smart-0e425fb9-4ca3-4691-bce1-1f5ef39970a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180777512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1180777512
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3622161701
Short name T664
Test name
Test status
Simulation time 238910023 ps
CPU time 4.09 seconds
Started Jul 28 05:32:14 PM PDT 24
Finished Jul 28 05:32:19 PM PDT 24
Peak memory 219556 kb
Host smart-092c4626-419d-4d36-9cd3-1aa3e1af78f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622161701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3622161701
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.779463755
Short name T975
Test name
Test status
Simulation time 7871087125 ps
CPU time 29.98 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:54 PM PDT 24
Peak memory 238456 kb
Host smart-4074dea5-8417-49db-aebb-87ab84d5d349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779463755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.779463755
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3121026897
Short name T697
Test name
Test status
Simulation time 18069218604 ps
CPU time 35.68 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:53 PM PDT 24
Peak memory 216424 kb
Host smart-b3331430-04f1-475f-94f7-de8342be1d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121026897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3121026897
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2509572887
Short name T358
Test name
Test status
Simulation time 5887973064 ps
CPU time 4.15 seconds
Started Jul 28 05:32:17 PM PDT 24
Finished Jul 28 05:32:21 PM PDT 24
Peak memory 217312 kb
Host smart-f0a2020b-3bf2-416c-8194-39dcdb4a93ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509572887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2509572887
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4227500650
Short name T950
Test name
Test status
Simulation time 90808122 ps
CPU time 1.39 seconds
Started Jul 28 05:32:18 PM PDT 24
Finished Jul 28 05:32:20 PM PDT 24
Peak memory 216376 kb
Host smart-ae4fb848-0f62-40ee-862f-7c144a06c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227500650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4227500650
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3369374383
Short name T755
Test name
Test status
Simulation time 43455529 ps
CPU time 0.74 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:18 PM PDT 24
Peak memory 206056 kb
Host smart-0a861507-bbc0-4ad8-99c2-45fccd5874cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369374383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3369374383
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3920681435
Short name T151
Test name
Test status
Simulation time 1449626174 ps
CPU time 8.04 seconds
Started Jul 28 05:32:16 PM PDT 24
Finished Jul 28 05:32:25 PM PDT 24
Peak memory 232848 kb
Host smart-d0e17e31-f52e-499a-9254-d4e709a06bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920681435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3920681435
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4237732358
Short name T535
Test name
Test status
Simulation time 70789989 ps
CPU time 0.74 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 205572 kb
Host smart-c1e2bf54-dcd8-4e41-a1ac-1d65bac360eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237732358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4237732358
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1662443973
Short name T492
Test name
Test status
Simulation time 413495440 ps
CPU time 2.3 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:06 PM PDT 24
Peak memory 223848 kb
Host smart-002dbcab-2f1c-4566-9edc-7bc089211765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662443973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1662443973
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4053671945
Short name T5
Test name
Test status
Simulation time 54779681 ps
CPU time 0.77 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 205960 kb
Host smart-c891edc4-0fc7-4406-bd2d-04e6686a999d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053671945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4053671945
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3572464398
Short name T995
Test name
Test status
Simulation time 259031384567 ps
CPU time 437.63 seconds
Started Jul 28 05:35:01 PM PDT 24
Finished Jul 28 05:42:19 PM PDT 24
Peak memory 250816 kb
Host smart-725e113d-fce2-49cd-a126-dc27a8078e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572464398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3572464398
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3324739895
Short name T561
Test name
Test status
Simulation time 73097010965 ps
CPU time 245.14 seconds
Started Jul 28 05:35:05 PM PDT 24
Finished Jul 28 05:39:10 PM PDT 24
Peak memory 267260 kb
Host smart-ed2c1900-4352-4467-9239-99122d6e8172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324739895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3324739895
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3081789186
Short name T361
Test name
Test status
Simulation time 237562601 ps
CPU time 5.49 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 224688 kb
Host smart-ef0c41fc-a7ee-4beb-8f08-f0a9a222d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081789186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3081789186
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.245911437
Short name T225
Test name
Test status
Simulation time 4813368044 ps
CPU time 37.31 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:44 PM PDT 24
Peak memory 236976 kb
Host smart-770c9a89-2f6a-4096-a97a-51aca2aff551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245911437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.245911437
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1061826431
Short name T668
Test name
Test status
Simulation time 242028320 ps
CPU time 5.58 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 224552 kb
Host smart-a814f01d-44ee-40b6-bb7b-67c0a372f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061826431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1061826431
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1471972951
Short name T240
Test name
Test status
Simulation time 14400821524 ps
CPU time 32.18 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:36 PM PDT 24
Peak memory 237864 kb
Host smart-7c6f0313-5f43-4148-999a-f1f6eea1257b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471972951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1471972951
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3789172928
Short name T834
Test name
Test status
Simulation time 621333102 ps
CPU time 5.7 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:08 PM PDT 24
Peak memory 224600 kb
Host smart-3e84d03e-a218-415c-b679-22aae97ed7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789172928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3789172928
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2183647572
Short name T231
Test name
Test status
Simulation time 5570469428 ps
CPU time 20.6 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:25 PM PDT 24
Peak memory 234412 kb
Host smart-50481110-d062-41f4-a301-f50c70027f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183647572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2183647572
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.17668719
Short name T753
Test name
Test status
Simulation time 10104221805 ps
CPU time 8.91 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:15 PM PDT 24
Peak memory 218852 kb
Host smart-58441c96-655e-4b91-a831-0c568a7392db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=17668719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direc
t.17668719
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1384773076
Short name T32
Test name
Test status
Simulation time 98683003 ps
CPU time 1.22 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 207040 kb
Host smart-42d2933b-3b94-4687-a431-aca8a2ca81ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384773076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1384773076
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4134994609
Short name T718
Test name
Test status
Simulation time 5515602921 ps
CPU time 29.27 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:33 PM PDT 24
Peak memory 216460 kb
Host smart-eb892559-b84b-419a-af15-ffe6adb1bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134994609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4134994609
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2175174680
Short name T966
Test name
Test status
Simulation time 16333966 ps
CPU time 0.71 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:05 PM PDT 24
Peak memory 205792 kb
Host smart-40867272-d3b2-490b-ba7f-82b950d0aeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175174680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2175174680
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1757229986
Short name T698
Test name
Test status
Simulation time 117312715 ps
CPU time 3.95 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:10 PM PDT 24
Peak memory 216372 kb
Host smart-90a28cbe-cc01-469c-ab66-57d6cfd1aa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757229986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1757229986
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.668503879
Short name T541
Test name
Test status
Simulation time 103944235 ps
CPU time 0.89 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:03 PM PDT 24
Peak memory 206096 kb
Host smart-dd0b6328-eafe-4555-8ab2-ac5931a0e3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668503879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.668503879
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2054880352
Short name T339
Test name
Test status
Simulation time 233615469 ps
CPU time 2.39 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 224280 kb
Host smart-3090360c-8fa8-4da5-95a8-cc3fd6b15c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054880352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2054880352
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3737716393
Short name T863
Test name
Test status
Simulation time 31572612 ps
CPU time 0.72 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 205504 kb
Host smart-b2a9dcb2-b6c0-43c9-a0ef-98ca6a11117e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737716393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3737716393
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.894891851
Short name T624
Test name
Test status
Simulation time 2534548274 ps
CPU time 6.27 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:14 PM PDT 24
Peak memory 224652 kb
Host smart-606e8331-a81b-4711-8280-a081ce1b0129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894891851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.894891851
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.731776267
Short name T439
Test name
Test status
Simulation time 24945228 ps
CPU time 0.8 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:03 PM PDT 24
Peak memory 206688 kb
Host smart-69f2ab7e-a8c5-441b-9571-d00538ff43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731776267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.731776267
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1837546376
Short name T257
Test name
Test status
Simulation time 55133385102 ps
CPU time 102.45 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:36:50 PM PDT 24
Peak memory 251708 kb
Host smart-aabe6531-c5a8-4ee9-a2bd-237a1ef7e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837546376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1837546376
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.232440089
Short name T442
Test name
Test status
Simulation time 1533464951 ps
CPU time 27.09 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:35:35 PM PDT 24
Peak memory 249296 kb
Host smart-c0c2d5d0-3d6b-4adc-a4d5-cc96516bd24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232440089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.232440089
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4039378328
Short name T685
Test name
Test status
Simulation time 3587731459 ps
CPU time 53.11 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:36:00 PM PDT 24
Peak memory 251956 kb
Host smart-36c1e9c9-82c7-4e47-b593-30d10846c9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039378328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4039378328
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3860975894
Short name T295
Test name
Test status
Simulation time 18174539363 ps
CPU time 62.22 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:36:08 PM PDT 24
Peak memory 240512 kb
Host smart-36be16d1-95d4-473f-a4c8-e6f0470b7e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860975894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3860975894
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2478439962
Short name T605
Test name
Test status
Simulation time 38536622 ps
CPU time 0.79 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 215904 kb
Host smart-c2294926-40ee-45ac-b63f-d78126ab98be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478439962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2478439962
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1116540678
Short name T750
Test name
Test status
Simulation time 857836764 ps
CPU time 2.7 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 224636 kb
Host smart-66746221-3d4b-4c94-beca-2e0d60947c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116540678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1116540678
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3916243533
Short name T587
Test name
Test status
Simulation time 2716497384 ps
CPU time 10.61 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:16 PM PDT 24
Peak memory 236484 kb
Host smart-9788a918-b3dd-4743-b13a-ce35952dde47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916243533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3916243533
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.414050014
Short name T488
Test name
Test status
Simulation time 180936263 ps
CPU time 4.4 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:11 PM PDT 24
Peak memory 224676 kb
Host smart-9b82781c-3743-45d1-8282-38c1c38897ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414050014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.414050014
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.65917903
Short name T462
Test name
Test status
Simulation time 445069044 ps
CPU time 7 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:14 PM PDT 24
Peak memory 240700 kb
Host smart-bbeb110f-18fd-4a39-9155-2ee78f9a6da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65917903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.65917903
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3835597937
Short name T440
Test name
Test status
Simulation time 1372427184 ps
CPU time 17.6 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:20 PM PDT 24
Peak memory 219008 kb
Host smart-a383bcc2-dd8f-49b2-bcc0-2bdfa8e91fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3835597937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3835597937
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.72999316
Short name T122
Test name
Test status
Simulation time 66744773846 ps
CPU time 320.38 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:40:28 PM PDT 24
Peak memory 285336 kb
Host smart-b0221b86-35f5-4bdf-91db-60c3e425298a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72999316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress
_all.72999316
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2662783557
Short name T31
Test name
Test status
Simulation time 9387195503 ps
CPU time 40.18 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:43 PM PDT 24
Peak memory 216532 kb
Host smart-3fa2a606-eb97-454a-a72f-86f3ea51dba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662783557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2662783557
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.614142272
Short name T378
Test name
Test status
Simulation time 650943761 ps
CPU time 1.63 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:05 PM PDT 24
Peak memory 207968 kb
Host smart-fc2e823c-fa52-432e-81d7-a14f18964165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614142272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.614142272
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4220285688
Short name T380
Test name
Test status
Simulation time 83783648 ps
CPU time 2.01 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:05 PM PDT 24
Peak memory 216452 kb
Host smart-d617ee09-7738-49b4-a59f-703273ed8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220285688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4220285688
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.282059505
Short name T821
Test name
Test status
Simulation time 22557738 ps
CPU time 0.82 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 206072 kb
Host smart-5c38cea1-2c6e-4df0-a8d5-43d35030f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282059505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.282059505
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1620487319
Short name T186
Test name
Test status
Simulation time 4389348458 ps
CPU time 16.34 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 232940 kb
Host smart-fce5b671-524d-40e5-b774-d288573fc713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620487319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1620487319
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1990820157
Short name T582
Test name
Test status
Simulation time 42435651 ps
CPU time 0.75 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:10 PM PDT 24
Peak memory 204924 kb
Host smart-5105aeac-e012-4456-acc1-0d28c1fc1a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990820157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1990820157
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1961910229
Short name T168
Test name
Test status
Simulation time 33657859 ps
CPU time 2.7 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 233016 kb
Host smart-5b84304f-58dc-4865-b296-9da3ec3f2ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961910229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1961910229
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3352140108
Short name T940
Test name
Test status
Simulation time 60606315 ps
CPU time 0.82 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:04 PM PDT 24
Peak memory 206688 kb
Host smart-17d269cc-02b4-48b2-b5e5-da1a1668d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352140108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3352140108
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3654618309
Short name T659
Test name
Test status
Simulation time 16276277299 ps
CPU time 127.8 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:37:16 PM PDT 24
Peak memory 249332 kb
Host smart-f73bf0f8-bd89-406f-9886-1aa4ade2c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654618309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3654618309
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3559877036
Short name T293
Test name
Test status
Simulation time 7806410505 ps
CPU time 116.77 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:37:05 PM PDT 24
Peak memory 265536 kb
Host smart-27d615b0-6933-4177-92dd-d7aca6034449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559877036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3559877036
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2975094634
Short name T672
Test name
Test status
Simulation time 12549588822 ps
CPU time 130.39 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 235492 kb
Host smart-a956c0b7-886d-4d1d-af42-90a6329e90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975094634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2975094634
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2832842757
Short name T602
Test name
Test status
Simulation time 5274835095 ps
CPU time 26.94 seconds
Started Jul 28 05:35:05 PM PDT 24
Finished Jul 28 05:35:32 PM PDT 24
Peak memory 249348 kb
Host smart-2ec992e2-318b-45e1-bafa-0881113907c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832842757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2832842757
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1099680601
Short name T195
Test name
Test status
Simulation time 4114884625 ps
CPU time 28.2 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:31 PM PDT 24
Peak memory 241008 kb
Host smart-947097a0-96ef-4dbd-9416-80c53a6e2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099680601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1099680601
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.394695132
Short name T266
Test name
Test status
Simulation time 6719657219 ps
CPU time 14.17 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 224656 kb
Host smart-88224fef-dc6c-479b-bb65-4ae76f7aec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394695132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.394695132
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3260885373
Short name T74
Test name
Test status
Simulation time 437613005 ps
CPU time 2.89 seconds
Started Jul 28 05:35:04 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 232828 kb
Host smart-a7739cb8-f8e7-42f1-8266-aae17f98bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260885373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3260885373
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.152228080
Short name T686
Test name
Test status
Simulation time 642287704 ps
CPU time 3.96 seconds
Started Jul 28 05:35:05 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 224664 kb
Host smart-b1472148-25df-45fc-b14d-de5e612088f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152228080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.152228080
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3337623170
Short name T562
Test name
Test status
Simulation time 177914075 ps
CPU time 2.85 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 228152 kb
Host smart-69480e73-c1e5-417c-8d74-7805a7a7b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337623170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3337623170
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3900887289
Short name T495
Test name
Test status
Simulation time 1798747673 ps
CPU time 8.97 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:12 PM PDT 24
Peak memory 220292 kb
Host smart-bafd381b-e21a-4ad8-88dd-22191a2dabd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3900887289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3900887289
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2916781574
Short name T20
Test name
Test status
Simulation time 26537430652 ps
CPU time 279.45 seconds
Started Jul 28 05:35:12 PM PDT 24
Finished Jul 28 05:39:51 PM PDT 24
Peak memory 265768 kb
Host smart-bbd13c5e-2f32-4174-9fd4-8eed8987aaa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916781574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2916781574
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2745111803
Short name T420
Test name
Test status
Simulation time 30798400521 ps
CPU time 49.12 seconds
Started Jul 28 05:35:02 PM PDT 24
Finished Jul 28 05:35:51 PM PDT 24
Peak memory 216444 kb
Host smart-5d41ace4-0e8b-4522-a59a-ca82400c252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745111803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2745111803
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1633085248
Short name T798
Test name
Test status
Simulation time 4328796319 ps
CPU time 12.69 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:22 PM PDT 24
Peak memory 216340 kb
Host smart-f0b47531-3688-4fbf-87e5-2942f77538c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633085248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1633085248
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2540489106
Short name T939
Test name
Test status
Simulation time 447894572 ps
CPU time 4.52 seconds
Started Jul 28 05:35:03 PM PDT 24
Finished Jul 28 05:35:08 PM PDT 24
Peak memory 216352 kb
Host smart-0eb797e2-f182-4767-8d5d-818f1f028828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540489106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2540489106
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1228005244
Short name T790
Test name
Test status
Simulation time 188687430 ps
CPU time 0.84 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 206016 kb
Host smart-950639fa-4d80-4d26-99ce-6a9714577c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228005244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1228005244
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3682600098
Short name T810
Test name
Test status
Simulation time 974937338 ps
CPU time 6.82 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:13 PM PDT 24
Peak memory 232824 kb
Host smart-4e00f31c-7392-4fe5-a279-301a8efe206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682600098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3682600098
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1091960356
Short name T432
Test name
Test status
Simulation time 33450165 ps
CPU time 0.74 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:07 PM PDT 24
Peak memory 204972 kb
Host smart-39aeb65e-d62e-4af4-a72e-dc6dd0dfcf5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091960356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1091960356
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4149218762
Short name T414
Test name
Test status
Simulation time 2201212194 ps
CPU time 5.59 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:13 PM PDT 24
Peak memory 232896 kb
Host smart-8d9df485-be21-4fb4-abc4-f80027cc114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149218762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4149218762
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.812003317
Short name T509
Test name
Test status
Simulation time 24526362 ps
CPU time 0.8 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:08 PM PDT 24
Peak memory 206608 kb
Host smart-5b6deed3-9101-4fa2-a3b6-79b595efd4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812003317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.812003317
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3747771755
Short name T175
Test name
Test status
Simulation time 11876069923 ps
CPU time 73.12 seconds
Started Jul 28 05:35:13 PM PDT 24
Finished Jul 28 05:36:27 PM PDT 24
Peak memory 251416 kb
Host smart-3bc7430a-0622-4e93-8ac2-5a586c21c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747771755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3747771755
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2794879348
Short name T763
Test name
Test status
Simulation time 4793270848 ps
CPU time 25.97 seconds
Started Jul 28 05:35:10 PM PDT 24
Finished Jul 28 05:35:36 PM PDT 24
Peak memory 231520 kb
Host smart-80d593c3-c51c-4c54-96a2-ef24777d8111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794879348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2794879348
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2418307691
Short name T292
Test name
Test status
Simulation time 114144347663 ps
CPU time 161.27 seconds
Started Jul 28 05:35:13 PM PDT 24
Finished Jul 28 05:37:54 PM PDT 24
Peak memory 267264 kb
Host smart-4d644e90-07dd-406d-914e-f9cf6b9a459f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418307691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2418307691
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3290352852
Short name T365
Test name
Test status
Simulation time 3688496659 ps
CPU time 16.84 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:26 PM PDT 24
Peak memory 232952 kb
Host smart-225d8b1b-9867-4cc8-9bf8-bad1aebdf59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290352852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3290352852
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2588546877
Short name T943
Test name
Test status
Simulation time 141304993179 ps
CPU time 256.31 seconds
Started Jul 28 05:35:13 PM PDT 24
Finished Jul 28 05:39:29 PM PDT 24
Peak memory 261300 kb
Host smart-d95e3f8e-e1c3-4dab-9d7d-92b2ed2b715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588546877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2588546877
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2948373852
Short name T536
Test name
Test status
Simulation time 373812413 ps
CPU time 7.2 seconds
Started Jul 28 05:35:10 PM PDT 24
Finished Jul 28 05:35:17 PM PDT 24
Peak memory 233052 kb
Host smart-253a5a57-ac4c-4f43-83f5-83f0a7ea2bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948373852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2948373852
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1811270707
Short name T441
Test name
Test status
Simulation time 42301502761 ps
CPU time 49.77 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:57 PM PDT 24
Peak memory 232904 kb
Host smart-8c46c4bc-2346-4b0a-9fe2-65326ae0dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811270707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1811270707
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.817544732
Short name T980
Test name
Test status
Simulation time 6797544536 ps
CPU time 10.84 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 224696 kb
Host smart-b891f3d6-45db-4e8e-aea7-5c152c36a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817544732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.817544732
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.755056262
Short name T746
Test name
Test status
Simulation time 27174023256 ps
CPU time 18.71 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:28 PM PDT 24
Peak memory 235204 kb
Host smart-e2a5f67a-9ff3-4aa3-aa9a-9cfda5fe6507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755056262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.755056262
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.188648436
Short name T128
Test name
Test status
Simulation time 2811576471 ps
CPU time 6.76 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:35:15 PM PDT 24
Peak memory 218964 kb
Host smart-46ee64ba-c73f-49f1-9294-525326dba629
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=188648436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.188648436
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2801957599
Short name T316
Test name
Test status
Simulation time 118707419184 ps
CPU time 240.44 seconds
Started Jul 28 05:35:13 PM PDT 24
Finished Jul 28 05:39:14 PM PDT 24
Peak memory 256032 kb
Host smart-e35693c1-9787-4c52-93e1-c9dc2c0f999a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801957599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2801957599
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2898448675
Short name T308
Test name
Test status
Simulation time 1335612356 ps
CPU time 13.74 seconds
Started Jul 28 05:35:06 PM PDT 24
Finished Jul 28 05:35:19 PM PDT 24
Peak memory 219428 kb
Host smart-9f09d6a7-e27e-4283-8103-f0ae6eba95d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898448675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2898448675
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.706317095
Short name T678
Test name
Test status
Simulation time 2081073323 ps
CPU time 6.2 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:15 PM PDT 24
Peak memory 216328 kb
Host smart-cbe2c3da-75f6-452d-8dd9-1ac596b2889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706317095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.706317095
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2650932506
Short name T330
Test name
Test status
Simulation time 214426816 ps
CPU time 2.57 seconds
Started Jul 28 05:35:09 PM PDT 24
Finished Jul 28 05:35:12 PM PDT 24
Peak memory 216332 kb
Host smart-5265d485-543d-4e8a-9f5f-dd98b3175c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650932506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2650932506
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4248562196
Short name T340
Test name
Test status
Simulation time 52082693 ps
CPU time 0.74 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:08 PM PDT 24
Peak memory 206092 kb
Host smart-241d9bf4-92bf-46d6-b16f-e922c77ee11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248562196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4248562196
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1136367875
Short name T676
Test name
Test status
Simulation time 39373795 ps
CPU time 2.29 seconds
Started Jul 28 05:35:07 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 224076 kb
Host smart-5d72243e-c69c-4954-bdf6-ff2da6b77593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136367875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1136367875
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2479839725
Short name T570
Test name
Test status
Simulation time 57072797 ps
CPU time 0.71 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 204976 kb
Host smart-c7456269-9032-4938-9be7-580fc5fe4589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479839725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2479839725
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3716751699
Short name T804
Test name
Test status
Simulation time 2159042383 ps
CPU time 14.24 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:30 PM PDT 24
Peak memory 224700 kb
Host smart-a983f476-06e3-47d0-a34c-7126fbef789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716751699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3716751699
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1385539977
Short name T423
Test name
Test status
Simulation time 37805058 ps
CPU time 0.79 seconds
Started Jul 28 05:35:08 PM PDT 24
Finished Jul 28 05:35:09 PM PDT 24
Peak memory 206748 kb
Host smart-16ed5037-3fd0-497c-ac0f-cc3f533c29b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385539977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1385539977
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3409996865
Short name T710
Test name
Test status
Simulation time 10044154160 ps
CPU time 39.79 seconds
Started Jul 28 05:35:20 PM PDT 24
Finished Jul 28 05:36:00 PM PDT 24
Peak memory 252292 kb
Host smart-0bf9efd2-e9dc-4089-89ab-7ac5dab73316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409996865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3409996865
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1560651333
Short name T1004
Test name
Test status
Simulation time 2019434711 ps
CPU time 48.01 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:36:04 PM PDT 24
Peak memory 251544 kb
Host smart-67896bc8-5458-43a4-8a88-6d0121539c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560651333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1560651333
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3273700319
Short name T925
Test name
Test status
Simulation time 417842925 ps
CPU time 5.35 seconds
Started Jul 28 05:35:15 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 232944 kb
Host smart-17dad5c0-ca40-4632-9733-6c6cd154d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273700319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3273700319
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.409317990
Short name T177
Test name
Test status
Simulation time 9759971130 ps
CPU time 133.7 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:37:31 PM PDT 24
Peak memory 265656 kb
Host smart-3b6af24d-195c-4fa8-b2dd-d430ae775be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409317990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.409317990
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.400844801
Short name T791
Test name
Test status
Simulation time 972395848 ps
CPU time 8.29 seconds
Started Jul 28 05:35:15 PM PDT 24
Finished Jul 28 05:35:24 PM PDT 24
Peak memory 232876 kb
Host smart-c3ba732a-e89c-4ef6-937d-0d7c3e535f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400844801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.400844801
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1667031034
Short name T693
Test name
Test status
Simulation time 9458496779 ps
CPU time 18.94 seconds
Started Jul 28 05:35:15 PM PDT 24
Finished Jul 28 05:35:34 PM PDT 24
Peak memory 232896 kb
Host smart-b9f99d84-ffeb-4197-8f61-2f08d2cd8734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667031034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1667031034
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3722665205
Short name T539
Test name
Test status
Simulation time 26155840326 ps
CPU time 12.91 seconds
Started Jul 28 05:35:18 PM PDT 24
Finished Jul 28 05:35:31 PM PDT 24
Peak memory 224632 kb
Host smart-3e1cff4a-08a7-40cb-a7d6-e64f8a737ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722665205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3722665205
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.255921286
Short name T935
Test name
Test status
Simulation time 13366027828 ps
CPU time 12.98 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:29 PM PDT 24
Peak memory 224680 kb
Host smart-55c24cba-e9f0-4032-af18-b4d17b1ead9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255921286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.255921286
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.938748081
Short name T954
Test name
Test status
Simulation time 3465746142 ps
CPU time 5.8 seconds
Started Jul 28 05:35:14 PM PDT 24
Finished Jul 28 05:35:20 PM PDT 24
Peak memory 219572 kb
Host smart-5b8ac88a-3ffd-4cda-a71c-b2efc6a3ec2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=938748081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.938748081
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1588519505
Short name T938
Test name
Test status
Simulation time 13789169401 ps
CPU time 160.71 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:37:57 PM PDT 24
Peak memory 250636 kb
Host smart-4481968c-7f31-4642-a6e8-ec8cb7afb719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588519505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1588519505
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.613712797
Short name T538
Test name
Test status
Simulation time 5054234482 ps
CPU time 29.75 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:46 PM PDT 24
Peak memory 216472 kb
Host smart-ebff0b22-51ee-4f9c-9929-94f457e2cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613712797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.613712797
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2050823525
Short name T434
Test name
Test status
Simulation time 2195342238 ps
CPU time 4.52 seconds
Started Jul 28 05:35:15 PM PDT 24
Finished Jul 28 05:35:19 PM PDT 24
Peak memory 216476 kb
Host smart-666cd0b4-cda0-412f-b975-d61b4c5d2f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050823525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2050823525
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2255235256
Short name T408
Test name
Test status
Simulation time 18296130 ps
CPU time 0.74 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 205740 kb
Host smart-ed6d835e-8202-439a-8fa1-d55bf178acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255235256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2255235256
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1811760974
Short name T906
Test name
Test status
Simulation time 24587545 ps
CPU time 0.81 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 206116 kb
Host smart-45fd1b4a-a065-48f1-9a23-bd9ae5f26806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811760974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1811760974
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3541695532
Short name T647
Test name
Test status
Simulation time 2172249310 ps
CPU time 9.17 seconds
Started Jul 28 05:35:15 PM PDT 24
Finished Jul 28 05:35:24 PM PDT 24
Peak memory 232936 kb
Host smart-520e259c-ed70-49d5-a7f0-ebbe6ca3c208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541695532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3541695532
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3425934484
Short name T631
Test name
Test status
Simulation time 13796784 ps
CPU time 0.7 seconds
Started Jul 28 05:35:20 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 205936 kb
Host smart-5f24a4ca-ba52-4cf4-997d-5ad75e0d12c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425934484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3425934484
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3724795281
Short name T170
Test name
Test status
Simulation time 294111892 ps
CPU time 2.37 seconds
Started Jul 28 05:35:14 PM PDT 24
Finished Jul 28 05:35:16 PM PDT 24
Peak memory 224600 kb
Host smart-3bcaaaff-a89c-4add-aa34-5873ab483b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724795281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3724795281
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3925908927
Short name T55
Test name
Test status
Simulation time 157526465 ps
CPU time 0.78 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:35:20 PM PDT 24
Peak memory 206684 kb
Host smart-8c171cf4-f2f7-4b6f-ba06-d642f7fb77bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925908927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3925908927
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1166555384
Short name T717
Test name
Test status
Simulation time 656072196 ps
CPU time 4.25 seconds
Started Jul 28 05:35:21 PM PDT 24
Finished Jul 28 05:35:26 PM PDT 24
Peak memory 233956 kb
Host smart-587ead30-65e2-4c21-9a52-252dbae1e01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166555384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1166555384
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1086164186
Short name T924
Test name
Test status
Simulation time 3976253313 ps
CPU time 95.05 seconds
Started Jul 28 05:35:22 PM PDT 24
Finished Jul 28 05:36:58 PM PDT 24
Peak memory 255136 kb
Host smart-baea6b46-8a60-4a6f-9dd9-d34f6d24bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086164186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1086164186
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3841918115
Short name T30
Test name
Test status
Simulation time 152359488930 ps
CPU time 282.63 seconds
Started Jul 28 05:35:20 PM PDT 24
Finished Jul 28 05:40:03 PM PDT 24
Peak memory 253204 kb
Host smart-7674db2c-88c0-4960-ba13-7f674718d5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841918115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3841918115
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.747793228
Short name T911
Test name
Test status
Simulation time 125743290 ps
CPU time 5.2 seconds
Started Jul 28 05:35:15 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 224660 kb
Host smart-edf25e12-d7f5-49a9-8ec2-769cdddb25f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747793228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.747793228
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.265445201
Short name T542
Test name
Test status
Simulation time 66515023575 ps
CPU time 230.52 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:39:06 PM PDT 24
Peak memory 261432 kb
Host smart-9fd79f68-3c8b-45a3-9e4f-7814e8d18036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265445201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.265445201
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3406142666
Short name T386
Test name
Test status
Simulation time 388316889 ps
CPU time 5.96 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:35:25 PM PDT 24
Peak memory 224688 kb
Host smart-91168b3b-d089-4cda-bc9c-4ead36d27c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406142666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3406142666
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2503677258
Short name T367
Test name
Test status
Simulation time 224851518 ps
CPU time 6.85 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:23 PM PDT 24
Peak memory 232824 kb
Host smart-5d8f2c03-c270-4977-9aee-ebe45cda8019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503677258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2503677258
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.841439077
Short name T206
Test name
Test status
Simulation time 37421982667 ps
CPU time 30.27 seconds
Started Jul 28 05:35:18 PM PDT 24
Finished Jul 28 05:35:48 PM PDT 24
Peak memory 232812 kb
Host smart-145b7e0f-90df-4c5d-8211-750778fdb74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841439077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.841439077
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3160944737
Short name T2
Test name
Test status
Simulation time 570484827 ps
CPU time 2.67 seconds
Started Jul 28 05:35:14 PM PDT 24
Finished Jul 28 05:35:17 PM PDT 24
Peak memory 232856 kb
Host smart-5e990bee-5720-4554-99fc-3c8f13ec0801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160944737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3160944737
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1783942275
Short name T977
Test name
Test status
Simulation time 1330372561 ps
CPU time 11.46 seconds
Started Jul 28 05:35:26 PM PDT 24
Finished Jul 28 05:35:37 PM PDT 24
Peak memory 219036 kb
Host smart-f30d5985-a075-49c4-a0e7-31fdaf9ff6a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1783942275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1783942275
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3181378448
Short name T932
Test name
Test status
Simulation time 12341294 ps
CPU time 0.7 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 205808 kb
Host smart-b9f026b9-60f2-4a0d-8d22-07bbedeeb82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181378448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3181378448
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2617258823
Short name T696
Test name
Test status
Simulation time 14853143588 ps
CPU time 5.58 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:21 PM PDT 24
Peak memory 216456 kb
Host smart-ba45405d-0705-4a26-b2e6-80b4ac28e6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617258823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2617258823
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3560620827
Short name T53
Test name
Test status
Simulation time 260331793 ps
CPU time 2.89 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:19 PM PDT 24
Peak memory 216336 kb
Host smart-0cd525cb-c810-4a76-95e1-4a0cfbc2c949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560620827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3560620827
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.504739955
Short name T27
Test name
Test status
Simulation time 269225938 ps
CPU time 0.8 seconds
Started Jul 28 05:35:17 PM PDT 24
Finished Jul 28 05:35:18 PM PDT 24
Peak memory 206048 kb
Host smart-ac8c534b-3b6b-45ca-8750-cbd11474099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504739955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.504739955
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.455620174
Short name T113
Test name
Test status
Simulation time 493482230 ps
CPU time 6.89 seconds
Started Jul 28 05:35:16 PM PDT 24
Finished Jul 28 05:35:23 PM PDT 24
Peak memory 224652 kb
Host smart-231569d2-e5f3-44b1-a8ac-77beec46af9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455620174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.455620174
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.898541988
Short name T893
Test name
Test status
Simulation time 16172728 ps
CPU time 0.75 seconds
Started Jul 28 05:35:26 PM PDT 24
Finished Jul 28 05:35:26 PM PDT 24
Peak memory 204992 kb
Host smart-4f3032cb-ecac-4b35-aa3b-7293bc56de8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898541988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.898541988
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1716556687
Short name T169
Test name
Test status
Simulation time 185016501 ps
CPU time 3.05 seconds
Started Jul 28 05:35:24 PM PDT 24
Finished Jul 28 05:35:27 PM PDT 24
Peak memory 232932 kb
Host smart-d0182a7c-c71a-40d8-9847-91964802740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716556687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1716556687
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2740280543
Short name T433
Test name
Test status
Simulation time 56020287 ps
CPU time 0.79 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:35:20 PM PDT 24
Peak memory 207004 kb
Host smart-01acf098-12dc-4c75-a0fe-11bb5b9e403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740280543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2740280543
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2240890417
Short name T277
Test name
Test status
Simulation time 1991053521 ps
CPU time 36.38 seconds
Started Jul 28 05:35:25 PM PDT 24
Finished Jul 28 05:36:02 PM PDT 24
Peak memory 257372 kb
Host smart-245e6d71-6251-4996-8b9f-ee8e0ca05cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240890417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2240890417
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2195328752
Short name T28
Test name
Test status
Simulation time 17348665398 ps
CPU time 48.42 seconds
Started Jul 28 05:35:25 PM PDT 24
Finished Jul 28 05:36:14 PM PDT 24
Peak memory 232964 kb
Host smart-2424b888-314f-4060-9087-ebed310546c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195328752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2195328752
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1454950719
Short name T679
Test name
Test status
Simulation time 21651605004 ps
CPU time 117.04 seconds
Started Jul 28 05:35:22 PM PDT 24
Finished Jul 28 05:37:19 PM PDT 24
Peak memory 241508 kb
Host smart-5130f593-07cb-460b-872a-4e0dd968c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454950719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1454950719
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2346221169
Short name T581
Test name
Test status
Simulation time 1571472930 ps
CPU time 27.06 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:35:47 PM PDT 24
Peak memory 249272 kb
Host smart-c2af9749-acfc-4fa1-bd63-6593b963a251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346221169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2346221169
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2203202112
Short name T695
Test name
Test status
Simulation time 26320535627 ps
CPU time 186.98 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:38:26 PM PDT 24
Peak memory 249272 kb
Host smart-f555e4d2-ec6d-4789-8f7d-01b6fc2936de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203202112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2203202112
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3280238096
Short name T803
Test name
Test status
Simulation time 1969289379 ps
CPU time 5.9 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:35:25 PM PDT 24
Peak memory 232808 kb
Host smart-a3add52f-384d-4d99-a9ed-1177da60e1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280238096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3280238096
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2766561065
Short name T111
Test name
Test status
Simulation time 288345012 ps
CPU time 5.03 seconds
Started Jul 28 05:35:25 PM PDT 24
Finished Jul 28 05:35:30 PM PDT 24
Peak memory 240788 kb
Host smart-80a66eb3-07f7-4f25-99a9-931313a3e8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766561065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2766561065
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.221572495
Short name T1002
Test name
Test status
Simulation time 379523458 ps
CPU time 3.38 seconds
Started Jul 28 05:35:22 PM PDT 24
Finished Jul 28 05:35:26 PM PDT 24
Peak memory 232800 kb
Host smart-0e7696f9-89c0-4f12-bf79-4429ce15bb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221572495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.221572495
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1943492443
Short name T765
Test name
Test status
Simulation time 64931608 ps
CPU time 2.06 seconds
Started Jul 28 05:35:22 PM PDT 24
Finished Jul 28 05:35:24 PM PDT 24
Peak memory 224532 kb
Host smart-6e031f1d-edad-4483-b792-994525a2b3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943492443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1943492443
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1386058901
Short name T591
Test name
Test status
Simulation time 116814864 ps
CPU time 4.57 seconds
Started Jul 28 05:35:20 PM PDT 24
Finished Jul 28 05:35:25 PM PDT 24
Peak memory 220748 kb
Host smart-905517c5-d70d-4fb8-ae47-0ddc4dfb4eef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1386058901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1386058901
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2055987402
Short name T1008
Test name
Test status
Simulation time 69601117 ps
CPU time 1 seconds
Started Jul 28 05:35:24 PM PDT 24
Finished Jul 28 05:35:25 PM PDT 24
Peak memory 207936 kb
Host smart-169821c2-10da-4f1c-ad9f-d45a94902a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055987402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2055987402
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.288680898
Short name T558
Test name
Test status
Simulation time 4152689885 ps
CPU time 26.2 seconds
Started Jul 28 05:35:18 PM PDT 24
Finished Jul 28 05:35:45 PM PDT 24
Peak memory 216456 kb
Host smart-6ac78728-59da-4e6a-a4f1-6dc923d33eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288680898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.288680898
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.513732228
Short name T332
Test name
Test status
Simulation time 938111190 ps
CPU time 2.98 seconds
Started Jul 28 05:35:20 PM PDT 24
Finished Jul 28 05:35:23 PM PDT 24
Peak memory 216336 kb
Host smart-dda7f0be-9559-4272-a427-c78738290cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513732228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.513732228
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3000703932
Short name T391
Test name
Test status
Simulation time 236775992 ps
CPU time 2.63 seconds
Started Jul 28 05:35:20 PM PDT 24
Finished Jul 28 05:35:23 PM PDT 24
Peak memory 216240 kb
Host smart-f0febf3f-59fa-41bf-9c71-b59dda5beedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000703932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3000703932
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3764332991
Short name T748
Test name
Test status
Simulation time 109176561 ps
CPU time 0.89 seconds
Started Jul 28 05:35:19 PM PDT 24
Finished Jul 28 05:35:20 PM PDT 24
Peak memory 207140 kb
Host smart-9d7fe2bb-7273-43fe-85b7-fbac09e7a2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764332991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3764332991
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.28253051
Short name T595
Test name
Test status
Simulation time 224174265 ps
CPU time 2.55 seconds
Started Jul 28 05:35:24 PM PDT 24
Finished Jul 28 05:35:27 PM PDT 24
Peak memory 232592 kb
Host smart-24bff5a2-9573-44a1-a6c6-7ecd2f58ea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28253051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.28253051
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.446128773
Short name T376
Test name
Test status
Simulation time 30345635 ps
CPU time 0.76 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:30 PM PDT 24
Peak memory 204956 kb
Host smart-87afd61d-5a79-4597-b869-87d1315658fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446128773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.446128773
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3310899694
Short name T227
Test name
Test status
Simulation time 456471405 ps
CPU time 4.85 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:34 PM PDT 24
Peak memory 232836 kb
Host smart-b3f9c4ba-aa7d-41b3-b696-ffa3b4d493e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310899694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3310899694
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4254490461
Short name T681
Test name
Test status
Simulation time 17439961 ps
CPU time 0.82 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:30 PM PDT 24
Peak memory 206692 kb
Host smart-3db54a7d-943a-4d5d-b0a4-f7c19a985e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254490461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4254490461
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3028596740
Short name T270
Test name
Test status
Simulation time 19103152888 ps
CPU time 140.89 seconds
Started Jul 28 05:35:26 PM PDT 24
Finished Jul 28 05:37:47 PM PDT 24
Peak memory 257484 kb
Host smart-b8fd94e6-b8dd-46ea-bc07-8f629ee7e068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028596740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3028596740
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3538241565
Short name T449
Test name
Test status
Simulation time 44265186032 ps
CPU time 209.13 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:38:56 PM PDT 24
Peak memory 249412 kb
Host smart-49673791-e091-4bfc-9d75-4bb72fa8210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538241565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3538241565
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.34999643
Short name T284
Test name
Test status
Simulation time 385240327178 ps
CPU time 578.49 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:45:05 PM PDT 24
Peak memory 257472 kb
Host smart-e59dc8e9-b592-4da0-bf5e-32514c6a15e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34999643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.34999643
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2687106074
Short name T625
Test name
Test status
Simulation time 1123627864 ps
CPU time 4.2 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:34 PM PDT 24
Peak memory 232836 kb
Host smart-26505fd0-d0fb-405a-9cc3-a0d516f7f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687106074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2687106074
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2178134404
Short name T876
Test name
Test status
Simulation time 245071034 ps
CPU time 4.52 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:35:31 PM PDT 24
Peak memory 224644 kb
Host smart-ec89029e-5f2f-49b2-83eb-f7d606124eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178134404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2178134404
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1231664400
Short name T963
Test name
Test status
Simulation time 59716285738 ps
CPU time 38.14 seconds
Started Jul 28 05:35:28 PM PDT 24
Finished Jul 28 05:36:06 PM PDT 24
Peak memory 232916 kb
Host smart-a062e63d-a8c6-43fc-84f3-d68901922086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231664400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1231664400
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.274847903
Short name T401
Test name
Test status
Simulation time 3946875591 ps
CPU time 12.73 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:35:40 PM PDT 24
Peak memory 232860 kb
Host smart-5c227ff9-f6da-4304-a908-36416cf573ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274847903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.274847903
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2691113175
Short name T232
Test name
Test status
Simulation time 1500444347 ps
CPU time 4.8 seconds
Started Jul 28 05:35:28 PM PDT 24
Finished Jul 28 05:35:33 PM PDT 24
Peak memory 232788 kb
Host smart-d0f8459f-13d3-47ad-8be2-0e7f28a040e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691113175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2691113175
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1873676243
Short name T734
Test name
Test status
Simulation time 3033111869 ps
CPU time 9.41 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:38 PM PDT 24
Peak memory 222380 kb
Host smart-bc0b3532-a9a6-4534-8c4a-ece99a95dd7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873676243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1873676243
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1806456071
Short name T460
Test name
Test status
Simulation time 51015832 ps
CPU time 0.93 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:30 PM PDT 24
Peak memory 206924 kb
Host smart-9254e3fa-e930-4f19-93d0-5a862c066d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806456071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1806456071
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.822555478
Short name T447
Test name
Test status
Simulation time 28245987946 ps
CPU time 19.73 seconds
Started Jul 28 05:35:28 PM PDT 24
Finished Jul 28 05:35:47 PM PDT 24
Peak memory 216508 kb
Host smart-abc2136f-c329-4d0e-ac6c-645ac2c8c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822555478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.822555478
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.370254981
Short name T859
Test name
Test status
Simulation time 7153067256 ps
CPU time 22.73 seconds
Started Jul 28 05:35:28 PM PDT 24
Finished Jul 28 05:35:51 PM PDT 24
Peak memory 216432 kb
Host smart-3d606783-1bd7-4f54-9785-e4a780988486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370254981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.370254981
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1346643447
Short name T848
Test name
Test status
Simulation time 69497671 ps
CPU time 1.61 seconds
Started Jul 28 05:35:26 PM PDT 24
Finished Jul 28 05:35:28 PM PDT 24
Peak memory 216352 kb
Host smart-fb9f4abb-7aca-4ca8-b4a4-97e13e7aeed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346643447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1346643447
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2598235419
Short name T497
Test name
Test status
Simulation time 72466057 ps
CPU time 0.82 seconds
Started Jul 28 05:35:25 PM PDT 24
Finished Jul 28 05:35:26 PM PDT 24
Peak memory 206028 kb
Host smart-d78b5a9c-a084-4466-86cc-38c184c77361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598235419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2598235419
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3894910742
Short name T661
Test name
Test status
Simulation time 14948692114 ps
CPU time 15.77 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:35:43 PM PDT 24
Peak memory 249080 kb
Host smart-fc9ccf7b-67c3-4c6d-aee4-80c49b805c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894910742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3894910742
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4173135802
Short name T357
Test name
Test status
Simulation time 15813239 ps
CPU time 0.72 seconds
Started Jul 28 05:35:41 PM PDT 24
Finished Jul 28 05:35:42 PM PDT 24
Peak memory 204956 kb
Host smart-38367012-4c7f-4e9f-a7f9-0663fb5385ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173135802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4173135802
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4063571379
Short name T265
Test name
Test status
Simulation time 70648378 ps
CPU time 3.14 seconds
Started Jul 28 05:35:32 PM PDT 24
Finished Jul 28 05:35:35 PM PDT 24
Peak memory 232796 kb
Host smart-83a59b34-2b74-4814-82b0-c538041a5846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063571379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4063571379
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4264511678
Short name T375
Test name
Test status
Simulation time 47777889 ps
CPU time 0.77 seconds
Started Jul 28 05:35:26 PM PDT 24
Finished Jul 28 05:35:27 PM PDT 24
Peak memory 206972 kb
Host smart-004f7181-b3ca-4627-b172-5553f7aaf433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264511678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4264511678
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1425715986
Short name T285
Test name
Test status
Simulation time 26709010758 ps
CPU time 84.38 seconds
Started Jul 28 05:35:38 PM PDT 24
Finished Jul 28 05:37:03 PM PDT 24
Peak memory 253028 kb
Host smart-3cbe87e1-d0e8-4f2a-9eb9-5e2ceebf349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425715986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1425715986
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.982855060
Short name T306
Test name
Test status
Simulation time 6199833539 ps
CPU time 33.54 seconds
Started Jul 28 05:35:40 PM PDT 24
Finished Jul 28 05:36:13 PM PDT 24
Peak memory 217704 kb
Host smart-9d0f0fe6-4ef4-414b-a0f7-dc7ba5eae7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982855060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.982855060
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.387869805
Short name T278
Test name
Test status
Simulation time 111619659137 ps
CPU time 581.16 seconds
Started Jul 28 05:35:39 PM PDT 24
Finished Jul 28 05:45:20 PM PDT 24
Peak memory 272440 kb
Host smart-80d0d287-6905-473c-9f4f-651e86e009b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387869805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.387869805
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2114592451
Short name T294
Test name
Test status
Simulation time 1985533413 ps
CPU time 10.73 seconds
Started Jul 28 05:35:32 PM PDT 24
Finished Jul 28 05:35:43 PM PDT 24
Peak memory 232880 kb
Host smart-5f8b4096-59f2-4528-b1ff-b79115fa2648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114592451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2114592451
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2484834928
Short name T690
Test name
Test status
Simulation time 1394213034 ps
CPU time 28.09 seconds
Started Jul 28 05:35:39 PM PDT 24
Finished Jul 28 05:36:07 PM PDT 24
Peak memory 252296 kb
Host smart-c665f521-c74f-4ef0-acab-e6b3ff8d8743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484834928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2484834928
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1194626582
Short name T889
Test name
Test status
Simulation time 29517339 ps
CPU time 2.2 seconds
Started Jul 28 05:35:36 PM PDT 24
Finished Jul 28 05:35:39 PM PDT 24
Peak memory 218708 kb
Host smart-a830a5a7-96a8-47ff-9b19-829a2413658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194626582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1194626582
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3856882039
Short name T178
Test name
Test status
Simulation time 16937552310 ps
CPU time 63.77 seconds
Started Jul 28 05:35:33 PM PDT 24
Finished Jul 28 05:36:37 PM PDT 24
Peak memory 232904 kb
Host smart-83123c83-d28c-451b-b7cd-3be5cbe5c988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856882039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3856882039
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2364771511
Short name T470
Test name
Test status
Simulation time 75635567 ps
CPU time 2.34 seconds
Started Jul 28 05:35:32 PM PDT 24
Finished Jul 28 05:35:35 PM PDT 24
Peak memory 223156 kb
Host smart-eabb1163-c959-41f3-8a9e-f0387adc4d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364771511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2364771511
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1953804273
Short name T597
Test name
Test status
Simulation time 10054918821 ps
CPU time 28.37 seconds
Started Jul 28 05:35:34 PM PDT 24
Finished Jul 28 05:36:03 PM PDT 24
Peak memory 235864 kb
Host smart-3be5fee8-cb4f-4d48-9444-69d5abe3a916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953804273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1953804273
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2008706644
Short name T44
Test name
Test status
Simulation time 3345459668 ps
CPU time 10.18 seconds
Started Jul 28 05:35:39 PM PDT 24
Finished Jul 28 05:35:49 PM PDT 24
Peak memory 223168 kb
Host smart-757dc7fa-4bf0-45ea-bd32-7b54b16e5446
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008706644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2008706644
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3813051729
Short name T988
Test name
Test status
Simulation time 270055322 ps
CPU time 0.94 seconds
Started Jul 28 05:35:44 PM PDT 24
Finished Jul 28 05:35:45 PM PDT 24
Peak memory 207056 kb
Host smart-124b9eba-65c6-4143-9a3b-d82f6bebe319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813051729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3813051729
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1106849306
Short name T515
Test name
Test status
Simulation time 1306280544 ps
CPU time 11.26 seconds
Started Jul 28 05:35:27 PM PDT 24
Finished Jul 28 05:35:39 PM PDT 24
Peak memory 216576 kb
Host smart-319e267a-db6d-404c-875f-20195b0a61d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106849306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1106849306
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3694497782
Short name T1001
Test name
Test status
Simulation time 12489126174 ps
CPU time 9.02 seconds
Started Jul 28 05:35:29 PM PDT 24
Finished Jul 28 05:35:38 PM PDT 24
Peak memory 216540 kb
Host smart-4f886835-f15a-46ab-b2c8-f726643e2469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694497782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3694497782
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3968538077
Short name T394
Test name
Test status
Simulation time 399968936 ps
CPU time 2.34 seconds
Started Jul 28 05:35:35 PM PDT 24
Finished Jul 28 05:35:37 PM PDT 24
Peak memory 216328 kb
Host smart-a51789cc-6421-4e88-aa99-aa64b4cc6192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968538077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3968538077
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1952381752
Short name T496
Test name
Test status
Simulation time 45804161 ps
CPU time 0.71 seconds
Started Jul 28 05:35:26 PM PDT 24
Finished Jul 28 05:35:27 PM PDT 24
Peak memory 206084 kb
Host smart-6f094c25-62e0-498a-8157-612d172ddee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952381752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1952381752
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1835561533
Short name T353
Test name
Test status
Simulation time 1928449735 ps
CPU time 3.92 seconds
Started Jul 28 05:35:34 PM PDT 24
Finished Jul 28 05:35:38 PM PDT 24
Peak memory 224680 kb
Host smart-b7ed1113-d589-4385-b084-d583f38fdd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835561533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1835561533
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2459942218
Short name T700
Test name
Test status
Simulation time 15896393 ps
CPU time 0.74 seconds
Started Jul 28 05:35:46 PM PDT 24
Finished Jul 28 05:35:47 PM PDT 24
Peak memory 205580 kb
Host smart-0511186d-d0eb-4116-b5ff-4de54e8805d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459942218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2459942218
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.785421128
Short name T826
Test name
Test status
Simulation time 482072035 ps
CPU time 5.62 seconds
Started Jul 28 05:35:40 PM PDT 24
Finished Jul 28 05:35:45 PM PDT 24
Peak memory 224576 kb
Host smart-e67db500-a9d7-40bd-aa97-31459c079e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785421128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.785421128
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2523254547
Short name T776
Test name
Test status
Simulation time 50988197 ps
CPU time 0.79 seconds
Started Jul 28 05:35:38 PM PDT 24
Finished Jul 28 05:35:39 PM PDT 24
Peak memory 206704 kb
Host smart-dbf18299-98e2-4cb2-935d-eca088801e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523254547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2523254547
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3983313377
Short name T513
Test name
Test status
Simulation time 2650009279 ps
CPU time 19.25 seconds
Started Jul 28 05:35:48 PM PDT 24
Finished Jul 28 05:36:08 PM PDT 24
Peak memory 241096 kb
Host smart-6b1d81e8-62cd-4130-9fa6-d1c8bb549e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983313377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3983313377
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3874259941
Short name T167
Test name
Test status
Simulation time 25126037236 ps
CPU time 94.89 seconds
Started Jul 28 05:35:43 PM PDT 24
Finished Jul 28 05:37:18 PM PDT 24
Peak memory 232944 kb
Host smart-4f71171b-f517-4b0a-ab98-088f71fb0669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874259941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3874259941
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.806269025
Short name T322
Test name
Test status
Simulation time 5383311480 ps
CPU time 28.29 seconds
Started Jul 28 05:35:44 PM PDT 24
Finished Jul 28 05:36:13 PM PDT 24
Peak memory 217824 kb
Host smart-512466df-e52a-46db-8803-29a96dc0e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806269025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.806269025
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1816058775
Short name T600
Test name
Test status
Simulation time 107701014 ps
CPU time 5.36 seconds
Started Jul 28 05:35:40 PM PDT 24
Finished Jul 28 05:35:46 PM PDT 24
Peak memory 233880 kb
Host smart-56764068-50b6-4838-bc4d-4135b715f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816058775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1816058775
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4034780578
Short name T824
Test name
Test status
Simulation time 3043491960 ps
CPU time 35.81 seconds
Started Jul 28 05:35:44 PM PDT 24
Finished Jul 28 05:36:20 PM PDT 24
Peak memory 257496 kb
Host smart-4b095337-c58c-4383-93c7-ce1c4bec52ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034780578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4034780578
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2605865624
Short name T637
Test name
Test status
Simulation time 126244382 ps
CPU time 3.64 seconds
Started Jul 28 05:35:38 PM PDT 24
Finished Jul 28 05:35:42 PM PDT 24
Peak memory 224676 kb
Host smart-702456e4-4383-460c-a8d4-73b4dcc44724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605865624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2605865624
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.981872093
Short name T666
Test name
Test status
Simulation time 15448240913 ps
CPU time 43.08 seconds
Started Jul 28 05:35:38 PM PDT 24
Finished Jul 28 05:36:21 PM PDT 24
Peak memory 232936 kb
Host smart-cd47b3b5-89bf-45c7-893a-fa6950999307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981872093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.981872093
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.622955637
Short name T45
Test name
Test status
Simulation time 8577758258 ps
CPU time 5.74 seconds
Started Jul 28 05:35:39 PM PDT 24
Finished Jul 28 05:35:45 PM PDT 24
Peak memory 239760 kb
Host smart-04eed6d5-d5ea-4284-ad21-e4cab0f2a280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622955637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.622955637
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3055440929
Short name T517
Test name
Test status
Simulation time 2065068876 ps
CPU time 3.44 seconds
Started Jul 28 05:35:38 PM PDT 24
Finished Jul 28 05:35:42 PM PDT 24
Peak memory 224640 kb
Host smart-1c80e200-2cf4-4e5e-9125-a723550fbd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055440929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3055440929
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1350820313
Short name T933
Test name
Test status
Simulation time 808351051 ps
CPU time 9.8 seconds
Started Jul 28 05:35:48 PM PDT 24
Finished Jul 28 05:35:58 PM PDT 24
Peak memory 221960 kb
Host smart-e4412d67-d1e9-46d2-bc25-aa19225feca7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1350820313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1350820313
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1518975322
Short name T867
Test name
Test status
Simulation time 17243188927 ps
CPU time 170.69 seconds
Started Jul 28 05:35:45 PM PDT 24
Finished Jul 28 05:38:36 PM PDT 24
Peak memory 265748 kb
Host smart-b416d9ab-5647-41af-a988-8c5d06626755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518975322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1518975322
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2900170908
Short name T613
Test name
Test status
Simulation time 2865883576 ps
CPU time 28.52 seconds
Started Jul 28 05:35:39 PM PDT 24
Finished Jul 28 05:36:07 PM PDT 24
Peak memory 220352 kb
Host smart-391657b4-33b6-4f9f-bf58-544679f457d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900170908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2900170908
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2457325832
Short name T618
Test name
Test status
Simulation time 187318211 ps
CPU time 1.55 seconds
Started Jul 28 05:35:38 PM PDT 24
Finished Jul 28 05:35:40 PM PDT 24
Peak memory 207992 kb
Host smart-902cc35e-0efb-4acd-8fd1-bb50ba7c193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457325832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2457325832
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.664736401
Short name T674
Test name
Test status
Simulation time 21607189 ps
CPU time 0.97 seconds
Started Jul 28 05:35:40 PM PDT 24
Finished Jul 28 05:35:41 PM PDT 24
Peak memory 208012 kb
Host smart-1c6a1969-c72f-4f54-a0d9-bf771c686345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664736401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.664736401
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1062481657
Short name T771
Test name
Test status
Simulation time 196577151 ps
CPU time 1.07 seconds
Started Jul 28 05:35:39 PM PDT 24
Finished Jul 28 05:35:40 PM PDT 24
Peak memory 207120 kb
Host smart-5dd3aa04-12b4-49e0-99f0-fcaa3960b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062481657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1062481657
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2025839679
Short name T435
Test name
Test status
Simulation time 430793137 ps
CPU time 6.55 seconds
Started Jul 28 05:35:44 PM PDT 24
Finished Jul 28 05:35:51 PM PDT 24
Peak memory 224688 kb
Host smart-e5d625c8-0680-4d66-a2c6-4870495585dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025839679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2025839679
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1253812397
Short name T658
Test name
Test status
Simulation time 14899595 ps
CPU time 0.73 seconds
Started Jul 28 05:32:20 PM PDT 24
Finished Jul 28 05:32:21 PM PDT 24
Peak memory 205016 kb
Host smart-5248feb9-96c6-43b9-bae1-b70a2978f5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253812397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
253812397
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1382625179
Short name T688
Test name
Test status
Simulation time 990656232 ps
CPU time 12.19 seconds
Started Jul 28 05:32:21 PM PDT 24
Finished Jul 28 05:32:33 PM PDT 24
Peak memory 224604 kb
Host smart-674f2e52-7540-426f-828e-422bd455512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382625179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1382625179
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.391390282
Short name T951
Test name
Test status
Simulation time 40453386 ps
CPU time 0.75 seconds
Started Jul 28 05:32:22 PM PDT 24
Finished Jul 28 05:32:23 PM PDT 24
Peak memory 205692 kb
Host smart-6f65ecc1-5e0e-448f-9a0e-a62919aa843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391390282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.391390282
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3101947787
Short name T526
Test name
Test status
Simulation time 5009557354 ps
CPU time 71.09 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:33:34 PM PDT 24
Peak memory 249304 kb
Host smart-68a49b63-c652-49af-af88-96b732809192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101947787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3101947787
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4056602695
Short name T255
Test name
Test status
Simulation time 56385832359 ps
CPU time 411.08 seconds
Started Jul 28 05:32:25 PM PDT 24
Finished Jul 28 05:39:16 PM PDT 24
Peak memory 251504 kb
Host smart-e9e194ae-b429-4c46-b293-20597758e611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056602695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4056602695
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3485676574
Short name T714
Test name
Test status
Simulation time 7636302172 ps
CPU time 51.32 seconds
Started Jul 28 05:32:26 PM PDT 24
Finished Jul 28 05:33:18 PM PDT 24
Peak memory 240780 kb
Host smart-4fc04e91-d9bf-45ca-86e1-0d87a1bd7337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485676574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3485676574
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.28098143
Short name T720
Test name
Test status
Simulation time 190686049 ps
CPU time 3.99 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 224676 kb
Host smart-7dfef394-ba96-428d-925d-7a2fc665b03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28098143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.28098143
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.739913027
Short name T621
Test name
Test status
Simulation time 14856566299 ps
CPU time 67.68 seconds
Started Jul 28 05:32:27 PM PDT 24
Finished Jul 28 05:33:35 PM PDT 24
Peak memory 249320 kb
Host smart-c0289116-89aa-4a62-9de5-52ddf282db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739913027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
739913027
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1237532997
Short name T35
Test name
Test status
Simulation time 766956219 ps
CPU time 6.01 seconds
Started Jul 28 05:32:27 PM PDT 24
Finished Jul 28 05:32:33 PM PDT 24
Peak memory 224644 kb
Host smart-77eeb01a-3256-4643-bab8-901db9bc55bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237532997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1237532997
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.98643702
Short name T920
Test name
Test status
Simulation time 4506430561 ps
CPU time 15.32 seconds
Started Jul 28 05:32:22 PM PDT 24
Finished Jul 28 05:32:37 PM PDT 24
Peak memory 232932 kb
Host smart-52a3b2c2-2e5e-45fb-82de-ea5780abfb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98643702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.98643702
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2002734340
Short name T494
Test name
Test status
Simulation time 6787787193 ps
CPU time 19.91 seconds
Started Jul 28 05:32:21 PM PDT 24
Finished Jul 28 05:32:41 PM PDT 24
Peak memory 232936 kb
Host smart-0b6fc796-19e3-4afc-a937-02e5cddb1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002734340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2002734340
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.756802930
Short name T831
Test name
Test status
Simulation time 16422061103 ps
CPU time 8.03 seconds
Started Jul 28 05:32:27 PM PDT 24
Finished Jul 28 05:32:35 PM PDT 24
Peak memory 232848 kb
Host smart-cf30fb06-5c61-4ddd-9a96-f68e90824d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756802930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.756802930
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.73837784
Short name T7
Test name
Test status
Simulation time 7018847325 ps
CPU time 13.73 seconds
Started Jul 28 05:32:20 PM PDT 24
Finished Jul 28 05:32:34 PM PDT 24
Peak memory 221784 kb
Host smart-9e3be508-b4a5-4cde-92eb-93a50860189c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=73837784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.73837784
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.992205008
Short name T749
Test name
Test status
Simulation time 10629537774 ps
CPU time 143.93 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:34:47 PM PDT 24
Peak memory 273540 kb
Host smart-3e0b9705-2e61-480e-89d7-055a65dd193f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992205008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.992205008
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2689931023
Short name T797
Test name
Test status
Simulation time 1677640025 ps
CPU time 14.02 seconds
Started Jul 28 05:32:20 PM PDT 24
Finished Jul 28 05:32:34 PM PDT 24
Peak memory 216436 kb
Host smart-7e868a4b-25b7-4fbb-81b0-bd4fc9783cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689931023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2689931023
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1984718028
Short name T607
Test name
Test status
Simulation time 2972124991 ps
CPU time 4.27 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:28 PM PDT 24
Peak memory 216444 kb
Host smart-4cf37995-2d7a-4d87-a743-3c2991a41f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984718028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1984718028
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.307920415
Short name T650
Test name
Test status
Simulation time 75332826 ps
CPU time 1.11 seconds
Started Jul 28 05:32:22 PM PDT 24
Finished Jul 28 05:32:23 PM PDT 24
Peak memory 207952 kb
Host smart-de8f6ba3-9c0d-452d-b781-601edc468d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307920415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.307920415
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.452199999
Short name T25
Test name
Test status
Simulation time 32363617 ps
CPU time 0.76 seconds
Started Jul 28 05:32:25 PM PDT 24
Finished Jul 28 05:32:26 PM PDT 24
Peak memory 206068 kb
Host smart-43c6bcba-5402-4b81-87db-4332893875fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452199999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.452199999
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3012961314
Short name T114
Test name
Test status
Simulation time 4170412485 ps
CPU time 7.75 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:32 PM PDT 24
Peak memory 224752 kb
Host smart-655871fb-30be-4cae-9b59-20ddcb4a7e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012961314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3012961314
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1846019607
Short name T377
Test name
Test status
Simulation time 11620404 ps
CPU time 0.8 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:31 PM PDT 24
Peak memory 204984 kb
Host smart-85300d46-3ef1-404d-a8de-6452d10896f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846019607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
846019607
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2998110644
Short name T813
Test name
Test status
Simulation time 683550194 ps
CPU time 5.71 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:30 PM PDT 24
Peak memory 232796 kb
Host smart-5d3880af-3200-4145-bd42-a797d26379d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998110644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2998110644
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2594201766
Short name T832
Test name
Test status
Simulation time 13035063 ps
CPU time 0.85 seconds
Started Jul 28 05:32:25 PM PDT 24
Finished Jul 28 05:32:26 PM PDT 24
Peak memory 206592 kb
Host smart-ca61c974-c668-4a67-9166-53cdeaf3687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594201766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2594201766
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1176815880
Short name T280
Test name
Test status
Simulation time 24019284114 ps
CPU time 130.84 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:34:40 PM PDT 24
Peak memory 270700 kb
Host smart-66e03bb5-f305-4f07-a339-a9343952bc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176815880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1176815880
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3007835577
Short name T874
Test name
Test status
Simulation time 4104761189 ps
CPU time 46.94 seconds
Started Jul 28 05:32:32 PM PDT 24
Finished Jul 28 05:33:19 PM PDT 24
Peak memory 249404 kb
Host smart-061ac1dc-bc78-4ddf-9ea2-e4c4bf4d45dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007835577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3007835577
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3696890140
Short name T868
Test name
Test status
Simulation time 969590958 ps
CPU time 15.54 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:32:38 PM PDT 24
Peak memory 224688 kb
Host smart-4391baad-650c-4b65-865f-2491f1d98478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696890140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3696890140
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1511214952
Short name T260
Test name
Test status
Simulation time 4672812356 ps
CPU time 16.43 seconds
Started Jul 28 05:32:23 PM PDT 24
Finished Jul 28 05:32:40 PM PDT 24
Peak memory 224736 kb
Host smart-d61cf6b7-3412-4365-adb9-ecc11fa1a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511214952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1511214952
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1651857311
Short name T721
Test name
Test status
Simulation time 11388572660 ps
CPU time 25.99 seconds
Started Jul 28 05:32:27 PM PDT 24
Finished Jul 28 05:32:53 PM PDT 24
Peak memory 232160 kb
Host smart-30a92b67-1701-4c94-bf4b-30c00e6dccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651857311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1651857311
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2996648280
Short name T205
Test name
Test status
Simulation time 5629542899 ps
CPU time 22.54 seconds
Started Jul 28 05:32:25 PM PDT 24
Finished Jul 28 05:32:48 PM PDT 24
Peak memory 240868 kb
Host smart-2f93cdb4-c9ee-4658-8a18-40033ce8a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996648280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2996648280
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.53541463
Short name T577
Test name
Test status
Simulation time 100833659 ps
CPU time 2.94 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 232748 kb
Host smart-620b43cd-471d-4294-b33a-c4e1b8ba6a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53541463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.53541463
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3977928155
Short name T976
Test name
Test status
Simulation time 158241796 ps
CPU time 4.07 seconds
Started Jul 28 05:32:28 PM PDT 24
Finished Jul 28 05:32:32 PM PDT 24
Peak memory 219036 kb
Host smart-5a7b9ee3-4fc5-445b-b4a0-830bfb4efcec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977928155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3977928155
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1530207240
Short name T144
Test name
Test status
Simulation time 68836686863 ps
CPU time 630.21 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:43:00 PM PDT 24
Peak memory 265772 kb
Host smart-35b65952-dc8b-475d-9988-d74146d143c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530207240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1530207240
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2058132919
Short name T991
Test name
Test status
Simulation time 5595390973 ps
CPU time 8.16 seconds
Started Jul 28 05:32:21 PM PDT 24
Finished Jul 28 05:32:30 PM PDT 24
Peak memory 219892 kb
Host smart-3753e734-2e5d-4359-8feb-cfa6f83e8c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058132919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2058132919
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1241712901
Short name T974
Test name
Test status
Simulation time 21408219 ps
CPU time 0.71 seconds
Started Jul 28 05:32:26 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 205776 kb
Host smart-c2f3f50d-0f24-4bc1-83e2-bfa1efe8ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241712901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1241712901
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2599796654
Short name T760
Test name
Test status
Simulation time 53891006 ps
CPU time 1.59 seconds
Started Jul 28 05:32:25 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 216400 kb
Host smart-9a84a752-e623-450f-b01e-8f55287fafd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599796654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2599796654
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4176561764
Short name T54
Test name
Test status
Simulation time 77987219 ps
CPU time 0.76 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:25 PM PDT 24
Peak memory 206060 kb
Host smart-7fdfce2b-72d4-468e-a573-4603336fedf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176561764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4176561764
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2528144557
Short name T936
Test name
Test status
Simulation time 109744672 ps
CPU time 2.59 seconds
Started Jul 28 05:32:24 PM PDT 24
Finished Jul 28 05:32:27 PM PDT 24
Peak memory 232764 kb
Host smart-4a918b2d-c97e-46b7-8443-893b21a6901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528144557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2528144557
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3666333488
Short name T57
Test name
Test status
Simulation time 41987408 ps
CPU time 0.73 seconds
Started Jul 28 05:32:31 PM PDT 24
Finished Jul 28 05:32:32 PM PDT 24
Peak memory 205492 kb
Host smart-98da0c46-834a-49fb-a91f-5fb3a9b877cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666333488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
666333488
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.51000873
Short name T552
Test name
Test status
Simulation time 3987086040 ps
CPU time 10.59 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:40 PM PDT 24
Peak memory 232824 kb
Host smart-8225b9ad-c144-4639-aa28-9d2c1d0ec491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51000873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.51000873
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3975349108
Short name T777
Test name
Test status
Simulation time 29876920 ps
CPU time 0.78 seconds
Started Jul 28 05:32:32 PM PDT 24
Finished Jul 28 05:32:33 PM PDT 24
Peak memory 205724 kb
Host smart-97c2fcc3-8215-436f-9582-c9b14e7abf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975349108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3975349108
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.146480884
Short name T907
Test name
Test status
Simulation time 87154997514 ps
CPU time 134.72 seconds
Started Jul 28 05:32:35 PM PDT 24
Finished Jul 28 05:34:50 PM PDT 24
Peak memory 250784 kb
Host smart-65a0df00-9135-48be-b3e7-6fa71c4b447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146480884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.146480884
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.645423200
Short name T194
Test name
Test status
Simulation time 48130782332 ps
CPU time 455.28 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:40:05 PM PDT 24
Peak memory 250276 kb
Host smart-3b48330c-c43f-4b8e-b076-93a763df6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645423200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.645423200
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.957148521
Short name T812
Test name
Test status
Simulation time 1651532554 ps
CPU time 29.91 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 249332 kb
Host smart-b10fbf29-520a-417e-a10d-7c9ee498e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957148521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
957148521
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1212035873
Short name T532
Test name
Test status
Simulation time 124405392 ps
CPU time 2.53 seconds
Started Jul 28 05:32:31 PM PDT 24
Finished Jul 28 05:32:34 PM PDT 24
Peak memory 232808 kb
Host smart-1d161478-0e6f-4ec2-b0e0-5b667522a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212035873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1212035873
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1872712468
Short name T723
Test name
Test status
Simulation time 29433713024 ps
CPU time 61.97 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:33:32 PM PDT 24
Peak memory 237968 kb
Host smart-8cdddf8b-e9aa-4703-aa8f-ae7a9407b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872712468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1872712468
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.356950608
Short name T191
Test name
Test status
Simulation time 2139292492 ps
CPU time 8.15 seconds
Started Jul 28 05:32:34 PM PDT 24
Finished Jul 28 05:32:42 PM PDT 24
Peak memory 224696 kb
Host smart-ffce2a26-1c32-4a95-8d7f-90498d4abf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356950608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.356950608
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3444107682
Short name T119
Test name
Test status
Simulation time 1359985959 ps
CPU time 21.17 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 232784 kb
Host smart-858fa189-220f-47ca-afeb-23b0432f3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444107682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3444107682
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2325256835
Short name T962
Test name
Test status
Simulation time 31059649933 ps
CPU time 20.19 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:32:50 PM PDT 24
Peak memory 249284 kb
Host smart-349498cc-b462-4193-880b-f7b42893d451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325256835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2325256835
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1194505700
Short name T209
Test name
Test status
Simulation time 1576797878 ps
CPU time 3.75 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:34 PM PDT 24
Peak memory 232820 kb
Host smart-fca728c2-5647-4682-8083-fdb89e0cb944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194505700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1194505700
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3312179972
Short name T683
Test name
Test status
Simulation time 3409864888 ps
CPU time 5.57 seconds
Started Jul 28 05:32:33 PM PDT 24
Finished Jul 28 05:32:39 PM PDT 24
Peak memory 223432 kb
Host smart-34dbb252-3cff-43a0-8dc2-063058669d97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3312179972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3312179972
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2587878750
Short name T628
Test name
Test status
Simulation time 54337302 ps
CPU time 1.04 seconds
Started Jul 28 05:32:35 PM PDT 24
Finished Jul 28 05:32:36 PM PDT 24
Peak memory 207036 kb
Host smart-f3c16ce5-58de-494a-929d-d5ba91edb28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587878750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2587878750
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.772694899
Short name T11
Test name
Test status
Simulation time 18489280415 ps
CPU time 24.13 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:32:54 PM PDT 24
Peak memory 216504 kb
Host smart-df439292-1de4-4ef8-bec0-dfc00ce52f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772694899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.772694899
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3768371187
Short name T348
Test name
Test status
Simulation time 34310332 ps
CPU time 0.74 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:31 PM PDT 24
Peak memory 205808 kb
Host smart-01f0e242-0f6a-4471-baa7-af9df1e20303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768371187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3768371187
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1944625008
Short name T706
Test name
Test status
Simulation time 178712920 ps
CPU time 4.59 seconds
Started Jul 28 05:32:35 PM PDT 24
Finished Jul 28 05:32:39 PM PDT 24
Peak memory 216404 kb
Host smart-beadccfb-61c0-49c9-aaf3-08f359a28913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944625008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1944625008
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3569163786
Short name T422
Test name
Test status
Simulation time 33388087 ps
CPU time 0.71 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:31 PM PDT 24
Peak memory 205648 kb
Host smart-2835293f-e5f9-4447-9c80-7f454b2fdb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569163786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3569163786
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.685824642
Short name T814
Test name
Test status
Simulation time 302394012 ps
CPU time 2.25 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:32:31 PM PDT 24
Peak memory 224260 kb
Host smart-1a91760f-19fe-4687-9fb3-b16cd70899cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685824642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.685824642
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2691526433
Short name T510
Test name
Test status
Simulation time 15276077 ps
CPU time 0.7 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 205000 kb
Host smart-972a712c-0430-4e20-9c6d-0ac297beea22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691526433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
691526433
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2649519236
Short name T443
Test name
Test status
Simulation time 312205455 ps
CPU time 6.28 seconds
Started Jul 28 05:32:28 PM PDT 24
Finished Jul 28 05:32:35 PM PDT 24
Peak memory 224656 kb
Host smart-f9ec1de2-3a02-4c74-a5b5-66fc4f2f65f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649519236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2649519236
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3783051706
Short name T727
Test name
Test status
Simulation time 15497765 ps
CPU time 0.74 seconds
Started Jul 28 05:32:31 PM PDT 24
Finished Jul 28 05:32:32 PM PDT 24
Peak memory 206008 kb
Host smart-8b9d65b0-30c8-435e-a062-7cc27bb8ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783051706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3783051706
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2485386282
Short name T504
Test name
Test status
Simulation time 6296711314 ps
CPU time 21.72 seconds
Started Jul 28 05:32:39 PM PDT 24
Finished Jul 28 05:33:01 PM PDT 24
Peak memory 239484 kb
Host smart-d3f1e2bd-f954-41d9-8b17-e9f35c1a3958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485386282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2485386282
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2372826269
Short name T885
Test name
Test status
Simulation time 811725950 ps
CPU time 7.48 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:54 PM PDT 24
Peak memory 217624 kb
Host smart-dfef8195-42ce-485c-9186-303b23f27f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372826269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2372826269
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1892000112
Short name T146
Test name
Test status
Simulation time 362169710 ps
CPU time 7.49 seconds
Started Jul 28 05:32:32 PM PDT 24
Finished Jul 28 05:32:40 PM PDT 24
Peak memory 232900 kb
Host smart-d048d1d2-faff-4335-8d3b-8250675d5402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892000112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1892000112
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2302204978
Short name T709
Test name
Test status
Simulation time 5508809973 ps
CPU time 36.34 seconds
Started Jul 28 05:32:31 PM PDT 24
Finished Jul 28 05:33:07 PM PDT 24
Peak memory 234440 kb
Host smart-168eb796-f5d2-405a-92c5-aa5c9dfd28c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302204978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2302204978
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4189309937
Short name T198
Test name
Test status
Simulation time 884159294 ps
CPU time 6.2 seconds
Started Jul 28 05:32:40 PM PDT 24
Finished Jul 28 05:32:46 PM PDT 24
Peak memory 224628 kb
Host smart-73f2ce62-6661-4cf2-9ed6-ac16ba1ff1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189309937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4189309937
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3468724284
Short name T712
Test name
Test status
Simulation time 30372907 ps
CPU time 2.3 seconds
Started Jul 28 05:32:33 PM PDT 24
Finished Jul 28 05:32:36 PM PDT 24
Peak memory 232540 kb
Host smart-0518ec46-a72f-4726-a66f-202a8f6f480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468724284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3468724284
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4230609348
Short name T1007
Test name
Test status
Simulation time 26504614626 ps
CPU time 11.52 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:41 PM PDT 24
Peak memory 224672 kb
Host smart-1d819de4-65c9-43a1-bac9-4396511306e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230609348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4230609348
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1792236533
Short name T942
Test name
Test status
Simulation time 1084756789 ps
CPU time 5.69 seconds
Started Jul 28 05:32:33 PM PDT 24
Finished Jul 28 05:32:39 PM PDT 24
Peak memory 232832 kb
Host smart-e89181aa-6960-4626-a33f-fcba9c9b1217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792236533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1792236533
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2684541736
Short name T491
Test name
Test status
Simulation time 956394727 ps
CPU time 5.41 seconds
Started Jul 28 05:32:31 PM PDT 24
Finished Jul 28 05:32:37 PM PDT 24
Peak memory 222800 kb
Host smart-992ff053-076e-4995-a6df-086f1444d5dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2684541736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2684541736
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.759985788
Short name T142
Test name
Test status
Simulation time 63964450 ps
CPU time 1.13 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 207200 kb
Host smart-1e329bea-eaf2-4cf6-af6d-bd6652b641dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759985788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.759985788
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1504034074
Short name T596
Test name
Test status
Simulation time 6455718946 ps
CPU time 31.68 seconds
Started Jul 28 05:32:28 PM PDT 24
Finished Jul 28 05:33:00 PM PDT 24
Peak memory 216396 kb
Host smart-5e6d91db-9fac-491d-ab9b-5e3c316a4b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504034074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1504034074
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2289910359
Short name T373
Test name
Test status
Simulation time 8831813203 ps
CPU time 6.21 seconds
Started Jul 28 05:32:30 PM PDT 24
Finished Jul 28 05:32:37 PM PDT 24
Peak memory 216476 kb
Host smart-c287ffc4-ae2a-45f8-85b3-dac84d612fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289910359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2289910359
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3290559541
Short name T147
Test name
Test status
Simulation time 24680372 ps
CPU time 0.77 seconds
Started Jul 28 05:32:29 PM PDT 24
Finished Jul 28 05:32:30 PM PDT 24
Peak memory 206060 kb
Host smart-6caed084-d265-4ac2-9ef8-eafa957204a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290559541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3290559541
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1520197881
Short name T739
Test name
Test status
Simulation time 45889293 ps
CPU time 0.79 seconds
Started Jul 28 05:32:27 PM PDT 24
Finished Jul 28 05:32:28 PM PDT 24
Peak memory 206012 kb
Host smart-9bb429d9-cebd-41a6-9791-d7d813a5e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520197881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1520197881
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.58412313
Short name T251
Test name
Test status
Simulation time 3018188862 ps
CPU time 8.97 seconds
Started Jul 28 05:32:34 PM PDT 24
Finished Jul 28 05:32:43 PM PDT 24
Peak memory 232904 kb
Host smart-02663c4f-0a34-4985-8e62-7db32f1359cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58412313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.58412313
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.780304910
Short name T994
Test name
Test status
Simulation time 101866209 ps
CPU time 0.79 seconds
Started Jul 28 05:32:51 PM PDT 24
Finished Jul 28 05:32:52 PM PDT 24
Peak memory 205916 kb
Host smart-3e3a6851-cf62-4963-a752-02b559b18082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780304910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.780304910
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3889675291
Short name T346
Test name
Test status
Simulation time 846034516 ps
CPU time 3.48 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:53 PM PDT 24
Peak memory 224616 kb
Host smart-f4dbc9ed-51b6-4ef5-8cb0-3505cb8839cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889675291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3889675291
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.589080285
Short name T886
Test name
Test status
Simulation time 31247846 ps
CPU time 0.75 seconds
Started Jul 28 05:32:50 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 205900 kb
Host smart-94ee7dac-4e0b-4972-9b0f-10c67bc084af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589080285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.589080285
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3043021913
Short name T984
Test name
Test status
Simulation time 3668227358 ps
CPU time 12.5 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:32:59 PM PDT 24
Peak memory 241088 kb
Host smart-1679ed8c-751e-434e-9612-15d5c800532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043021913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3043021913
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1058538520
Short name T192
Test name
Test status
Simulation time 33341189379 ps
CPU time 357.65 seconds
Started Jul 28 05:32:45 PM PDT 24
Finished Jul 28 05:38:43 PM PDT 24
Peak memory 268364 kb
Host smart-bf863f0f-b9b9-42fe-8abb-b2f484468c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058538520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1058538520
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2361669684
Short name T273
Test name
Test status
Simulation time 143921404499 ps
CPU time 405.17 seconds
Started Jul 28 05:32:36 PM PDT 24
Finished Jul 28 05:39:22 PM PDT 24
Peak memory 266784 kb
Host smart-5d5c6da7-59f0-4284-b747-7b4e67da906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361669684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2361669684
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3881408195
Short name T557
Test name
Test status
Simulation time 460439227 ps
CPU time 3.1 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:50 PM PDT 24
Peak memory 224660 kb
Host smart-536895ee-4db2-42b8-8f9c-88b7d89ac4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881408195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3881408195
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3451241543
Short name T164
Test name
Test status
Simulation time 4851874058 ps
CPU time 28.86 seconds
Started Jul 28 05:32:39 PM PDT 24
Finished Jul 28 05:33:08 PM PDT 24
Peak memory 251652 kb
Host smart-be7c03b5-9cc1-4293-80c7-13bbade01b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451241543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3451241543
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3776073473
Short name T522
Test name
Test status
Simulation time 662655198 ps
CPU time 5.65 seconds
Started Jul 28 05:32:47 PM PDT 24
Finished Jul 28 05:32:53 PM PDT 24
Peak memory 232808 kb
Host smart-7885f7f7-fd33-43fc-bd3e-edc8616e62e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776073473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3776073473
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1864966890
Short name T585
Test name
Test status
Simulation time 21463426641 ps
CPU time 133.14 seconds
Started Jul 28 05:32:38 PM PDT 24
Finished Jul 28 05:34:51 PM PDT 24
Peak memory 234124 kb
Host smart-fbee09f5-aa74-4509-96ee-f2d55e05f37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864966890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1864966890
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1291761934
Short name T381
Test name
Test status
Simulation time 62724902 ps
CPU time 2.75 seconds
Started Jul 28 05:32:49 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 232828 kb
Host smart-70e4d459-d813-4308-878b-136b76f0ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291761934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1291761934
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.313052880
Short name T947
Test name
Test status
Simulation time 5868384030 ps
CPU time 12.2 seconds
Started Jul 28 05:32:39 PM PDT 24
Finished Jul 28 05:32:51 PM PDT 24
Peak memory 224676 kb
Host smart-043ed55a-85c1-4214-9dcb-98e756439806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313052880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.313052880
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1132320115
Short name T892
Test name
Test status
Simulation time 240217716 ps
CPU time 4.79 seconds
Started Jul 28 05:32:38 PM PDT 24
Finished Jul 28 05:32:43 PM PDT 24
Peak memory 220556 kb
Host smart-f65f9032-bd5a-492c-b867-9e2f43e68a33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132320115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1132320115
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4289999963
Short name T140
Test name
Test status
Simulation time 20240981016 ps
CPU time 106.48 seconds
Started Jul 28 05:32:40 PM PDT 24
Finished Jul 28 05:34:26 PM PDT 24
Peak memory 252128 kb
Host smart-dbcf0cbc-b928-4ba4-a829-919e92f84dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289999963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4289999963
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3981881383
Short name T521
Test name
Test status
Simulation time 1816942234 ps
CPU time 8.75 seconds
Started Jul 28 05:32:38 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 219260 kb
Host smart-744f1334-6432-4ebf-8dbf-5a1f4f5e6d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981881383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3981881383
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.669538492
Short name T946
Test name
Test status
Simulation time 17089498 ps
CPU time 0.72 seconds
Started Jul 28 05:32:44 PM PDT 24
Finished Jul 28 05:32:45 PM PDT 24
Peak memory 205788 kb
Host smart-4f9d4749-8467-46f4-afff-7979bff74e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669538492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.669538492
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3857253892
Short name T756
Test name
Test status
Simulation time 19415639 ps
CPU time 0.7 seconds
Started Jul 28 05:32:46 PM PDT 24
Finished Jul 28 05:32:47 PM PDT 24
Peak memory 205680 kb
Host smart-15369327-2366-404b-8cd9-e92450a1970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857253892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3857253892
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2432389607
Short name T914
Test name
Test status
Simulation time 12542325 ps
CPU time 0.7 seconds
Started Jul 28 05:32:36 PM PDT 24
Finished Jul 28 05:32:37 PM PDT 24
Peak memory 205688 kb
Host smart-cf6af1cc-fd96-4df6-a241-96a28fd147c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432389607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2432389607
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2540276695
Short name T238
Test name
Test status
Simulation time 1476191948 ps
CPU time 3.87 seconds
Started Jul 28 05:32:37 PM PDT 24
Finished Jul 28 05:32:41 PM PDT 24
Peak memory 224680 kb
Host smart-db8b7542-90f3-40f1-a023-798aec585b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540276695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2540276695
Directory /workspace/9.spi_device_upload/latest
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