Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2524212	1			T1	7589		T2	1		T3	1
all_values[1]	2524212	1			T1	7589		T2	1		T3	1
all_values[2]	2524212	1			T1	7589		T2	1		T3	1
all_values[3]	2524212	1			T1	7589		T2	1		T3	1
all_values[4]	2524212	1			T1	7589		T2	1		T3	1
all_values[5]	2524212	1			T1	7589		T2	1		T3	1
all_values[6]	2524212	1			T1	7589		T2	1		T3	1
all_values[7]	2524212	1			T1	7589		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19509734

1

T1

60712

T2

8

T3

8

auto[1]

683962

1

T12

90

T13

26

T14

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20167643

1

T1

60712

T2

8

T3

8

auto[1]

26053

1

T6

133

T8

18

T11

392

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2414911	1			T1	7589		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	11593	1			T6	131		T8	18		T11	197
all_values[0]	auto[1]	auto[0]	96758	1			T12	9		T14	2		T15	7
all_values[0]	auto[1]	auto[1]	950	1			T12	3		T14	3		T15	4
all_values[1]	auto[0]	auto[0]	2491743	1			T1	7589		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	7575	1			T6	2		T11	147		T12	177
all_values[1]	auto[1]	auto[0]	24136	1			T12	4		T13	1		T14	3
all_values[1]	auto[1]	auto[1]	758	1			T12	3		T13	1		T15	2
all_values[2]	auto[0]	auto[0]	2453332	1			T1	7589		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2839	1			T11	48		T12	73		T28	54
all_values[2]	auto[1]	auto[0]	67732	1			T12	8		T13	2		T15	7
all_values[2]	auto[1]	auto[1]	309	1			T12	4		T13	5		T14	2
all_values[3]	auto[0]	auto[0]	2435434	1			T1	7589		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	204	1			T12	5		T13	3		T14	1
all_values[3]	auto[1]	auto[0]	88362	1			T12	6		T13	1		T14	2
all_values[3]	auto[1]	auto[1]	212	1			T12	5		T13	1		T14	3
all_values[4]	auto[0]	auto[0]	2431238	1			T1	7589		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	219	1			T12	4		T38	2		T13	1
all_values[4]	auto[1]	auto[0]	92560	1			T12	9		T13	3		T14	1
all_values[4]	auto[1]	auto[1]	195	1			T12	2		T13	2		T14	1
all_values[5]	auto[0]	auto[0]	2403437	1			T1	7589		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	182	1			T12	4		T15	3		T16	2
all_values[5]	auto[1]	auto[0]	120413	1			T12	9		T13	4		T14	7
all_values[5]	auto[1]	auto[1]	180	1			T12	4		T13	2		T14	3
all_values[6]	auto[0]	auto[0]	2425851	1			T1	7589		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	216	1			T12	6		T13	2		T14	1
all_values[6]	auto[1]	auto[0]	97934	1			T12	4		T13	1		T14	6
all_values[6]	auto[1]	auto[1]	211	1			T12	6		T13	2		T14	4
all_values[7]	auto[0]	auto[0]	2430768	1			T1	7589		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	192	1			T12	3		T13	3		T14	2
all_values[7]	auto[1]	auto[0]	93034	1			T12	10		T14	6		T15	6
all_values[7]	auto[1]	auto[1]	218	1			T12	4		T13	1		T14	2