Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35217	1			T5	792		T6	60		T8	13
auto[SpiFlashAddrCfg]	7789	1			T2	1		T5	46		T6	18
auto[SpiFlashAddr3b]	9228	1			T3	2		T5	69		T6	19
auto[SpiFlashAddr4b]	7326	1			T2	1		T3	6		T5	45

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34558

1

T2

2

T3

8

T5

327

auto[1]

25002

1

T5

625

T6

52

T8

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31040

1

T2

2

T3

2

T5

501

auto[1]

28520

1

T3

6

T5

451

T6

58

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39837	1			T5	824		T6	78		T8	15
values[1]	1090	1			T5	4		T6	2		T9	1
values[2]	1442	1			T5	15		T6	2		T8	1
values[3]	1507	1			T3	2		T5	9		T6	3
values[4]	1465	1			T5	9		T6	3		T9	11
values[5]	1376	1			T5	10		T6	5		T8	1
values[6]	1459	1			T5	12		T6	1		T9	2
values[7]	1515	1			T5	6		T10	8		T11	10
values[8]	9869	1			T2	2		T3	6		T5	63

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28854

1

T3

8

T9

80

T10

10

auto[1]

30706

1

T2

2

T5

952

T6

115

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56246

1

T2

2

T3

8

T5

918

write

3314

1

T5

34

T6

10

T8

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19443

1

T2

1

T5

133

T6

46

valids[0x1]

40117

1

T2

1

T3

8

T5

819

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1673	1			T3	6		T5	12		T6	4
internal_process_ops[0x5a]	1597	1			T3	2		T5	11		T6	2
internal_process_ops[0x05]	20880	1			T5	685		T6	22		T8	3
internal_process_ops[0x35]	1598	1			T5	13		T6	5		T9	2
internal_process_ops[0x15]	1635	1			T5	9		T6	5		T8	2
internal_process_ops[0x03]	1045	1			T2	1		T5	4		T6	1
internal_process_ops[0x0b]	980	1			T5	2		T6	1		T9	2
internal_process_ops[0x3b]	961	1			T8	1		T9	4		T11	3
internal_process_ops[0x6b]	1061	1			T5	6		T6	1		T9	2
internal_process_ops[0xbb]	1047	1			T5	2		T6	1		T9	2
internal_process_ops[0xeb]	1033	1			T2	1		T5	1		T6	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57959

1

T2

2

T3

8

T5

937

auto[1]

1601

1

T5

15

T6

2

T8

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57129

1

T2

2

T3

8

T5

921

auto[1]

2431

1

T5

31

T6

7

T8

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9959

1

T9

17

T10

2

T12

74

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5195

1

T9

8

T12

25

T40

22

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2046

1

T9

7

T12

18

T40

19

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1810

1

T9

7

T12

13

T40

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2477

1

T3

2

T9

10

T10

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2189

1

T9

5

T12

25

T40

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1920

1

T3

6

T9

8

T12

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1695

1

T9

15

T12

17

T40

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

124

1

T41

1

T97

2

T166

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

70

1

T12

3

T40

1

T44

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T44

2

T42

2

T83

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T9

2

T12

2

T40

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

131

1

T12

1

T14

2

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T12

2

T40

3

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T12

4

T40

2

T41

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T12

1

T40

1

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

125

1

T167

4

T43

3

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T9

1

T12

2

T40

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T40

2

T14

3

T83

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T40

1

T14

2

T43

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

123

1

T12

2

T16

1

T168

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T12

3

T41

3

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

77

1

T12

2

T83

2

T95

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

79

1

T12

1

T40

2

T41

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11500

1

T5

247

T6

34

T8

11

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7714

1

T5

530

T6

25

T8

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1575

1

T2

1

T5

20

T6

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1515

1

T5

23

T6

8

T8

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1841

1

T5

20

T6

8

T8

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1904

1

T5

40

T6

11

T8

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1476

1

T2

1

T5

18

T6

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1430

1

T5

20

T6

5

T8

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

138

1

T5

10

T11

1

T28

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

108

1

T5

2

T23

2

T28

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T5

2

T6

1

T28

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

121

1

T5

1

T8

1

T169

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

134

1

T6

2

T11

2

T28

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T8

1

T11

1

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T5

1

T169

1

T170

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

108

1

T5

2

T6

1

T11

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T5

4

T23

1

T28

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T5

4

T11

2

T28

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

100

1

T11

3

T171

1

T172

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

107

1

T5

1

T28

3

T122

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T6

5

T11

3

T82

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

128

1

T5

2

T28

7

T122

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

99

1

T5

2

T28

1

T173

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

113

1

T5

3

T6

1

T11

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3779	1			T9	9		T12	40		T22	10
auto[0]	values[0]	valids[0x1]	14156	1			T9	23		T10	2		T12	94
auto[0]	values[1]	valids[0x1]	545	1			T9	1		T12	8		T40	2
auto[0]	values[2]	valids[0x0]	514	1			T9	1		T12	3		T40	4
auto[0]	values[2]	valids[0x1]	270	1			T12	1		T14	4		T41	3
auto[0]	values[3]	valids[0x0]	528	1			T9	1		T12	3		T40	2
auto[0]	values[3]	valids[0x1]	308	1			T3	2		T9	4		T12	3
auto[0]	values[4]	valids[0x0]	552	1			T9	8		T12	3		T40	6
auto[0]	values[4]	valids[0x1]	299	1			T9	3		T12	1		T40	3
auto[0]	values[5]	valids[0x0]	502	1			T9	3		T12	4		T40	4
auto[0]	values[5]	valids[0x1]	264	1			T9	1		T12	1		T40	1
auto[0]	values[6]	valids[0x0]	609	1			T9	1		T12	1		T40	3
auto[0]	values[6]	valids[0x1]	276	1			T9	1		T12	2		T40	2
auto[0]	values[7]	valids[0x0]	506	1			T12	13		T40	3		T41	2
auto[0]	values[7]	valids[0x1]	322	1			T10	8		T12	3		T40	1
auto[0]	values[8]	valids[0x0]	3396	1			T9	17		T12	22		T40	39
auto[0]	values[8]	valids[0x1]	2028	1			T3	6		T9	7		T12	29
auto[1]	values[0]	valids[0x0]	4171	1			T5	60		T6	27		T8	6
auto[1]	values[0]	valids[0x1]	17731	1			T5	764		T6	51		T8	9
auto[1]	values[1]	valids[0x1]	545	1			T5	4		T6	2		T11	3
auto[1]	values[2]	valids[0x0]	386	1			T5	10		T6	1		T8	1
auto[1]	values[2]	valids[0x1]	272	1			T5	5		T6	1		T11	4
auto[1]	values[3]	valids[0x0]	385	1			T5	2		T6	2		T11	6
auto[1]	values[3]	valids[0x1]	286	1			T5	7		T6	1		T11	2
auto[1]	values[4]	valids[0x0]	380	1			T5	3		T6	1		T11	3
auto[1]	values[4]	valids[0x1]	234	1			T5	6		T6	2		T23	2
auto[1]	values[5]	valids[0x0]	365	1			T5	4		T6	4		T8	1
auto[1]	values[5]	valids[0x1]	245	1			T5	6		T6	1		T11	2
auto[1]	values[6]	valids[0x0]	365	1			T5	10		T6	1		T11	6
auto[1]	values[6]	valids[0x1]	209	1			T5	2		T11	7		T23	2
auto[1]	values[7]	valids[0x0]	433	1			T5	5		T11	8		T28	2
auto[1]	values[7]	valids[0x1]	254	1			T5	1		T11	2		T23	1
auto[1]	values[8]	valids[0x0]	2572	1			T2	1		T5	39		T6	10
auto[1]	values[8]	valids[0x1]	1873	1			T2	1		T5	24		T6	11