Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3326565

1

T2

149

T3

1152

T5

12220

auto[1]

28517

1

T5

672

T6

15

T8

3

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

868376

1

T2

149

T3

1152

T5

120

auto[1]

2486706

1

T5

12772

T6

8038

T8

1760

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	624031	1			T2	117		T3	97		T5	2693
auto[524288:1048575]	400269	1			T5	974		T6	1		T9	19
auto[1048576:1572863]	356385	1			T2	14		T3	569		T5	3955
auto[1572864:2097151]	410178	1			T3	3		T5	103		T6	5456
auto[2097152:2621439]	407918	1			T5	1284		T6	2		T9	4
auto[2621440:3145727]	382300	1			T2	18		T5	93		T6	8
auto[3145728:3670015]	401575	1			T5	3171		T6	1812		T9	2010
auto[3670016:4194303]	372426	1			T3	483		T5	619		T10	595

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2522012

1

T2

15

T3

10

T5

12862

auto[1]

833070

1

T2

134

T3

1142

T5

30

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2927877

1

T2

149

T3

1152

T5

6174

auto[1]

427205

1

T5

6718

T6

4745

T11

1191

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	181636	1			T2	117		T3	97		T5	10
auto[0]	auto[0]	auto[0:524287]	auto[1]	378145	1			T5	1631		T6	3		T10	5370
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	105541	1			T5	16		T6	1		T9	14
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	233656	1			T5	776		T11	640		T12	257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	69608	1			T2	14		T3	569		T5	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232325	1			T5	520		T6	512		T8	1758
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	115134	1			T3	3		T5	7		T6	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	243105	1			T5	5		T6	2805		T11	224
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	103238	1			T5	4		T6	1		T9	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	251588	1			T5	1280		T11	773		T12	1299
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	94484	1			T2	18		T5	3		T9	21
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	244450	1			T5	2		T9	895		T11	1182
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	120667	1			T5	6		T9	42		T10	17788
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	219661	1			T5	826		T9	1963		T10	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	63374	1			T3	483		T5	14		T10	595
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	248020	1			T5	556		T11	1		T12	2463
auto[0]	auto[1]	auto[0:524287]	auto[0]	2321	1			T5	1		T6	5		T14	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	58037	1			T5	1003		T6	12		T40	2606
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1855	1			T11	1		T12	1		T28	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	55148	1			T5	2		T28	130		T122	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1014	1			T5	8		T6	1		T11	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	50799	1			T5	3321		T6	256		T11	1174
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	955	1			T6	4		T12	1		T122	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	46962	1			T6	2636		T12	128		T169	1234
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	703	1			T6	1		T11	1		T12	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49121	1			T12	2898		T28	855		T42	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1107	1			T5	5		T6	3		T11	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	38624	1			T5	3		T6	2		T28	521
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1649	1			T5	7		T6	6		T12	8
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	56620	1			T5	2206		T6	1804		T12	522
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1135	1			T12	5		T28	1		T232	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	55883	1			T12	3473		T122	256		T232	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	495	1			T5	2		T23	3		T28	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2686	1			T5	46		T40	2		T16	24
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	408	1			T5	8		T9	5		T12	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3146	1			T5	172		T28	4		T40	14
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	404	1			T5	3		T8	1		T9	22
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1743	1			T5	68		T8	2		T9	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	318	1			T5	5		T11	1		T12	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3154	1			T5	86		T11	6		T41	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	426	1			T12	2		T28	6		T41	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2170	1			T12	1		T28	5		T16	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	401	1			T5	2		T9	9		T11	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2745	1			T5	14		T9	182		T11	29
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	370	1			T5	2		T9	5		T11	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1911	1			T5	53		T11	10		T40	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	414	1			T5	2		T11	1		T12	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2454	1			T5	47		T11	18		T41	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	112	1			T6	1		T41	1		T83	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	599	1			T6	1		T83	9		T21	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	82	1			T28	2		T83	1		T196	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	433	1			T28	1		T83	34		T78	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	60	1			T5	1		T11	1		T172	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	432	1			T5	26		T11	11		T172	27
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	110	1			T6	3		T172	1		T170	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	440	1			T6	5		T172	30		T170	22
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	83	1			T173	1		T170	1		T233	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	589	1			T173	30		T170	10		T233	20
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	71	1			T5	3		T6	2		T28	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	418	1			T5	61		T6	1		T28	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	80	1			T5	3		T6	1		T12	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	617	1			T5	68		T6	1		T12	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	121	1			T12	2		T232	1		T83	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1025	1			T12	1		T232	2		T83	41

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2077853	1			T2	15		T3	10		T5	5652
auto[0]	auto[0]	auto[1]	826779	1			T2	134		T3	1142		T5	12
auto[0]	auto[1]	auto[0]	416382	1			T5	6551		T6	4730		T11	1179
auto[0]	auto[1]	auto[1]	5551	1			T5	5		T83	3		T173	1
auto[1]	auto[0]	auto[0]	22645	1			T5	500		T8	3		T9	226
auto[1]	auto[0]	auto[1]	600	1			T5	10		T9	6		T23	2
auto[1]	auto[1]	auto[0]	5132	1			T5	159		T6	15		T11	12
auto[1]	auto[1]	auto[1]	140	1			T5	3		T28	1		T44	1