Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2524212	1			T1	7589		T2	1		T3	1
all_pins[1]	2524212	1			T1	7589		T2	1		T3	1
all_pins[2]	2524212	1			T1	7589		T2	1		T3	1
all_pins[3]	2524212	1			T1	7589		T2	1		T3	1
all_pins[4]	2524212	1			T1	7589		T2	1		T3	1
all_pins[5]	2524212	1			T1	7589		T2	1		T3	1
all_pins[6]	2524212	1			T1	7589		T2	1		T3	1
all_pins[7]	2524212	1			T1	7589		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20095659	1			T1	60712		T2	8		T3	8
values[0x1]	98037	1			T12	31		T13	14		T14	18
transitions[0x0=>0x1]	96396	1			T12	23		T13	9		T14	13
transitions[0x1=>0x0]	96414	1			T12	23		T13	9		T14	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2523172	1			T1	7589		T2	1		T3	1
all_pins[0]	values[0x1]	1040	1			T12	3		T14	3		T15	4
all_pins[0]	transitions[0x0=>0x1]	704	1			T12	3		T14	3		T15	4
all_pins[0]	transitions[0x1=>0x0]	465	1			T12	3		T13	1		T15	2
all_pins[1]	values[0x0]	2523411	1			T1	7589		T2	1		T3	1
all_pins[1]	values[0x1]	801	1			T12	3		T13	1		T15	2
all_pins[1]	transitions[0x0=>0x1]	688	1			T12	2		T15	2		T16	4
all_pins[1]	transitions[0x1=>0x0]	208	1			T12	3		T13	4		T14	2
all_pins[2]	values[0x0]	2523891	1			T1	7589		T2	1		T3	1
all_pins[2]	values[0x1]	321	1			T12	4		T13	5		T14	2
all_pins[2]	transitions[0x0=>0x1]	257	1			T12	1		T13	4		T14	1
all_pins[2]	transitions[0x1=>0x0]	148	1			T12	2		T14	2		T16	4
all_pins[3]	values[0x0]	2524000	1			T1	7589		T2	1		T3	1
all_pins[3]	values[0x1]	212	1			T12	5		T13	1		T14	3
all_pins[3]	transitions[0x0=>0x1]	172	1			T12	4		T13	1		T14	3
all_pins[3]	transitions[0x1=>0x0]	155	1			T12	1		T13	2		T14	1
all_pins[4]	values[0x0]	2524017	1			T1	7589		T2	1		T3	1
all_pins[4]	values[0x1]	195	1			T12	2		T13	2		T14	1
all_pins[4]	transitions[0x0=>0x1]	157	1			T12	2		T14	1		T15	2
all_pins[4]	transitions[0x1=>0x0]	1408	1			T12	4		T14	3		T15	2
all_pins[5]	values[0x0]	2522766	1			T1	7589		T2	1		T3	1
all_pins[5]	values[0x1]	1446	1			T12	4		T13	2		T14	3
all_pins[5]	transitions[0x0=>0x1]	501	1			T12	3		T13	1		T14	2
all_pins[5]	transitions[0x1=>0x0]	92859	1			T12	5		T13	1		T14	3
all_pins[6]	values[0x0]	2430408	1			T1	7589		T2	1		T3	1
all_pins[6]	values[0x1]	93804	1			T12	6		T13	2		T14	4
all_pins[6]	transitions[0x0=>0x1]	93755	1			T12	4		T13	2		T14	2
all_pins[6]	transitions[0x1=>0x0]	169	1			T12	2		T13	1		T15	1
all_pins[7]	values[0x0]	2523994	1			T1	7589		T2	1		T3	1
all_pins[7]	values[0x1]	218	1			T12	4		T13	1		T14	2
all_pins[7]	transitions[0x0=>0x1]	162	1			T12	4		T13	1		T14	1
all_pins[7]	transitions[0x1=>0x0]	1002	1			T12	3		T14	2		T15	3