Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17241

1

T3

8

T9

43

T10

10

auto[1]

11613

1

T9

37

T12

90

T40

71

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3518	1			T9	40		T10	10		T12	70
values[1]	3588	1			T3	8		T12	24		T41	21
values[2]	2959	1			T9	20		T105	6		T14	23
values[3]	4162	1			T22	10		T40	46		T14	20
values[4]	3825	1			T9	20		T40	20		T14	22
values[5]	3377	1			T12	115		T40	21		T121	12
values[6]	3263	1			T40	37		T43	20		T89	6
values[7]	4162	1			T12	22		T40	72		T14	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4095	1			T9	20		T12	28		T40	20
values[1]	3614	1			T9	20		T40	26		T121	12
values[2]	3592	1			T9	20		T12	43		T40	21
values[3]	3153	1			T12	43		T14	45		T41	29
values[4]	3710	1			T12	50		T40	40		T14	20
values[5]	3765	1			T10	10		T40	20		T14	21
values[6]	3302	1			T9	20		T12	42		T22	10
values[7]	3623	1			T3	8		T12	25		T40	69

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	280	1			T9	8		T99	20		T14	11
auto[0]	values[0]	values[1]	266	1			T43	11		T208	13		T222	11
auto[0]	values[0]	values[2]	335	1			T12	15		T79	23		T186	14
auto[0]	values[0]	values[3]	254	1			T12	13		T230	13		T234	12
auto[0]	values[0]	values[4]	397	1			T12	13		T79	15		T192	12
auto[0]	values[0]	values[5]	166	1			T10	10		T81	4		T198	19
auto[0]	values[0]	values[6]	202	1			T9	8		T235	11		T220	15
auto[0]	values[0]	values[7]	357	1			T42	10		T196	13		T199	17
auto[0]	values[1]	values[0]	300	1			T42	11		T208	9		T203	33
auto[0]	values[1]	values[1]	188	1			T20	14		T222	14		T92	11
auto[0]	values[1]	values[2]	173	1			T225	12		T220	14		T206	12
auto[0]	values[1]	values[3]	390	1			T95	11		T188	9		T203	17
auto[0]	values[1]	values[4]	142	1			T12	18		T16	8		T236	2
auto[0]	values[1]	values[5]	350	1			T41	9		T83	64		T207	8
auto[0]	values[1]	values[6]	328	1			T42	10		T192	10		T222	29
auto[0]	values[1]	values[7]	161	1			T3	8		T227	16		T203	17
auto[0]	values[2]	values[0]	274	1			T192	9		T237	18		T225	25
auto[0]	values[2]	values[1]	95	1			T184	10		T92	15		T238	10
auto[0]	values[2]	values[2]	239	1			T9	13		T168	26		T90	14
auto[0]	values[2]	values[3]	89	1			T14	16		T138	10		T239	2
auto[0]	values[2]	values[4]	297	1			T42	6		T196	9		T76	20
auto[0]	values[2]	values[5]	234	1			T46	15		T42	8		T217	13
auto[0]	values[2]	values[6]	176	1			T105	6		T46	10		T198	19
auto[0]	values[2]	values[7]	224	1			T97	20		T240	4		T79	24
auto[0]	values[3]	values[0]	245	1			T20	11		T203	9		T186	11
auto[0]	values[3]	values[1]	295	1			T40	24		T46	11		T241	2
auto[0]	values[3]	values[2]	223	1			T14	12		T46	31		T42	5
auto[0]	values[3]	values[3]	292	1			T166	12		T226	6		T20	12
auto[0]	values[3]	values[4]	180	1			T16	9		T242	12		T216	13
auto[0]	values[3]	values[5]	475	1			T40	12		T41	15		T123	4
auto[0]	values[3]	values[6]	403	1			T22	10		T42	12		T95	13
auto[0]	values[3]	values[7]	270	1			T42	11		T95	8		T186	28
auto[0]	values[4]	values[0]	446	1			T40	14		T198	37		T199	13
auto[0]	values[4]	values[1]	255	1			T9	14		T44	14		T91	10
auto[0]	values[4]	values[2]	277	1			T95	11		T196	29		T208	23
auto[0]	values[4]	values[3]	293	1			T14	11		T41	20		T46	10
auto[0]	values[4]	values[4]	383	1			T41	12		T243	10		T20	12
auto[0]	values[4]	values[5]	257	1			T198	18		T208	15		T244	10
auto[0]	values[4]	values[6]	182	1			T95	10		T245	6		T20	7
auto[0]	values[4]	values[7]	117	1			T222	10		T159	16		T219	15
auto[0]	values[5]	values[0]	229	1			T12	20		T167	18		T14	9
auto[0]	values[5]	values[1]	371	1			T121	12		T14	10		T44	13
auto[0]	values[5]	values[2]	288	1			T12	15		T40	12		T43	15
auto[0]	values[5]	values[3]	210	1			T44	11		T223	14		T192	8
auto[0]	values[5]	values[4]	172	1			T16	12		T46	15		T191	10
auto[0]	values[5]	values[5]	268	1			T14	10		T95	6		T192	13
auto[0]	values[5]	values[6]	216	1			T12	20		T186	16		T230	15
auto[0]	values[5]	values[7]	332	1			T12	7		T43	11		T44	13
auto[0]	values[6]	values[0]	345	1			T83	126		T184	15		T246	20
auto[0]	values[6]	values[1]	309	1			T20	10		T208	33		T217	19
auto[0]	values[6]	values[2]	213	1			T205	16		T83	14		T192	7
auto[0]	values[6]	values[3]	160	1			T43	11		T83	10		T186	10
auto[0]	values[6]	values[4]	315	1			T42	12		T217	15		T247	13
auto[0]	values[6]	values[5]	149	1			T208	21		T217	10		T184	17
auto[0]	values[6]	values[6]	319	1			T89	6		T96	20		T212	16
auto[0]	values[6]	values[7]	308	1			T40	13		T222	11		T184	14
auto[0]	values[7]	values[0]	377	1			T41	8		T46	13		T197	134
auto[0]	values[7]	values[1]	328	1			T41	13		T46	12		T95	9
auto[0]	values[7]	values[2]	392	1			T83	10		T188	14		T186	11
auto[0]	values[7]	values[3]	167	1			T12	20		T196	31		T184	15
auto[0]	values[7]	values[4]	344	1			T40	28		T14	11		T83	53
auto[0]	values[7]	values[5]	224	1			T95	8		T196	9		T188	10
auto[0]	values[7]	values[6]	197	1			T192	17		T199	27		T217	16
auto[0]	values[7]	values[7]	498	1			T40	22		T83	77		T95	18
auto[1]	values[0]	values[0]	242	1			T9	12		T14	10		T198	4
auto[1]	values[0]	values[1]	174	1			T43	9		T208	7		T222	11
auto[1]	values[0]	values[2]	156	1			T12	8		T79	17		T186	6
auto[1]	values[0]	values[3]	161	1			T12	8		T230	7		T214	10
auto[1]	values[0]	values[4]	128	1			T12	13		T79	5		T192	8
auto[1]	values[0]	values[5]	90	1			T198	9		T48	3		T215	11
auto[1]	values[0]	values[6]	169	1			T9	12		T235	18		T220	5
auto[1]	values[0]	values[7]	141	1			T42	10		T196	7		T199	28
auto[1]	values[1]	values[0]	252	1			T42	9		T208	20		T203	9
auto[1]	values[1]	values[1]	110	1			T20	8		T222	12		T92	9
auto[1]	values[1]	values[2]	117	1			T225	8		T220	6		T206	21
auto[1]	values[1]	values[3]	334	1			T95	9		T188	11		T203	16
auto[1]	values[1]	values[4]	158	1			T12	6		T16	44		T248	11
auto[1]	values[1]	values[5]	275	1			T41	12		T83	10		T203	7
auto[1]	values[1]	values[6]	193	1			T42	10		T192	10		T222	39
auto[1]	values[1]	values[7]	117	1			T203	10		T201	8		T206	14
auto[1]	values[2]	values[0]	221	1			T192	11		T225	7		T206	8
auto[1]	values[2]	values[1]	55	1			T184	10		T92	5		T249	11
auto[1]	values[2]	values[2]	163	1			T9	7		T198	11		T208	8
auto[1]	values[2]	values[3]	125	1			T14	7		T250	2		T138	17
auto[1]	values[2]	values[4]	292	1			T42	14		T196	13		T203	11
auto[1]	values[2]	values[5]	174	1			T46	6		T42	12		T217	7
auto[1]	values[2]	values[6]	143	1			T46	10		T198	8		T217	6
auto[1]	values[2]	values[7]	158	1			T79	16		T208	8		T216	35
auto[1]	values[3]	values[0]	122	1			T251	6		T20	10		T203	11
auto[1]	values[3]	values[1]	290	1			T40	2		T46	9		T203	8
auto[1]	values[3]	values[2]	243	1			T14	8		T46	4		T42	15
auto[1]	values[3]	values[3]	136	1			T20	9		T186	6		T199	5
auto[1]	values[3]	values[4]	209	1			T16	22		T252	10		T216	40
auto[1]	values[3]	values[5]	263	1			T40	8		T41	8		T83	6
auto[1]	values[3]	values[6]	261	1			T42	8		T95	7		T253	24
auto[1]	values[3]	values[7]	255	1			T254	2		T42	9		T95	12
auto[1]	values[4]	values[0]	224	1			T40	6		T198	4		T199	7
auto[1]	values[4]	values[1]	193	1			T9	6		T44	6		T20	10
auto[1]	values[4]	values[2]	239	1			T98	8		T95	9		T196	10
auto[1]	values[4]	values[3]	149	1			T14	11		T41	9		T46	15
auto[1]	values[4]	values[4]	239	1			T41	11		T20	10		T203	11
auto[1]	values[4]	values[5]	298	1			T198	34		T208	8		T142	12
auto[1]	values[4]	values[6]	215	1			T255	4		T95	10		T20	13
auto[1]	values[4]	values[7]	58	1			T222	10		T159	6		T219	5
auto[1]	values[5]	values[0]	131	1			T12	8		T14	11		T196	22
auto[1]	values[5]	values[1]	118	1			T14	10		T44	7		T199	6
auto[1]	values[5]	values[2]	187	1			T12	5		T40	9		T43	5
auto[1]	values[5]	values[3]	160	1			T44	9		T192	12		T222	5
auto[1]	values[5]	values[4]	168	1			T16	8		T46	7		T20	2
auto[1]	values[5]	values[5]	196	1			T14	11		T95	14		T192	7
auto[1]	values[5]	values[6]	92	1			T12	22		T186	4		T230	5
auto[1]	values[5]	values[7]	239	1			T12	18		T43	11		T44	7
auto[1]	values[6]	values[0]	157	1			T83	25		T195	24		T184	5
auto[1]	values[6]	values[1]	164	1			T20	13		T256	12		T208	9
auto[1]	values[6]	values[2]	146	1			T83	6		T192	13		T257	7
auto[1]	values[6]	values[3]	153	1			T43	9		T83	19		T186	10
auto[1]	values[6]	values[4]	79	1			T42	8		T217	11		T247	8
auto[1]	values[6]	values[5]	161	1			T208	5		T217	10		T184	3
auto[1]	values[6]	values[6]	93	1			T45	8		T203	12		T192	13
auto[1]	values[6]	values[7]	192	1			T40	24		T222	33		T184	6
auto[1]	values[7]	values[0]	250	1			T41	16		T46	7		T258	6
auto[1]	values[7]	values[1]	403	1			T41	8		T46	8		T95	11
auto[1]	values[7]	values[2]	201	1			T83	10		T188	12		T186	9
auto[1]	values[7]	values[3]	80	1			T12	2		T196	1		T184	5
auto[1]	values[7]	values[4]	207	1			T40	12		T14	9		T83	63
auto[1]	values[7]	values[5]	185	1			T95	12		T196	39		T188	15
auto[1]	values[7]	values[6]	113	1			T192	3		T199	13		T217	10
auto[1]	values[7]	values[7]	196	1			T40	10		T83	12		T95	22