Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	404	1			T9	2		T12	4		T40	3
auto[ReadAddrCrossIntoMailbox]	283	1			T9	1		T12	2		T40	4
auto[ReadAddrCrossOutOfMailbox]	291	1			T9	1		T12	3		T40	6
auto[ReadAddrCrossAllMailbox]	217	1			T12	3		T40	1		T14	2
auto[ReadAddrOutsideMailbox]	3450	1			T9	13		T12	33		T40	18

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2315

1

T9

7

T12

20

T40

14

auto[1]

2330

1

T9

10

T12

25

T40

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	784	1			T9	4		T12	7		T40	6
read_ops[0x0b]	759	1			T9	2		T12	10		T40	5
read_ops[0x3b]	741	1			T9	4		T12	7		T40	1
read_ops[0x6b]	799	1			T9	2		T12	4		T40	9
read_ops[0xbb]	794	1			T9	2		T12	11		T40	6
read_ops[0xeb]	768	1			T9	3		T12	6		T40	5

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T42	2		T188	1		T208	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T46	1		T42	1		T79	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T79	1		T208	1		T203	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T95	1		T196	1		T79	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T40	1		T188	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T9	1		T83	1		T199	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T259	1		T217	1		T220	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T14	1		T192	1		T186	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T12	2		T40	5		T14	7
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T9	3		T12	5		T14	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T46	1		T223	1		T20	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T12	2		T40	1		T223	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T12	1		T79	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T14	1		T95	1		T196	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T41	1		T43	1		T95	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T12	1		T40	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T12	1		T225	1		T230	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T196	1		T198	1		T208	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	303	1			T9	1		T12	1		T40	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T9	1		T12	4		T40	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T9	2		T46	1		T198	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T196	1		T197	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T40	1		T95	2		T79	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T83	1		T198	1		T208	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T186	1		T259	1		T199	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T196	2		T79	1		T259	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T46	1		T42	1		T260	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T260	1		T92	1		T235	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T12	6		T99	2		T41	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T9	2		T12	1		T99	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T41	1		T42	1		T83	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T40	1		T83	1		T95	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T83	1		T217	2		T201	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T40	1		T95	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T14	1		T41	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T12	1		T40	2		T208	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T46	1		T42	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T12	1		T40	1		T260	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	290	1			T9	2		T40	2		T14	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T12	2		T40	2		T43	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	49	1			T12	2		T42	2		T20	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T83	1		T95	1		T79	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T12	1		T40	1		T95	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T46	1		T188	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T12	1		T41	1		T95	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T40	2		T83	1		T95	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T83	1		T192	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T196	1		T186	1		T259	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T12	3		T40	3		T14	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	288	1			T9	2		T12	4		T14	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T46	1		T196	1		T197	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T40	1		T208	1		T222	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T14	1		T20	1		T79	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T9	1		T40	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T95	1		T260	1		T142	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T42	3		T196	1		T79	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T14	1		T41	2		T44	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T12	1		T230	1		T145	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T9	2		T12	2		T99	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T12	3		T40	3		T99	1