Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3809	1			T10	10		T12	46		T14	40
values[1]	3755	1			T12	74		T14	42		T41	21
values[2]	3337	1			T9	40		T22	10		T40	32
values[3]	2819	1			T12	46		T40	40		T43	20
values[4]	4085	1			T9	40		T105	6		T40	47
values[5]	3580	1			T12	42		T14	21		T41	45
values[6]	3411	1			T3	8		T40	20		T14	21
values[7]	4058	1			T12	23		T40	57		T121	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3715	1			T3	8		T9	20		T12	21
values[1]	3806	1			T12	21		T40	20		T121	12
values[2]	4205	1			T9	20		T12	26		T22	10
values[3]	3986	1			T10	10		T12	53		T99	20
values[4]	3081	1			T14	65		T123	4		T16	52
values[5]	3492	1			T9	20		T12	43		T40	115
values[6]	3262	1			T12	43		T40	20		T14	41
values[7]	3307	1			T9	20		T12	24		T40	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28159

1

T3

8

T9

77

T10

10

auto[1]

695

1

T9

3

T12

14

T40

12

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	541	1			T12	20		T42	40		T79	20
auto[0]	values[0]	values[1]	530	1			T44	20		T16	20		T83	20
auto[0]	values[0]	values[2]	512	1			T14	20		T44	18		T260	14
auto[0]	values[0]	values[3]	695	1			T10	10		T12	25		T14	20
auto[0]	values[0]	values[4]	294	1			T42	20		T258	6		T20	21
auto[0]	values[0]	values[5]	481	1			T43	20		T192	37		T261	8
auto[0]	values[0]	values[6]	291	1			T83	28		T191	10		T79	19
auto[0]	values[0]	values[7]	388	1			T196	27		T262	2		T192	20
auto[0]	values[1]	values[0]	466	1			T46	59		T83	29		T95	20
auto[0]	values[1]	values[1]	341	1			T46	22		T42	20		T20	19
auto[0]	values[1]	values[2]	667	1			T12	23		T95	18		T79	20
auto[0]	values[1]	values[3]	483	1			T12	28		T46	17		T240	4
auto[0]	values[1]	values[4]	472	1			T14	40		T192	19		T213	10
auto[0]	values[1]	values[5]	584	1			T42	19		T196	20		T79	19
auto[0]	values[1]	values[6]	328	1			T12	18		T222	28		T199	45
auto[0]	values[1]	values[7]	310	1			T41	21		T186	20		T235	29
auto[0]	values[2]	values[0]	280	1			T226	6		T208	20		T246	20
auto[0]	values[2]	values[1]	391	1			T167	18		T205	16		T95	20
auto[0]	values[2]	values[2]	363	1			T22	10		T41	22		T90	14
auto[0]	values[2]	values[3]	555	1			T203	23		T138	44		T231	46
auto[0]	values[2]	values[4]	419	1			T123	4		T255	2		T196	51
auto[0]	values[2]	values[5]	331	1			T9	20		T40	29		T41	22
auto[0]	values[2]	values[6]	451	1			T14	20		T250	2		T16	29
auto[0]	values[2]	values[7]	479	1			T9	19		T97	20		T186	20
auto[0]	values[3]	values[0]	220	1			T43	20		T20	43		T184	17
auto[0]	values[3]	values[1]	642	1			T40	18		T46	24		T197	125
auto[0]	values[3]	values[2]	235	1			T20	21		T236	2		T192	20
auto[0]	values[3]	values[3]	322	1			T252	10		T186	38		T246	20
auto[0]	values[3]	values[4]	191	1			T16	49		T245	6		T79	20
auto[0]	values[3]	values[5]	511	1			T12	20		T166	12		T46	18
auto[0]	values[3]	values[6]	298	1			T40	20		T95	20		T207	8
auto[0]	values[3]	values[7]	333	1			T12	23		T45	6		T83	30
auto[0]	values[4]	values[0]	739	1			T9	19		T40	20		T196	128
auto[0]	values[4]	values[1]	499	1			T243	10		T203	20		T225	31
auto[0]	values[4]	values[2]	466	1			T9	19		T105	6		T83	130
auto[0]	values[4]	values[3]	673	1			T99	20		T96	20		T203	26
auto[0]	values[4]	values[4]	473	1			T14	23		T42	20		T83	94
auto[0]	values[4]	values[5]	238	1			T40	22		T254	2		T246	20
auto[0]	values[4]	values[6]	469	1			T95	20		T257	20		T235	19
auto[0]	values[4]	values[7]	418	1			T20	20		T186	20		T263	10
auto[0]	values[5]	values[0]	379	1			T43	41		T44	20		T42	20
auto[0]	values[5]	values[1]	439	1			T12	20		T76	20		T203	20
auto[0]	values[5]	values[2]	751	1			T41	18		T83	40		T197	20
auto[0]	values[5]	values[3]	352	1			T242	12		T217	20		T184	18
auto[0]	values[5]	values[4]	422	1			T95	20		T221	43		T184	40
auto[0]	values[5]	values[5]	270	1			T12	20		T14	19		T159	20
auto[0]	values[5]	values[6]	387	1			T212	16		T198	29		T216	40
auto[0]	values[5]	values[7]	489	1			T41	24		T91	10		T95	57
auto[0]	values[6]	values[0]	425	1			T3	8		T227	16		T222	20
auto[0]	values[6]	values[1]	398	1			T95	20		T208	27		T199	20
auto[0]	values[6]	values[2]	362	1			T89	6		T198	27		T208	26
auto[0]	values[6]	values[3]	408	1			T256	12		T188	20		T264	14
auto[0]	values[6]	values[4]	449	1			T223	14		T95	19		T20	21
auto[0]	values[6]	values[5]	601	1			T40	20		T192	18		T199	20
auto[0]	values[6]	values[6]	360	1			T14	21		T98	8		T251	6
auto[0]	values[6]	values[7]	330	1			T203	33		T201	20		T230	18
auto[0]	values[7]	values[0]	553	1			T44	20		T241	2		T198	58
auto[0]	values[7]	values[1]	487	1			T121	12		T83	116		T253	24
auto[0]	values[7]	values[2]	743	1			T192	19		T184	20		T265	25
auto[0]	values[7]	values[3]	410	1			T42	19		T217	20		T92	16
auto[0]	values[7]	values[4]	294	1			T83	20		T208	20		T192	20
auto[0]	values[7]	values[5]	385	1			T40	36		T186	18		T266	14
auto[0]	values[7]	values[6]	603	1			T12	20		T41	25		T46	35
auto[0]	values[7]	values[7]	483	1			T40	19		T95	19		T267	6
auto[1]	values[0]	values[0]	15	1			T12	1		T203	1		T202	3
auto[1]	values[0]	values[1]	5	1			T215	1		T248	1		T268	3
auto[1]	values[0]	values[2]	13	1			T44	2		T192	2		T230	3
auto[1]	values[0]	values[3]	11	1			T188	1		T138	1		T146	1
auto[1]	values[0]	values[4]	8	1			T20	1		T188	2		T199	1
auto[1]	values[0]	values[5]	11	1			T192	3		T220	1		T249	2
auto[1]	values[0]	values[6]	7	1			T83	1		T79	1		T208	1
auto[1]	values[0]	values[7]	7	1			T92	1		T269	3		T270	2
auto[1]	values[1]	values[0]	11	1			T46	2		T83	1		T49	1
auto[1]	values[1]	values[1]	9	1			T20	1		T186	1		T246	2
auto[1]	values[1]	values[2]	21	1			T12	3		T95	2		T198	2
auto[1]	values[1]	values[3]	14	1			T46	3		T271	4		T248	1
auto[1]	values[1]	values[4]	10	1			T14	2		T192	1		T272	4
auto[1]	values[1]	values[5]	22	1			T42	1		T79	1		T192	3
auto[1]	values[1]	values[6]	14	1			T12	2		T206	3		T273	2
auto[1]	values[1]	values[7]	3	1			T220	1		T215	2		-	-
auto[1]	values[2]	values[0]	3	1			T35	3		-	-		-	-
auto[1]	values[2]	values[1]	12	1			T92	3		T274	8		T275	1
auto[1]	values[2]	values[2]	4	1			T41	1		T194	2		T276	1
auto[1]	values[2]	values[3]	9	1			T203	2		T277	1		T50	1
auto[1]	values[2]	values[4]	8	1			T255	2		T196	1		T208	1
auto[1]	values[2]	values[5]	9	1			T40	3		T41	1		T217	2
auto[1]	values[2]	values[6]	13	1			T16	2		T42	1		T184	6
auto[1]	values[2]	values[7]	10	1			T9	1		T199	1		T159	1
auto[1]	values[3]	values[0]	9	1			T20	1		T184	3		T278	3
auto[1]	values[3]	values[1]	10	1			T40	2		T46	1		T197	1
auto[1]	values[3]	values[2]	9	1			T20	1		T217	1		T159	5
auto[1]	values[3]	values[3]	4	1			T186	2		T142	2		-	-
auto[1]	values[3]	values[4]	8	1			T16	3		T279	4		T218	1
auto[1]	values[3]	values[5]	11	1			T12	2		T46	2		T222	1
auto[1]	values[3]	values[6]	4	1			T186	1		T199	1		T246	1
auto[1]	values[3]	values[7]	12	1			T12	1		T45	2		T214	1
auto[1]	values[4]	values[0]	33	1			T9	1		T40	1		T196	4
auto[1]	values[4]	values[1]	8	1			T225	1		T249	1		T280	1
auto[1]	values[4]	values[2]	18	1			T9	1		T83	4		T199	2
auto[1]	values[4]	values[3]	12	1			T203	1		T225	1		T194	4
auto[1]	values[4]	values[4]	14	1			T220	2		T281	2		T282	10
auto[1]	values[4]	values[5]	9	1			T40	4		T283	3		T284	1
auto[1]	values[4]	values[6]	5	1			T235	1		T249	1		T280	1
auto[1]	values[4]	values[7]	11	1			T219	2		T285	2		T210	5
auto[1]	values[5]	values[0]	11	1			T43	1		T201	1		T219	2
auto[1]	values[5]	values[1]	11	1			T12	1		T217	3		T220	1
auto[1]	values[5]	values[2]	24	1			T41	3		T83	1		T198	1
auto[1]	values[5]	values[3]	7	1			T217	1		T184	2		T194	3
auto[1]	values[5]	values[4]	6	1			T221	2		T138	3		T286	1
auto[1]	values[5]	values[5]	10	1			T12	1		T14	2		T142	1
auto[1]	values[5]	values[6]	8	1			T184	5		T49	1		T287	2
auto[1]	values[5]	values[7]	14	1			T95	3		T196	1		T203	5
auto[1]	values[6]	values[0]	15	1			T222	2		T217	1		T92	1
auto[1]	values[6]	values[1]	10	1			T208	2		T216	2		T215	1
auto[1]	values[6]	values[2]	5	1			T203	1		T50	1		T288	2
auto[1]	values[6]	values[3]	14	1			T217	1		T206	1		T289	1
auto[1]	values[6]	values[4]	5	1			T95	1		T145	1		T229	1
auto[1]	values[6]	values[5]	12	1			T192	2		T216	2		T269	2
auto[1]	values[6]	values[6]	12	1			T80	2		T220	5		T290	1
auto[1]	values[6]	values[7]	5	1			T230	2		T291	2		T292	1
auto[1]	values[7]	values[0]	15	1			T198	3		T208	1		T225	2
auto[1]	values[7]	values[1]	14	1			T83	5		T145	3		T293	2
auto[1]	values[7]	values[2]	12	1			T192	1		T230	1		T206	1
auto[1]	values[7]	values[3]	17	1			T42	1		T92	4		T294	1
auto[1]	values[7]	values[4]	8	1			T186	1		T199	2		T202	1
auto[1]	values[7]	values[5]	7	1			T40	1		T186	2		T295	1
auto[1]	values[7]	values[6]	12	1			T12	3		T41	4		T222	2
auto[1]	values[7]	values[7]	15	1			T40	1		T95	1		T296	4