Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1787

1

T1

7

T4

7

T6

7

auto[1]

1907

1

T1

4

T4

6

T6

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1923

1

T1

8

T6

5

T8

13

auto[1]

1771

1

T1

3

T4

13

T6

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2943

1

T1

9

T4

13

T6

6

auto[1]

751

1

T1

2

T6

4

T8

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	730	1			T4	2		T6	3		T8	4
valid[1]	752	1			T4	6		T6	1		T8	1
valid[2]	711	1			T1	4		T4	2		T6	2
valid[3]	769	1			T1	3		T4	2		T6	3
valid[4]	732	1			T1	4		T4	1		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	111	1			T6	1		T11	1		T28	2
auto[0]	auto[0]	valid[0]	auto[1]	185	1			T4	1		T6	1		T8	1
auto[0]	auto[0]	valid[1]	auto[0]	104	1			T11	1		T12	1		T28	1
auto[0]	auto[0]	valid[1]	auto[1]	179	1			T4	4		T12	3		T24	1
auto[0]	auto[0]	valid[2]	auto[0]	117	1			T1	3		T11	1		T31	1
auto[0]	auto[0]	valid[2]	auto[1]	143	1			T4	1		T11	1		T302	1
auto[0]	auto[0]	valid[3]	auto[0]	128	1			T8	1		T11	1		T28	2
auto[0]	auto[0]	valid[3]	auto[1]	185	1			T1	3		T6	1		T8	1
auto[0]	auto[0]	valid[4]	auto[0]	99	1			T8	2		T12	1		T40	3
auto[0]	auto[0]	valid[4]	auto[1]	170	1			T4	1		T6	1		T8	1
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T8	1		T12	2		T28	1
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T4	1		T6	1		T12	1
auto[0]	auto[1]	valid[1]	auto[0]	120	1			T28	1		T40	1		T61	1
auto[0]	auto[1]	valid[1]	auto[1]	186	1			T4	2		T12	1		T24	2
auto[0]	auto[1]	valid[2]	auto[0]	134	1			T11	2		T31	1		T12	3
auto[0]	auto[1]	valid[2]	auto[1]	176	1			T4	1		T8	1		T12	1
auto[0]	auto[1]	valid[3]	auto[0]	116	1			T8	2		T11	1		T12	1
auto[0]	auto[1]	valid[3]	auto[1]	191	1			T4	2		T6	1		T8	1
auto[0]	auto[1]	valid[4]	auto[0]	124	1			T1	3		T8	1		T31	1
auto[0]	auto[1]	valid[4]	auto[1]	185	1			T8	1		T11	1		T12	1
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T8	1		T11	1		T12	5
auto[1]	auto[0]	valid[1]	auto[0]	80	1			T6	1		T11	3		T12	1
auto[1]	auto[0]	valid[2]	auto[0]	66	1			T1	1		T6	1		T8	1
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T6	1		T11	2		T12	1
auto[1]	auto[0]	valid[4]	auto[0]	70	1			T61	1		T41	1		T43	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T8	1		T12	1		T28	2
auto[1]	auto[1]	valid[1]	auto[0]	83	1			T8	1		T11	2		T12	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T6	1		T61	1		T82	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T8	1		T11	1		T12	3
auto[1]	auto[1]	valid[4]	auto[0]	84	1			T1	1		T8	1		T11	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal