Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48897

1

T1

231

T6

161

T8

329

auto[1]

19578

1

T1

56

T4

13

T6

84

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50322

1

T1

206

T4

13

T6

161

auto[1]

18153

1

T1

81

T6

84

T8

128

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35500	1			T1	144		T4	13		T6	127
others[1]	5684	1			T1	14		T6	23		T8	31
others[2]	5777	1			T1	29		T6	21		T8	36
others[3]	6456	1			T1	32		T6	23		T8	26
interest[1]	3870	1			T1	18		T6	15		T8	26
interest[4]	23243	1			T1	102		T4	13		T6	81
interest[64]	11188	1			T1	50		T6	36		T8	61

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15816	1			T1	67		T6	34		T8	109
auto[0]	auto[0]	others[1]	2523	1			T1	9		T6	6		T8	15
auto[0]	auto[0]	others[2]	2624	1			T1	18		T6	9		T8	17
auto[0]	auto[0]	others[3]	2914	1			T1	16		T6	10		T8	12
auto[0]	auto[0]	interest[1]	1750	1			T1	13		T6	5		T8	11
auto[0]	auto[0]	interest[4]	10327	1			T1	48		T6	16		T8	78
auto[0]	auto[0]	interest[64]	5117	1			T1	27		T6	13		T8	37
auto[0]	auto[1]	others[0]	10277	1			T1	28		T4	13		T6	47
auto[0]	auto[1]	others[1]	1641	1			T1	3		T6	7		T8	4
auto[0]	auto[1]	others[2]	1621	1			T1	4		T6	7		T8	4
auto[0]	auto[1]	others[3]	1791	1			T1	6		T6	5		T8	9
auto[0]	auto[1]	interest[1]	1093	1			T1	3		T6	5		T8	7
auto[0]	auto[1]	interest[4]	6836	1			T1	19		T4	13		T6	32
auto[0]	auto[1]	interest[64]	3155	1			T1	12		T6	13		T8	3
auto[1]	auto[0]	others[0]	9407	1			T1	49		T6	46		T8	67
auto[1]	auto[0]	others[1]	1520	1			T1	2		T6	10		T8	12
auto[1]	auto[0]	others[2]	1532	1			T1	7		T6	5		T8	15
auto[1]	auto[0]	others[3]	1751	1			T1	10		T6	8		T8	5
auto[1]	auto[0]	interest[1]	1027	1			T1	2		T6	5		T8	8
auto[1]	auto[0]	interest[4]	6080	1			T1	35		T6	33		T8	46
auto[1]	auto[0]	interest[64]	2916	1			T1	11		T6	10		T8	21

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal