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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
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T1026 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2356401330 Jul 29 05:08:24 PM PDT 24 Jul 29 05:08:48 PM PDT 24 729561997 ps
T114 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3733334165 Jul 29 05:09:27 PM PDT 24 Jul 29 05:09:43 PM PDT 24 1046454155 ps
T1027 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2572294634 Jul 29 05:08:24 PM PDT 24 Jul 29 05:08:24 PM PDT 24 16345836 ps
T1028 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3779480119 Jul 29 05:09:30 PM PDT 24 Jul 29 05:09:30 PM PDT 24 234541600 ps
T1029 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2259413298 Jul 29 05:07:56 PM PDT 24 Jul 29 05:07:57 PM PDT 24 13425159 ps
T111 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4283539067 Jul 29 05:09:27 PM PDT 24 Jul 29 05:09:29 PM PDT 24 65250403 ps
T84 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1016010815 Jul 29 05:08:00 PM PDT 24 Jul 29 05:08:01 PM PDT 24 27066296 ps
T1030 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.270438910 Jul 29 05:08:05 PM PDT 24 Jul 29 05:08:05 PM PDT 24 12738736 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4121858432 Jul 29 05:08:02 PM PDT 24 Jul 29 05:08:05 PM PDT 24 157746737 ps
T1031 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3114940075 Jul 29 05:08:08 PM PDT 24 Jul 29 05:08:09 PM PDT 24 31731759 ps
T1032 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3630777042 Jul 29 05:08:54 PM PDT 24 Jul 29 05:08:55 PM PDT 24 17467965 ps
T1033 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4060016354 Jul 29 05:08:10 PM PDT 24 Jul 29 05:08:12 PM PDT 24 214346180 ps
T1034 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.711067517 Jul 29 05:08:55 PM PDT 24 Jul 29 05:08:56 PM PDT 24 43568958 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1581011314 Jul 29 05:08:53 PM PDT 24 Jul 29 05:08:56 PM PDT 24 145544541 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1189040748 Jul 29 05:08:47 PM PDT 24 Jul 29 05:08:49 PM PDT 24 149337086 ps
T132 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2065431813 Jul 29 05:08:39 PM PDT 24 Jul 29 05:08:40 PM PDT 24 63096474 ps
T174 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1107152447 Jul 29 05:08:30 PM PDT 24 Jul 29 05:08:51 PM PDT 24 1990895242 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4025095135 Jul 29 05:08:00 PM PDT 24 Jul 29 05:08:07 PM PDT 24 1390768397 ps
T86 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1409809181 Jul 29 05:08:04 PM PDT 24 Jul 29 05:08:05 PM PDT 24 74874149 ps
T133 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2767288892 Jul 29 05:08:10 PM PDT 24 Jul 29 05:08:12 PM PDT 24 32133329 ps
T175 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1172714584 Jul 29 05:08:53 PM PDT 24 Jul 29 05:09:07 PM PDT 24 2549419781 ps
T134 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.219816808 Jul 29 05:09:27 PM PDT 24 Jul 29 05:09:29 PM PDT 24 193370879 ps
T1036 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.663647139 Jul 29 05:08:53 PM PDT 24 Jul 29 05:08:56 PM PDT 24 187273064 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.560634816 Jul 29 05:08:54 PM PDT 24 Jul 29 05:08:55 PM PDT 24 54192430 ps
T179 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3442283491 Jul 29 05:08:44 PM PDT 24 Jul 29 05:08:52 PM PDT 24 739259800 ps
T106 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1703073151 Jul 29 05:08:37 PM PDT 24 Jul 29 05:08:40 PM PDT 24 55109421 ps
T1038 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.659914183 Jul 29 05:08:49 PM PDT 24 Jul 29 05:08:51 PM PDT 24 285727754 ps
T108 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4266612445 Jul 29 05:08:55 PM PDT 24 Jul 29 05:09:01 PM PDT 24 1440025031 ps
T112 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2779746473 Jul 29 05:08:17 PM PDT 24 Jul 29 05:08:20 PM PDT 24 49314492 ps
T1039 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1794451485 Jul 29 05:09:07 PM PDT 24 Jul 29 05:09:08 PM PDT 24 13538418 ps
T1040 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2692938975 Jul 29 05:09:24 PM PDT 24 Jul 29 05:09:25 PM PDT 24 35257125 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3976198838 Jul 29 05:08:10 PM PDT 24 Jul 29 05:08:12 PM PDT 24 702200108 ps
T107 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.422144242 Jul 29 05:08:11 PM PDT 24 Jul 29 05:08:15 PM PDT 24 1025917490 ps
T1042 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2008541883 Jul 29 05:08:24 PM PDT 24 Jul 29 05:08:24 PM PDT 24 57731638 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2409940395 Jul 29 05:08:56 PM PDT 24 Jul 29 05:08:59 PM PDT 24 208417788 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.414495527 Jul 29 05:08:02 PM PDT 24 Jul 29 05:08:05 PM PDT 24 64334661 ps
T1045 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3544976062 Jul 29 05:08:41 PM PDT 24 Jul 29 05:08:41 PM PDT 24 37231808 ps
T1046 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.892563724 Jul 29 05:09:12 PM PDT 24 Jul 29 05:09:13 PM PDT 24 16154971 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3695937864 Jul 29 05:08:49 PM PDT 24 Jul 29 05:08:52 PM PDT 24 83665998 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2457718369 Jul 29 05:07:52 PM PDT 24 Jul 29 05:07:53 PM PDT 24 33644129 ps
T180 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3176899806 Jul 29 05:08:03 PM PDT 24 Jul 29 05:08:25 PM PDT 24 1088949790 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3422966372 Jul 29 05:08:07 PM PDT 24 Jul 29 05:08:12 PM PDT 24 95690656 ps
T1050 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.177999807 Jul 29 05:08:55 PM PDT 24 Jul 29 05:08:56 PM PDT 24 52567190 ps
T109 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3571947548 Jul 29 05:08:35 PM PDT 24 Jul 29 05:08:40 PM PDT 24 737100305 ps
T1051 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2029027151 Jul 29 05:08:56 PM PDT 24 Jul 29 05:08:58 PM PDT 24 32062769 ps
T1052 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.554330184 Jul 29 05:09:17 PM PDT 24 Jul 29 05:09:18 PM PDT 24 13751475 ps
T1053 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.193272547 Jul 29 05:08:19 PM PDT 24 Jul 29 05:08:24 PM PDT 24 72489997 ps
T1054 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.148049299 Jul 29 05:08:31 PM PDT 24 Jul 29 05:08:34 PM PDT 24 99774218 ps
T1055 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3292817008 Jul 29 05:09:03 PM PDT 24 Jul 29 05:09:04 PM PDT 24 34057674 ps
T1056 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1842855760 Jul 29 05:08:08 PM PDT 24 Jul 29 05:08:16 PM PDT 24 1394130859 ps
T182 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.509800936 Jul 29 05:08:32 PM PDT 24 Jul 29 05:08:53 PM PDT 24 3989123742 ps
T1057 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.777622389 Jul 29 05:09:35 PM PDT 24 Jul 29 05:09:36 PM PDT 24 74632684 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.146553741 Jul 29 05:08:39 PM PDT 24 Jul 29 05:08:42 PM PDT 24 108923534 ps
T1059 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.509522793 Jul 29 05:08:47 PM PDT 24 Jul 29 05:08:53 PM PDT 24 2700454483 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1448340540 Jul 29 05:07:58 PM PDT 24 Jul 29 05:08:34 PM PDT 24 7201669048 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3217127811 Jul 29 05:09:08 PM PDT 24 Jul 29 05:09:10 PM PDT 24 30962079 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4094074077 Jul 29 05:07:58 PM PDT 24 Jul 29 05:08:00 PM PDT 24 56164356 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3421220951 Jul 29 05:08:11 PM PDT 24 Jul 29 05:08:27 PM PDT 24 632846882 ps
T1064 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2760305960 Jul 29 05:08:40 PM PDT 24 Jul 29 05:08:42 PM PDT 24 27319093 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1892572462 Jul 29 05:07:50 PM PDT 24 Jul 29 05:07:57 PM PDT 24 126429629 ps
T1066 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3072018372 Jul 29 05:08:26 PM PDT 24 Jul 29 05:08:28 PM PDT 24 45880822 ps
T1067 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4113346799 Jul 29 05:08:48 PM PDT 24 Jul 29 05:08:51 PM PDT 24 312411592 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3758960489 Jul 29 05:08:00 PM PDT 24 Jul 29 05:08:02 PM PDT 24 91266957 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2544267928 Jul 29 05:08:01 PM PDT 24 Jul 29 05:08:01 PM PDT 24 36410273 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1345830307 Jul 29 05:08:12 PM PDT 24 Jul 29 05:08:12 PM PDT 24 65541554 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3650345034 Jul 29 05:08:25 PM PDT 24 Jul 29 05:08:34 PM PDT 24 1686451968 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1746619351 Jul 29 05:08:37 PM PDT 24 Jul 29 05:08:46 PM PDT 24 1665632427 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2027209704 Jul 29 05:08:04 PM PDT 24 Jul 29 05:08:05 PM PDT 24 47425964 ps
T1074 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3401895383 Jul 29 05:08:42 PM PDT 24 Jul 29 05:08:42 PM PDT 24 41196776 ps
T1075 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1522397035 Jul 29 05:09:12 PM PDT 24 Jul 29 05:09:27 PM PDT 24 4553707980 ps
T181 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3876385457 Jul 29 05:08:32 PM PDT 24 Jul 29 05:08:41 PM PDT 24 290463970 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1435178532 Jul 29 05:08:48 PM PDT 24 Jul 29 05:08:51 PM PDT 24 182959436 ps
T1077 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4114641205 Jul 29 05:08:53 PM PDT 24 Jul 29 05:08:57 PM PDT 24 62683842 ps
T1078 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1460679220 Jul 29 05:08:09 PM PDT 24 Jul 29 05:08:12 PM PDT 24 178066603 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2687005794 Jul 29 05:08:03 PM PDT 24 Jul 29 05:08:26 PM PDT 24 735307086 ps
T1080 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.572327279 Jul 29 05:08:55 PM PDT 24 Jul 29 05:08:56 PM PDT 24 24266870 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2628466735 Jul 29 05:09:14 PM PDT 24 Jul 29 05:09:30 PM PDT 24 2780522851 ps
T1082 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2498418639 Jul 29 05:08:31 PM PDT 24 Jul 29 05:08:35 PM PDT 24 1061582821 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.270702810 Jul 29 05:08:48 PM PDT 24 Jul 29 05:09:00 PM PDT 24 448051864 ps
T1084 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2165213221 Jul 29 05:08:25 PM PDT 24 Jul 29 05:08:30 PM PDT 24 306366877 ps
T1085 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2102571742 Jul 29 05:09:07 PM PDT 24 Jul 29 05:09:07 PM PDT 24 12622027 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2217961494 Jul 29 05:08:00 PM PDT 24 Jul 29 05:08:04 PM PDT 24 318806570 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2316614965 Jul 29 05:08:39 PM PDT 24 Jul 29 05:08:43 PM PDT 24 152997327 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1744042743 Jul 29 05:07:50 PM PDT 24 Jul 29 05:07:51 PM PDT 24 67705461 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.586127152 Jul 29 05:08:59 PM PDT 24 Jul 29 05:09:01 PM PDT 24 51390743 ps
T1090 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.257137651 Jul 29 05:08:54 PM PDT 24 Jul 29 05:08:56 PM PDT 24 49394010 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.46281391 Jul 29 05:08:47 PM PDT 24 Jul 29 05:08:50 PM PDT 24 209744559 ps
T1092 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3062377791 Jul 29 05:09:06 PM PDT 24 Jul 29 05:09:09 PM PDT 24 1054149207 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.277205530 Jul 29 05:08:41 PM PDT 24 Jul 29 05:08:42 PM PDT 24 14947568 ps
T1094 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.428942774 Jul 29 05:08:30 PM PDT 24 Jul 29 05:08:34 PM PDT 24 818644035 ps
T87 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.455812673 Jul 29 05:08:31 PM PDT 24 Jul 29 05:08:33 PM PDT 24 45271282 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3904890361 Jul 29 05:08:55 PM PDT 24 Jul 29 05:08:57 PM PDT 24 27346695 ps
T1096 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1694637804 Jul 29 05:09:13 PM PDT 24 Jul 29 05:09:16 PM PDT 24 112705879 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.290538475 Jul 29 05:08:37 PM PDT 24 Jul 29 05:08:41 PM PDT 24 508586248 ps
T1098 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3223694491 Jul 29 05:09:00 PM PDT 24 Jul 29 05:09:04 PM PDT 24 61915135 ps
T1099 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1010426732 Jul 29 05:08:31 PM PDT 24 Jul 29 05:08:32 PM PDT 24 29969993 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1303272598 Jul 29 05:08:19 PM PDT 24 Jul 29 05:08:27 PM PDT 24 630194374 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1617469654 Jul 29 05:08:19 PM PDT 24 Jul 29 05:08:22 PM PDT 24 143140441 ps
T1102 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1607254380 Jul 29 05:08:36 PM PDT 24 Jul 29 05:08:37 PM PDT 24 46479150 ps
T1103 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1155238987 Jul 29 05:08:03 PM PDT 24 Jul 29 05:08:05 PM PDT 24 75988910 ps
T1104 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4057494006 Jul 29 05:08:30 PM PDT 24 Jul 29 05:08:31 PM PDT 24 23435320 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.932795416 Jul 29 05:08:01 PM PDT 24 Jul 29 05:08:04 PM PDT 24 136981197 ps
T1106 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3277596240 Jul 29 05:09:04 PM PDT 24 Jul 29 05:09:07 PM PDT 24 43058710 ps
T177 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3772910666 Jul 29 05:08:56 PM PDT 24 Jul 29 05:09:19 PM PDT 24 912557490 ps
T1107 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.108139193 Jul 29 05:08:01 PM PDT 24 Jul 29 05:08:02 PM PDT 24 13054095 ps
T1108 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2726272538 Jul 29 05:09:26 PM PDT 24 Jul 29 05:09:29 PM PDT 24 44777769 ps
T1109 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2186880773 Jul 29 05:08:12 PM PDT 24 Jul 29 05:08:18 PM PDT 24 359055383 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2814939674 Jul 29 05:07:57 PM PDT 24 Jul 29 05:08:00 PM PDT 24 70495054 ps
T1111 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2589742456 Jul 29 05:09:15 PM PDT 24 Jul 29 05:09:16 PM PDT 24 51460980 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1122560942 Jul 29 05:07:57 PM PDT 24 Jul 29 05:08:21 PM PDT 24 2025669663 ps
T1113 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.899451002 Jul 29 05:08:50 PM PDT 24 Jul 29 05:08:50 PM PDT 24 14355899 ps
T88 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2585209453 Jul 29 05:08:34 PM PDT 24 Jul 29 05:08:35 PM PDT 24 17917181 ps
T1114 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1426342258 Jul 29 05:08:36 PM PDT 24 Jul 29 05:08:38 PM PDT 24 106504154 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.54681353 Jul 29 05:08:40 PM PDT 24 Jul 29 05:08:41 PM PDT 24 89905846 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3021485840 Jul 29 05:08:22 PM PDT 24 Jul 29 05:08:24 PM PDT 24 65412388 ps
T1117 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2258330315 Jul 29 05:09:24 PM PDT 24 Jul 29 05:09:26 PM PDT 24 80324369 ps
T1118 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2171139362 Jul 29 05:08:32 PM PDT 24 Jul 29 05:08:33 PM PDT 24 37516972 ps
T1119 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2871992557 Jul 29 05:09:13 PM PDT 24 Jul 29 05:09:15 PM PDT 24 94930089 ps
T1120 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2904084175 Jul 29 05:08:59 PM PDT 24 Jul 29 05:08:59 PM PDT 24 39457744 ps
T1121 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2573429597 Jul 29 05:08:10 PM PDT 24 Jul 29 05:08:12 PM PDT 24 299509599 ps
T1122 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2235946064 Jul 29 05:08:37 PM PDT 24 Jul 29 05:08:37 PM PDT 24 52339327 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4027681781 Jul 29 05:07:49 PM PDT 24 Jul 29 05:08:15 PM PDT 24 4842873024 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2680095843 Jul 29 05:08:41 PM PDT 24 Jul 29 05:08:42 PM PDT 24 50151491 ps
T1125 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1794443813 Jul 29 05:08:56 PM PDT 24 Jul 29 05:08:57 PM PDT 24 16130188 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1774259593 Jul 29 05:07:58 PM PDT 24 Jul 29 05:07:59 PM PDT 24 356639008 ps
T1127 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3005974884 Jul 29 05:08:27 PM PDT 24 Jul 29 05:08:29 PM PDT 24 42714313 ps
T1128 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2990769638 Jul 29 05:08:38 PM PDT 24 Jul 29 05:08:39 PM PDT 24 14371295 ps
T1129 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3225566925 Jul 29 05:08:10 PM PDT 24 Jul 29 05:08:12 PM PDT 24 67728368 ps
T1130 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2053641423 Jul 29 05:09:04 PM PDT 24 Jul 29 05:09:05 PM PDT 24 30742968 ps
T178 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4081192886 Jul 29 05:08:21 PM PDT 24 Jul 29 05:08:35 PM PDT 24 2100722718 ps

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3735929247
Short name T8
Test name
Test status
Simulation time 2944428040 ps
CPU time 30.78 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:10:08 PM PDT 24
Peak memory 225008 kb
Host smart-e2a3681c-4fae-48c6-b921-5aded5ef1bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735929247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3735929247
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1482691966
Short name T12
Test name
Test status
Simulation time 188668184805 ps
CPU time 680.25 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:23:44 PM PDT 24
Peak memory 263380 kb
Host smart-adc27c3b-35b8-41e6-8516-89eba6e9f911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482691966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1482691966
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.702746787
Short name T40
Test name
Test status
Simulation time 21946780333 ps
CPU time 138.97 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 265780 kb
Host smart-ba7b5413-4fd5-4a97-bf49-a75062d97a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702746787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.702746787
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2368251499
Short name T100
Test name
Test status
Simulation time 167288257 ps
CPU time 4.02 seconds
Started Jul 29 05:08:48 PM PDT 24
Finished Jul 29 05:08:52 PM PDT 24
Peak memory 217396 kb
Host smart-91aeffdf-5660-4ef3-9fd8-5bbfff65e624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368251499 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2368251499
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1723833835
Short name T46
Test name
Test status
Simulation time 43761116825 ps
CPU time 257.62 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:14:00 PM PDT 24
Peak memory 265484 kb
Host smart-0e0960ea-15bf-40fb-b920-b35cbd9d1fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723833835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1723833835
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3831691407
Short name T70
Test name
Test status
Simulation time 24528220 ps
CPU time 0.76 seconds
Started Jul 29 05:09:26 PM PDT 24
Finished Jul 29 05:09:27 PM PDT 24
Peak memory 216380 kb
Host smart-c7c43388-009d-4ebe-9337-adcd68e883bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831691407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3831691407
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.993861148
Short name T208
Test name
Test status
Simulation time 14519254335 ps
CPU time 97.69 seconds
Started Jul 29 05:10:58 PM PDT 24
Finished Jul 29 05:12:36 PM PDT 24
Peak memory 252508 kb
Host smart-17ec0988-2697-47e7-a32a-87bdd7f97bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993861148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.993861148
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.435177528
Short name T28
Test name
Test status
Simulation time 338436420334 ps
CPU time 321.78 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 265700 kb
Host smart-8eccdae1-c6ca-41ab-a2fa-d9ba024625b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435177528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.435177528
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2344067574
Short name T192
Test name
Test status
Simulation time 27570569222 ps
CPU time 277.36 seconds
Started Jul 29 05:12:59 PM PDT 24
Finished Jul 29 05:17:36 PM PDT 24
Peak memory 264860 kb
Host smart-08b1fa92-2786-42f1-a752-bc6eaf1697a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344067574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2344067574
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2581711801
Short name T19
Test name
Test status
Simulation time 138141319 ps
CPU time 1.15 seconds
Started Jul 29 05:09:02 PM PDT 24
Finished Jul 29 05:09:04 PM PDT 24
Peak memory 236748 kb
Host smart-cd09bff5-e929-4a57-a20a-26b36b9d3712
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581711801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2581711801
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4243725105
Short name T203
Test name
Test status
Simulation time 4816380863 ps
CPU time 142.81 seconds
Started Jul 29 05:11:22 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 266632 kb
Host smart-4f353e18-063d-433e-a032-3ef25899e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243725105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4243725105
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.712290521
Short name T20
Test name
Test status
Simulation time 36218165994 ps
CPU time 370.4 seconds
Started Jul 29 05:11:03 PM PDT 24
Finished Jul 29 05:17:14 PM PDT 24
Peak memory 253192 kb
Host smart-4cfdc583-bc42-4495-afdd-010cee99fc87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712290521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.712290521
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.38440763
Short name T38
Test name
Test status
Simulation time 145650221 ps
CPU time 7.12 seconds
Started Jul 29 05:10:08 PM PDT 24
Finished Jul 29 05:10:16 PM PDT 24
Peak memory 225100 kb
Host smart-62505994-d1ff-43c7-90b4-b7b69566d2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38440763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.38440763
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.4176424242
Short name T184
Test name
Test status
Simulation time 140431248976 ps
CPU time 273.26 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:14:06 PM PDT 24
Peak memory 272588 kb
Host smart-e5a69946-1574-4877-a29a-4df5e4ba9021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176424242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.4176424242
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2772372531
Short name T101
Test name
Test status
Simulation time 4042858604 ps
CPU time 20.75 seconds
Started Jul 29 05:08:42 PM PDT 24
Finished Jul 29 05:09:03 PM PDT 24
Peak memory 215164 kb
Host smart-dcce03fa-9c35-427e-b578-390f2b71191f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772372531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2772372531
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3654827257
Short name T159
Test name
Test status
Simulation time 61786834314 ps
CPU time 569.96 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 274176 kb
Host smart-5a345f79-5a51-48d4-92ab-c84dffaa68d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654827257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3654827257
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.390051175
Short name T217
Test name
Test status
Simulation time 327702512454 ps
CPU time 850.1 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:25:41 PM PDT 24
Peak memory 266096 kb
Host smart-9b650e1c-9d0f-4022-ada4-a04ca02342c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390051175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.390051175
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2429911562
Short name T127
Test name
Test status
Simulation time 73690490 ps
CPU time 2.42 seconds
Started Jul 29 05:08:46 PM PDT 24
Finished Jul 29 05:08:48 PM PDT 24
Peak memory 215172 kb
Host smart-e03355e4-3a80-42bd-afc4-2b8e279b2116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429911562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
429911562
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1004951650
Short name T14
Test name
Test status
Simulation time 51390894661 ps
CPU time 278.08 seconds
Started Jul 29 05:12:41 PM PDT 24
Finished Jul 29 05:17:19 PM PDT 24
Peak memory 252884 kb
Host smart-6dbaab28-f291-49ec-bff0-0ab9bb6ed9ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004951650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1004951650
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4266612445
Short name T108
Test name
Test status
Simulation time 1440025031 ps
CPU time 5.46 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:09:01 PM PDT 24
Peak memory 216320 kb
Host smart-b4dac009-49eb-4a8b-80df-3e0488f0bc69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266612445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
266612445
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1284591685
Short name T11
Test name
Test status
Simulation time 14910083334 ps
CPU time 83.55 seconds
Started Jul 29 05:12:47 PM PDT 24
Finished Jul 29 05:14:11 PM PDT 24
Peak memory 257684 kb
Host smart-f2cdac13-ceb6-4411-a16a-721cb1a4f9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284591685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1284591685
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3470353853
Short name T229
Test name
Test status
Simulation time 108214249921 ps
CPU time 174.02 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:15:01 PM PDT 24
Peak memory 266012 kb
Host smart-50a450e7-54b9-4c63-947c-bd73f3c95d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470353853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3470353853
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2940101501
Short name T206
Test name
Test status
Simulation time 359577360567 ps
CPU time 592.29 seconds
Started Jul 29 05:10:07 PM PDT 24
Finished Jul 29 05:20:00 PM PDT 24
Peak memory 257548 kb
Host smart-91eaa6eb-737f-4dad-b28a-c511711f0d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940101501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2940101501
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.154515362
Short name T186
Test name
Test status
Simulation time 31799074571 ps
CPU time 291.62 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:16:22 PM PDT 24
Peak memory 265868 kb
Host smart-ed899dc4-56aa-4d87-9e3f-e0161ad0f896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154515362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.154515362
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2755662948
Short name T50
Test name
Test status
Simulation time 80794232895 ps
CPU time 724.57 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:22:14 PM PDT 24
Peak memory 265708 kb
Host smart-abdbe420-fde9-4f13-8aaf-121029906f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755662948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2755662948
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3253186751
Short name T235
Test name
Test status
Simulation time 8367141843 ps
CPU time 127.87 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:15:06 PM PDT 24
Peak memory 251944 kb
Host smart-cea406af-8791-4e01-b6fa-ba2bc8e14f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253186751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3253186751
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2893918592
Short name T92
Test name
Test status
Simulation time 58889504767 ps
CPU time 148.51 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:14:48 PM PDT 24
Peak memory 270384 kb
Host smart-59a0c4ac-ed89-4b37-a188-013bfae9a9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893918592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2893918592
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.204387521
Short name T360
Test name
Test status
Simulation time 11702221 ps
CPU time 0.74 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 205236 kb
Host smart-2e8d01b0-8ae5-4179-9191-83ebc73289b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204387521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.204387521
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.288383390
Short name T219
Test name
Test status
Simulation time 516394418961 ps
CPU time 193.95 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:15:09 PM PDT 24
Peak memory 257492 kb
Host smart-07473c1d-8073-4b2b-8ed7-94f60ffdc068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288383390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.288383390
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1508174642
Short name T21
Test name
Test status
Simulation time 12176636318 ps
CPU time 69.2 seconds
Started Jul 29 05:10:48 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 252784 kb
Host smart-c843caed-836c-479c-9802-bc03f47e3ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508174642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1508174642
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1621098083
Short name T268
Test name
Test status
Simulation time 8495711683 ps
CPU time 73.25 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:13:34 PM PDT 24
Peak memory 240272 kb
Host smart-7cfa4027-e9a3-44db-9662-b0494d08400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621098083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1621098083
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1108231719
Short name T145
Test name
Test status
Simulation time 26835705000 ps
CPU time 138.41 seconds
Started Jul 29 05:13:11 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 256932 kb
Host smart-e2fa3726-bdbc-45bd-bf77-757819f887cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108231719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1108231719
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2156881827
Short name T29
Test name
Test status
Simulation time 588515885 ps
CPU time 8.08 seconds
Started Jul 29 05:09:39 PM PDT 24
Finished Jul 29 05:09:47 PM PDT 24
Peak memory 232956 kb
Host smart-af2cfc59-391f-4e6d-96bc-73c8dbd1817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156881827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2156881827
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.352529158
Short name T35
Test name
Test status
Simulation time 32377592159 ps
CPU time 392.46 seconds
Started Jul 29 05:09:30 PM PDT 24
Finished Jul 29 05:16:03 PM PDT 24
Peak memory 264568 kb
Host smart-506b89e4-b5d0-45bb-af82-59809e47ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352529158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
352529158
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1277310068
Short name T104
Test name
Test status
Simulation time 85505721 ps
CPU time 5.38 seconds
Started Jul 29 05:08:57 PM PDT 24
Finished Jul 29 05:09:03 PM PDT 24
Peak memory 215444 kb
Host smart-75b0eb82-c318-4b42-aef3-9d383636bf62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277310068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1277310068
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.377788867
Short name T67
Test name
Test status
Simulation time 2432661469 ps
CPU time 15.47 seconds
Started Jul 29 05:07:50 PM PDT 24
Finished Jul 29 05:08:06 PM PDT 24
Peak memory 215120 kb
Host smart-0b8473e3-ed2a-4967-b920-a8d8b9ac3590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377788867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.377788867
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1791114824
Short name T138
Test name
Test status
Simulation time 131313679192 ps
CPU time 202.45 seconds
Started Jul 29 05:08:40 PM PDT 24
Finished Jul 29 05:12:02 PM PDT 24
Peak memory 241244 kb
Host smart-184a67d8-ae3a-44c3-94be-669a216c1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791114824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1791114824
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1222627351
Short name T220
Test name
Test status
Simulation time 152455631151 ps
CPU time 511.34 seconds
Started Jul 29 05:09:54 PM PDT 24
Finished Jul 29 05:18:26 PM PDT 24
Peak memory 264660 kb
Host smart-df1ada9f-5224-424a-9136-b860ff92549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222627351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1222627351
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1905249079
Short name T863
Test name
Test status
Simulation time 4270137883 ps
CPU time 13.8 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:53 PM PDT 24
Peak memory 233000 kb
Host smart-b7dbfd9f-9f3b-43ed-b071-b79f527ded15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905249079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1905249079
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3944973259
Short name T16
Test name
Test status
Simulation time 13803687495 ps
CPU time 65.81 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:13:19 PM PDT 24
Peak memory 265924 kb
Host smart-37ef92ac-79b8-4c54-ab69-215665b642f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944973259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3944973259
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.94853604
Short name T194
Test name
Test status
Simulation time 22529496389 ps
CPU time 111.74 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:14:30 PM PDT 24
Peak memory 257128 kb
Host smart-26088d63-515d-45a7-9b19-4edb58e08b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94853604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.94853604
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2370109052
Short name T297
Test name
Test status
Simulation time 397612313 ps
CPU time 13.84 seconds
Started Jul 29 05:09:37 PM PDT 24
Finished Jul 29 05:09:51 PM PDT 24
Peak memory 235144 kb
Host smart-0b7da79b-1a01-4d4a-90bc-7e3149999f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370109052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2370109052
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.328144773
Short name T291
Test name
Test status
Simulation time 891289352 ps
CPU time 4.42 seconds
Started Jul 29 05:09:54 PM PDT 24
Finished Jul 29 05:09:59 PM PDT 24
Peak memory 224888 kb
Host smart-67ad8c90-2a75-4d10-a6fc-44765c05e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328144773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.328144773
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1793032004
Short name T307
Test name
Test status
Simulation time 14122594285 ps
CPU time 170.62 seconds
Started Jul 29 05:10:22 PM PDT 24
Finished Jul 29 05:13:13 PM PDT 24
Peak memory 255144 kb
Host smart-74876a67-b589-4682-9fba-ade60a31e6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793032004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1793032004
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3847036085
Short name T334
Test name
Test status
Simulation time 1498754576 ps
CPU time 26.17 seconds
Started Jul 29 05:09:23 PM PDT 24
Finished Jul 29 05:09:50 PM PDT 24
Peak memory 251384 kb
Host smart-086d536e-54cf-4526-b372-4b18b4f15ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847036085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3847036085
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3629782870
Short name T255
Test name
Test status
Simulation time 2640908347 ps
CPU time 13.08 seconds
Started Jul 29 05:10:04 PM PDT 24
Finished Jul 29 05:10:17 PM PDT 24
Peak memory 241492 kb
Host smart-7f62c73c-75cc-458f-af68-3d34201193d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629782870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3629782870
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.455812673
Short name T87
Test name
Test status
Simulation time 45271282 ps
CPU time 1.12 seconds
Started Jul 29 05:08:31 PM PDT 24
Finished Jul 29 05:08:33 PM PDT 24
Peak memory 206788 kb
Host smart-4f7b8ad6-32db-45a3-a85a-ddc3c49e2929
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455812673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.455812673
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4121858432
Short name T110
Test name
Test status
Simulation time 157746737 ps
CPU time 2.91 seconds
Started Jul 29 05:08:02 PM PDT 24
Finished Jul 29 05:08:05 PM PDT 24
Peak memory 217088 kb
Host smart-91aaaff1-4320-4179-8ea9-dc587b5bc648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121858432 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4121858432
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1892572462
Short name T1065
Test name
Test status
Simulation time 126429629 ps
CPU time 7.57 seconds
Started Jul 29 05:07:50 PM PDT 24
Finished Jul 29 05:07:57 PM PDT 24
Peak memory 215008 kb
Host smart-ef04e21f-07d0-49ab-845c-c30fcc23a9bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892572462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1892572462
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4027681781
Short name T1123
Test name
Test status
Simulation time 4842873024 ps
CPU time 25.17 seconds
Started Jul 29 05:07:49 PM PDT 24
Finished Jul 29 05:08:15 PM PDT 24
Peak memory 206980 kb
Host smart-44b90ba3-2dc2-4a26-916f-6f8b9d326952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027681781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4027681781
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1409809181
Short name T86
Test name
Test status
Simulation time 74874149 ps
CPU time 1.16 seconds
Started Jul 29 05:08:04 PM PDT 24
Finished Jul 29 05:08:05 PM PDT 24
Peak memory 206860 kb
Host smart-8004f86e-c1de-4b9c-a21f-ce1585da9a26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409809181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1409809181
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2457718369
Short name T1048
Test name
Test status
Simulation time 33644129 ps
CPU time 1.24 seconds
Started Jul 29 05:07:52 PM PDT 24
Finished Jul 29 05:07:53 PM PDT 24
Peak memory 215104 kb
Host smart-c2039658-57a1-492a-bafa-5ee56ec5c7c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457718369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
457718369
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4145326120
Short name T1019
Test name
Test status
Simulation time 14852955 ps
CPU time 0.73 seconds
Started Jul 29 05:07:57 PM PDT 24
Finished Jul 29 05:07:57 PM PDT 24
Peak memory 203912 kb
Host smart-7baa698c-c813-4ec5-930f-b32fb1042e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145326120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
145326120
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1953964330
Short name T128
Test name
Test status
Simulation time 39035930 ps
CPU time 1.69 seconds
Started Jul 29 05:07:57 PM PDT 24
Finished Jul 29 05:07:59 PM PDT 24
Peak memory 215020 kb
Host smart-ec080564-34d1-43ba-8ec8-e20a286d99dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953964330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1953964330
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.108139193
Short name T1107
Test name
Test status
Simulation time 13054095 ps
CPU time 0.69 seconds
Started Jul 29 05:08:01 PM PDT 24
Finished Jul 29 05:08:02 PM PDT 24
Peak memory 203880 kb
Host smart-180753a8-6b95-4468-85fc-840bbd27164f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108139193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.108139193
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1155238987
Short name T1103
Test name
Test status
Simulation time 75988910 ps
CPU time 1.84 seconds
Started Jul 29 05:08:03 PM PDT 24
Finished Jul 29 05:08:05 PM PDT 24
Peak memory 206900 kb
Host smart-883c5c2d-9767-4d55-8d9c-5a8c96b090ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155238987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1155238987
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2338488990
Short name T69
Test name
Test status
Simulation time 157125560 ps
CPU time 2.33 seconds
Started Jul 29 05:07:52 PM PDT 24
Finished Jul 29 05:07:54 PM PDT 24
Peak memory 215212 kb
Host smart-587b93dc-f119-4de2-ad3a-814147ca306e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338488990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
338488990
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3650345034
Short name T1071
Test name
Test status
Simulation time 1686451968 ps
CPU time 9.02 seconds
Started Jul 29 05:08:25 PM PDT 24
Finished Jul 29 05:08:34 PM PDT 24
Peak memory 215008 kb
Host smart-372048fd-48c5-4742-81f8-cc71d6625368
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650345034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3650345034
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3511860747
Short name T126
Test name
Test status
Simulation time 192739237 ps
CPU time 11.45 seconds
Started Jul 29 05:07:57 PM PDT 24
Finished Jul 29 05:08:08 PM PDT 24
Peak memory 206860 kb
Host smart-86e0f9d8-be08-4c45-9ae7-00e968ed1222
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511860747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3511860747
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3422966372
Short name T1049
Test name
Test status
Simulation time 95690656 ps
CPU time 4.24 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 217776 kb
Host smart-0ee704ba-5e7d-4056-bb03-14f18dd9325f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422966372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3422966372
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1764535585
Short name T1021
Test name
Test status
Simulation time 78439871 ps
CPU time 1.38 seconds
Started Jul 29 05:08:47 PM PDT 24
Finished Jul 29 05:08:49 PM PDT 24
Peak memory 206800 kb
Host smart-10bb5c88-a81a-4953-b279-1f794bbbaafc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764535585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
764535585
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1744042743
Short name T1088
Test name
Test status
Simulation time 67705461 ps
CPU time 0.76 seconds
Started Jul 29 05:07:50 PM PDT 24
Finished Jul 29 05:07:51 PM PDT 24
Peak memory 203876 kb
Host smart-e5a3eb6b-a3c6-4e32-85a4-39b0c2316d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744042743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
744042743
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3021485840
Short name T1116
Test name
Test status
Simulation time 65412388 ps
CPU time 2.08 seconds
Started Jul 29 05:08:22 PM PDT 24
Finished Jul 29 05:08:24 PM PDT 24
Peak memory 214948 kb
Host smart-ba218426-3574-4fc3-92a4-11fb91550dac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021485840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3021485840
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2027209704
Short name T1073
Test name
Test status
Simulation time 47425964 ps
CPU time 0.64 seconds
Started Jul 29 05:08:04 PM PDT 24
Finished Jul 29 05:08:05 PM PDT 24
Peak memory 203532 kb
Host smart-400fbad1-d63c-4fe5-bfb8-4d9a1596f1db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027209704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2027209704
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.954497214
Short name T150
Test name
Test status
Simulation time 235923460 ps
CPU time 3.94 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:08:59 PM PDT 24
Peak memory 215088 kb
Host smart-362fa0fb-7751-4ffb-a2be-c7613e4630be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954497214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.954497214
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4094074077
Short name T1062
Test name
Test status
Simulation time 56164356 ps
CPU time 1.74 seconds
Started Jul 29 05:07:58 PM PDT 24
Finished Jul 29 05:08:00 PM PDT 24
Peak memory 215264 kb
Host smart-7ffee89c-989a-4d32-bb3f-15f52a369976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094074077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
094074077
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1122560942
Short name T1112
Test name
Test status
Simulation time 2025669663 ps
CPU time 23.48 seconds
Started Jul 29 05:07:57 PM PDT 24
Finished Jul 29 05:08:21 PM PDT 24
Peak memory 215468 kb
Host smart-fc55e0b8-0a8b-4a56-8c22-f321cc36dad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122560942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1122560942
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1426342258
Short name T1114
Test name
Test status
Simulation time 106504154 ps
CPU time 1.83 seconds
Started Jul 29 05:08:36 PM PDT 24
Finished Jul 29 05:08:38 PM PDT 24
Peak memory 215172 kb
Host smart-33e00390-d334-40f8-8deb-aa76206af6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426342258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1426342258
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1794443813
Short name T1125
Test name
Test status
Simulation time 16130188 ps
CPU time 0.76 seconds
Started Jul 29 05:08:56 PM PDT 24
Finished Jul 29 05:08:57 PM PDT 24
Peak memory 203540 kb
Host smart-c129cade-11a1-4291-9cbc-ec1f5e895f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794443813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1794443813
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3062377791
Short name T1092
Test name
Test status
Simulation time 1054149207 ps
CPU time 3.19 seconds
Started Jul 29 05:09:06 PM PDT 24
Finished Jul 29 05:09:09 PM PDT 24
Peak memory 214988 kb
Host smart-1bb3309b-1dc1-4a7a-9d73-1709c3aea654
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062377791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3062377791
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2165213221
Short name T1084
Test name
Test status
Simulation time 306366877 ps
CPU time 3.91 seconds
Started Jul 29 05:08:25 PM PDT 24
Finished Jul 29 05:08:30 PM PDT 24
Peak memory 215236 kb
Host smart-94ebc1a5-33b1-419c-b0f1-7d12162af6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165213221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2165213221
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1303272598
Short name T1100
Test name
Test status
Simulation time 630194374 ps
CPU time 7.54 seconds
Started Jul 29 05:08:19 PM PDT 24
Finished Jul 29 05:08:27 PM PDT 24
Peak memory 215140 kb
Host smart-25d07fc8-17ae-43a3-8628-7b6482c2b018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303272598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1303272598
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2231643621
Short name T116
Test name
Test status
Simulation time 49059992 ps
CPU time 3.05 seconds
Started Jul 29 05:08:42 PM PDT 24
Finished Jul 29 05:08:45 PM PDT 24
Peak memory 217268 kb
Host smart-5df0fc2d-35f7-454a-a2ff-86eab1ea12c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231643621 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2231643621
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2573429597
Short name T1121
Test name
Test status
Simulation time 299509599 ps
CPU time 2.03 seconds
Started Jul 29 05:08:10 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 215072 kb
Host smart-5577e49f-9dbb-4aa2-95fe-196c8c6a37ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573429597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2573429597
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1607254380
Short name T1102
Test name
Test status
Simulation time 46479150 ps
CPU time 0.74 seconds
Started Jul 29 05:08:36 PM PDT 24
Finished Jul 29 05:08:37 PM PDT 24
Peak memory 203524 kb
Host smart-1b31acce-7656-4b10-b4a4-c4b090ee01b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607254380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1607254380
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3393687666
Short name T1024
Test name
Test status
Simulation time 61997959 ps
CPU time 4.07 seconds
Started Jul 29 05:08:35 PM PDT 24
Finished Jul 29 05:08:39 PM PDT 24
Peak memory 215040 kb
Host smart-7c7c3328-b585-45c8-96bc-669aa9f4c6ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393687666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3393687666
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2186880773
Short name T1109
Test name
Test status
Simulation time 359055383 ps
CPU time 5.21 seconds
Started Jul 29 05:08:12 PM PDT 24
Finished Jul 29 05:08:18 PM PDT 24
Peak memory 215168 kb
Host smart-cd2dadc5-7a01-48e6-9d03-a7d8a22ee5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186880773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2186880773
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.509800936
Short name T182
Test name
Test status
Simulation time 3989123742 ps
CPU time 20.8 seconds
Started Jul 29 05:08:32 PM PDT 24
Finished Jul 29 05:08:53 PM PDT 24
Peak memory 215408 kb
Host smart-4284ffd4-a1c3-4ed9-b755-d67a6115444b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509800936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.509800936
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.428942774
Short name T1094
Test name
Test status
Simulation time 818644035 ps
CPU time 4.06 seconds
Started Jul 29 05:08:30 PM PDT 24
Finished Jul 29 05:08:34 PM PDT 24
Peak memory 216916 kb
Host smart-2ceafbf4-3fa2-4590-a952-e1e459386d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428942774 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.428942774
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.219816808
Short name T134
Test name
Test status
Simulation time 193370879 ps
CPU time 2.61 seconds
Started Jul 29 05:09:27 PM PDT 24
Finished Jul 29 05:09:29 PM PDT 24
Peak memory 215012 kb
Host smart-08fea721-d265-4f94-82af-b0d8aabefe3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219816808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.219816808
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3544976062
Short name T1045
Test name
Test status
Simulation time 37231808 ps
CPU time 0.72 seconds
Started Jul 29 05:08:41 PM PDT 24
Finished Jul 29 05:08:41 PM PDT 24
Peak memory 203544 kb
Host smart-f5b358c0-607f-45f1-b64a-dbfd61f3f789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544976062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3544976062
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2871992557
Short name T1119
Test name
Test status
Simulation time 94930089 ps
CPU time 1.78 seconds
Started Jul 29 05:09:13 PM PDT 24
Finished Jul 29 05:09:15 PM PDT 24
Peak memory 215048 kb
Host smart-c059bccb-c569-48f9-a33b-151a9b266c08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871992557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2871992557
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3571947548
Short name T109
Test name
Test status
Simulation time 737100305 ps
CPU time 4.82 seconds
Started Jul 29 05:08:35 PM PDT 24
Finished Jul 29 05:08:40 PM PDT 24
Peak memory 215232 kb
Host smart-baaf8ed9-0863-4f07-aa36-b00353a10f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571947548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3571947548
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3733334165
Short name T114
Test name
Test status
Simulation time 1046454155 ps
CPU time 16.39 seconds
Started Jul 29 05:09:27 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 215092 kb
Host smart-4399d181-aa79-4bd7-8f95-730be6555c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733334165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3733334165
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.570347401
Short name T103
Test name
Test status
Simulation time 213691695 ps
CPU time 3.68 seconds
Started Jul 29 05:08:56 PM PDT 24
Finished Jul 29 05:09:00 PM PDT 24
Peak memory 217556 kb
Host smart-abc342c6-2a8e-49ed-8c3d-f72cf607970f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570347401 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.570347401
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1694637804
Short name T1096
Test name
Test status
Simulation time 112705879 ps
CPU time 2.78 seconds
Started Jul 29 05:09:13 PM PDT 24
Finished Jul 29 05:09:16 PM PDT 24
Peak memory 214960 kb
Host smart-6584208d-c5fc-4b75-8e69-e0e75c49fe6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694637804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1694637804
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2171139362
Short name T1118
Test name
Test status
Simulation time 37516972 ps
CPU time 0.69 seconds
Started Jul 29 05:08:32 PM PDT 24
Finished Jul 29 05:08:33 PM PDT 24
Peak memory 203604 kb
Host smart-16b18840-a7c5-4a91-9146-16e5326f87e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171139362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2171139362
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.46281391
Short name T1091
Test name
Test status
Simulation time 209744559 ps
CPU time 2.86 seconds
Started Jul 29 05:08:47 PM PDT 24
Finished Jul 29 05:08:50 PM PDT 24
Peak memory 215004 kb
Host smart-4190bc19-0588-4c97-aefe-1ecc330a2a2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46281391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sp
i_device_same_csr_outstanding.46281391
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.509522793
Short name T1059
Test name
Test status
Simulation time 2700454483 ps
CPU time 5.24 seconds
Started Jul 29 05:08:47 PM PDT 24
Finished Jul 29 05:08:53 PM PDT 24
Peak memory 215228 kb
Host smart-3b0c4ab7-d7dd-4f6a-a2ca-7a6ac2c6d4f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509522793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.509522793
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3442283491
Short name T179
Test name
Test status
Simulation time 739259800 ps
CPU time 8.5 seconds
Started Jul 29 05:08:44 PM PDT 24
Finished Jul 29 05:08:52 PM PDT 24
Peak memory 215040 kb
Host smart-62b51fc0-56e3-446d-8f4b-ddb801fa456d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442283491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3442283491
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.761032919
Short name T68
Test name
Test status
Simulation time 32664329 ps
CPU time 1.76 seconds
Started Jul 29 05:08:20 PM PDT 24
Finished Jul 29 05:08:21 PM PDT 24
Peak memory 216156 kb
Host smart-3af53bab-de93-40fd-bccd-f9b0c0d1dde5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761032919 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.761032919
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.586127152
Short name T1089
Test name
Test status
Simulation time 51390743 ps
CPU time 1.9 seconds
Started Jul 29 05:08:59 PM PDT 24
Finished Jul 29 05:09:01 PM PDT 24
Peak memory 215008 kb
Host smart-9a9c1a82-456b-4349-84e0-ee001af29eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586127152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.586127152
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4057494006
Short name T1104
Test name
Test status
Simulation time 23435320 ps
CPU time 0.7 seconds
Started Jul 29 05:08:30 PM PDT 24
Finished Jul 29 05:08:31 PM PDT 24
Peak memory 203596 kb
Host smart-df47bb49-a8e3-4c04-88d3-24e7cde99f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057494006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4057494006
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.257137651
Short name T1090
Test name
Test status
Simulation time 49394010 ps
CPU time 1.73 seconds
Started Jul 29 05:08:54 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 206780 kb
Host smart-3076bbd6-fd7e-40e2-acba-6d2da5b1976b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257137651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.257137651
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1703073151
Short name T106
Test name
Test status
Simulation time 55109421 ps
CPU time 3.25 seconds
Started Jul 29 05:08:37 PM PDT 24
Finished Jul 29 05:08:40 PM PDT 24
Peak memory 215092 kb
Host smart-16b49998-edc4-4a2f-a8a5-579ad6db3d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703073151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1703073151
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2628466735
Short name T1081
Test name
Test status
Simulation time 2780522851 ps
CPU time 16.78 seconds
Started Jul 29 05:09:14 PM PDT 24
Finished Jul 29 05:09:30 PM PDT 24
Peak memory 215636 kb
Host smart-6e145d61-17ce-4fbb-a7da-475322ef3864
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628466735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2628466735
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.146553741
Short name T1058
Test name
Test status
Simulation time 108923534 ps
CPU time 2.87 seconds
Started Jul 29 05:08:39 PM PDT 24
Finished Jul 29 05:08:42 PM PDT 24
Peak memory 216100 kb
Host smart-f324e04f-93e8-48ad-8e95-5334e12e77e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146553741 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.146553741
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2029027151
Short name T1051
Test name
Test status
Simulation time 32062769 ps
CPU time 1.21 seconds
Started Jul 29 05:08:56 PM PDT 24
Finished Jul 29 05:08:58 PM PDT 24
Peak memory 215052 kb
Host smart-aa15c240-70e7-4eec-ad51-e6ba6b9ce2a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029027151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2029027151
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1997762662
Short name T1013
Test name
Test status
Simulation time 24498673 ps
CPU time 0.75 seconds
Started Jul 29 05:08:57 PM PDT 24
Finished Jul 29 05:08:58 PM PDT 24
Peak memory 203600 kb
Host smart-4c347638-dc45-4ec2-8654-d9b116864723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997762662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1997762662
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2409940395
Short name T1043
Test name
Test status
Simulation time 208417788 ps
CPU time 3.31 seconds
Started Jul 29 05:08:56 PM PDT 24
Finished Jul 29 05:08:59 PM PDT 24
Peak memory 215344 kb
Host smart-ecba363a-38cc-41af-a2df-e1516c3ac46c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409940395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2409940395
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.193272547
Short name T1053
Test name
Test status
Simulation time 72489997 ps
CPU time 5.21 seconds
Started Jul 29 05:08:19 PM PDT 24
Finished Jul 29 05:08:24 PM PDT 24
Peak memory 215268 kb
Host smart-feb2c0c1-6983-43a8-a12e-e6feda7e9d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193272547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.193272547
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3072018372
Short name T1066
Test name
Test status
Simulation time 45880822 ps
CPU time 1.78 seconds
Started Jul 29 05:08:26 PM PDT 24
Finished Jul 29 05:08:28 PM PDT 24
Peak memory 215048 kb
Host smart-18b34fb7-72f9-4b9a-843e-f00ae8ef95b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072018372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3072018372
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3956479864
Short name T125
Test name
Test status
Simulation time 37436859 ps
CPU time 2.26 seconds
Started Jul 29 05:09:09 PM PDT 24
Finished Jul 29 05:09:11 PM PDT 24
Peak memory 206800 kb
Host smart-cae2d941-fe6c-4e4c-97d6-93bbd92b735c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956479864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3956479864
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2518192913
Short name T1007
Test name
Test status
Simulation time 41717291 ps
CPU time 0.72 seconds
Started Jul 29 05:08:39 PM PDT 24
Finished Jul 29 05:08:40 PM PDT 24
Peak memory 203536 kb
Host smart-56da6ffd-0709-481c-8bf1-4d1c6f8e1cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518192913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2518192913
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3277596240
Short name T1106
Test name
Test status
Simulation time 43058710 ps
CPU time 2.66 seconds
Started Jul 29 05:09:04 PM PDT 24
Finished Jul 29 05:09:07 PM PDT 24
Peak memory 215140 kb
Host smart-d376d959-23b5-4d6a-aae1-0a070025913f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277596240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3277596240
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2726272538
Short name T1108
Test name
Test status
Simulation time 44777769 ps
CPU time 2.89 seconds
Started Jul 29 05:09:26 PM PDT 24
Finished Jul 29 05:09:29 PM PDT 24
Peak memory 217108 kb
Host smart-a0db5fb5-9d6f-40c7-93c4-2b6a057f2f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726272538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2726272538
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1294886958
Short name T176
Test name
Test status
Simulation time 2686526140 ps
CPU time 7.48 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:09:03 PM PDT 24
Peak memory 215148 kb
Host smart-0762ad19-0e1b-4588-8210-9345396c8f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294886958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1294886958
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1152161419
Short name T118
Test name
Test status
Simulation time 26821532 ps
CPU time 1.62 seconds
Started Jul 29 05:08:42 PM PDT 24
Finished Jul 29 05:08:44 PM PDT 24
Peak memory 215296 kb
Host smart-8e3f8aed-85c1-4139-93d0-ae342523c537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152161419 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1152161419
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.867470749
Short name T131
Test name
Test status
Simulation time 520336438 ps
CPU time 2.54 seconds
Started Jul 29 05:08:57 PM PDT 24
Finished Jul 29 05:09:00 PM PDT 24
Peak memory 214996 kb
Host smart-2cf9dfc1-28e1-4634-95fc-e8c91c80f6c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867470749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.867470749
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2904084175
Short name T1120
Test name
Test status
Simulation time 39457744 ps
CPU time 0.68 seconds
Started Jul 29 05:08:59 PM PDT 24
Finished Jul 29 05:08:59 PM PDT 24
Peak memory 203892 kb
Host smart-5b30dd0b-1598-4c5f-a4f0-a542404779ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904084175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2904084175
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3223694491
Short name T1098
Test name
Test status
Simulation time 61915135 ps
CPU time 3.85 seconds
Started Jul 29 05:09:00 PM PDT 24
Finished Jul 29 05:09:04 PM PDT 24
Peak memory 215052 kb
Host smart-8d781b8a-eca1-4cb2-a849-69fdf02db53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223694491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3223694491
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3005974884
Short name T1127
Test name
Test status
Simulation time 42714313 ps
CPU time 2.56 seconds
Started Jul 29 05:08:27 PM PDT 24
Finished Jul 29 05:08:29 PM PDT 24
Peak memory 216164 kb
Host smart-44583beb-af09-42ff-b0b1-ae71cb450afb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005974884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3005974884
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.270702810
Short name T1083
Test name
Test status
Simulation time 448051864 ps
CPU time 12 seconds
Started Jul 29 05:08:48 PM PDT 24
Finished Jul 29 05:09:00 PM PDT 24
Peak memory 215080 kb
Host smart-91f4ecfd-f568-4173-b838-af1c41b6b6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270702810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.270702810
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3988275232
Short name T115
Test name
Test status
Simulation time 428342019 ps
CPU time 2.82 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:06 PM PDT 24
Peak memory 216860 kb
Host smart-0310ba44-d096-44d4-9ff7-9feaf7c3c8e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988275232 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3988275232
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.560634816
Short name T1037
Test name
Test status
Simulation time 54192430 ps
CPU time 1.19 seconds
Started Jul 29 05:08:54 PM PDT 24
Finished Jul 29 05:08:55 PM PDT 24
Peak memory 215072 kb
Host smart-ddf604a6-bf22-4cfa-a10d-9733746b30c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560634816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.560634816
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3630777042
Short name T1032
Test name
Test status
Simulation time 17467965 ps
CPU time 0.73 seconds
Started Jul 29 05:08:54 PM PDT 24
Finished Jul 29 05:08:55 PM PDT 24
Peak memory 203584 kb
Host smart-8412fe03-e6fa-437e-9ea0-497770089f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630777042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3630777042
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.659914183
Short name T1038
Test name
Test status
Simulation time 285727754 ps
CPU time 1.82 seconds
Started Jul 29 05:08:49 PM PDT 24
Finished Jul 29 05:08:51 PM PDT 24
Peak memory 206872 kb
Host smart-c41cc2ee-b331-4cbf-a5aa-3597d7e7e2da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659914183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.659914183
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1581011314
Short name T113
Test name
Test status
Simulation time 145544541 ps
CPU time 2.23 seconds
Started Jul 29 05:08:53 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 215368 kb
Host smart-900bc924-67cf-4ee1-ba92-8d294c838318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581011314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1581011314
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1522397035
Short name T1075
Test name
Test status
Simulation time 4553707980 ps
CPU time 15.31 seconds
Started Jul 29 05:09:12 PM PDT 24
Finished Jul 29 05:09:27 PM PDT 24
Peak memory 216340 kb
Host smart-cd853539-d615-457e-ada2-bcd05e4e8717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522397035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1522397035
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3904890361
Short name T1095
Test name
Test status
Simulation time 27346695 ps
CPU time 1.81 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:08:57 PM PDT 24
Peak memory 215160 kb
Host smart-17f720a3-7ee5-4cff-a8a5-3b777248302c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904890361 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3904890361
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3217127811
Short name T1061
Test name
Test status
Simulation time 30962079 ps
CPU time 1.51 seconds
Started Jul 29 05:09:08 PM PDT 24
Finished Jul 29 05:09:10 PM PDT 24
Peak memory 206824 kb
Host smart-2cc6d409-3edf-4d83-abc3-ce57d935990a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217127811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3217127811
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.277205530
Short name T1093
Test name
Test status
Simulation time 14947568 ps
CPU time 0.79 seconds
Started Jul 29 05:08:41 PM PDT 24
Finished Jul 29 05:08:42 PM PDT 24
Peak memory 203820 kb
Host smart-235338bc-55d0-43bf-ab13-902ed2bc070d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277205530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.277205530
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2760305960
Short name T1064
Test name
Test status
Simulation time 27319093 ps
CPU time 1.71 seconds
Started Jul 29 05:08:40 PM PDT 24
Finished Jul 29 05:08:42 PM PDT 24
Peak memory 206812 kb
Host smart-80fed65c-5b7e-4880-851d-940780b66607
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760305960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2760305960
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1775330885
Short name T102
Test name
Test status
Simulation time 13822475266 ps
CPU time 22.01 seconds
Started Jul 29 05:09:32 PM PDT 24
Finished Jul 29 05:09:54 PM PDT 24
Peak memory 215080 kb
Host smart-40337ef6-21d4-443e-8397-98d0b1a86e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775330885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1775330885
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3421220951
Short name T1063
Test name
Test status
Simulation time 632846882 ps
CPU time 15.81 seconds
Started Jul 29 05:08:11 PM PDT 24
Finished Jul 29 05:08:27 PM PDT 24
Peak memory 215176 kb
Host smart-d06ca903-d248-427f-8d94-b16e916ee09b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421220951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3421220951
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2687005794
Short name T1079
Test name
Test status
Simulation time 735307086 ps
CPU time 22.99 seconds
Started Jul 29 05:08:03 PM PDT 24
Finished Jul 29 05:08:26 PM PDT 24
Peak memory 215080 kb
Host smart-c5c87a6e-4b9a-4c44-bf5d-c5373eb83c82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687005794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2687005794
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1016010815
Short name T84
Test name
Test status
Simulation time 27066296 ps
CPU time 0.95 seconds
Started Jul 29 05:08:00 PM PDT 24
Finished Jul 29 05:08:01 PM PDT 24
Peak memory 206720 kb
Host smart-db590e90-0963-43ba-99d9-6cff3f15a56a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016010815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1016010815
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1774259593
Short name T1126
Test name
Test status
Simulation time 356639008 ps
CPU time 1.84 seconds
Started Jul 29 05:07:58 PM PDT 24
Finished Jul 29 05:07:59 PM PDT 24
Peak memory 216232 kb
Host smart-b893e3f5-0e13-48af-8b0d-7eb9d3c7b1e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774259593 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1774259593
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2065431813
Short name T132
Test name
Test status
Simulation time 63096474 ps
CPU time 1.23 seconds
Started Jul 29 05:08:39 PM PDT 24
Finished Jul 29 05:08:40 PM PDT 24
Peak memory 206812 kb
Host smart-1e6d8b5c-bcb0-46cb-8039-9e7fc758685f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065431813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
065431813
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.54681353
Short name T1115
Test name
Test status
Simulation time 89905846 ps
CPU time 0.72 seconds
Started Jul 29 05:08:40 PM PDT 24
Finished Jul 29 05:08:41 PM PDT 24
Peak memory 203872 kb
Host smart-cec1fddf-5be2-42c1-9f29-88f538e3f40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54681353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.54681353
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3025053007
Short name T124
Test name
Test status
Simulation time 34590066 ps
CPU time 1.38 seconds
Started Jul 29 05:08:03 PM PDT 24
Finished Jul 29 05:08:04 PM PDT 24
Peak memory 214948 kb
Host smart-03797e09-83a3-4ad0-95a9-b4e91129a789
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025053007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3025053007
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1345830307
Short name T1070
Test name
Test status
Simulation time 65541554 ps
CPU time 0.68 seconds
Started Jul 29 05:08:12 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 203828 kb
Host smart-de81ea16-ef33-4470-96ad-1f924a876dcb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345830307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1345830307
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2316614965
Short name T1087
Test name
Test status
Simulation time 152997327 ps
CPU time 3.38 seconds
Started Jul 29 05:08:39 PM PDT 24
Finished Jul 29 05:08:43 PM PDT 24
Peak memory 215060 kb
Host smart-d769efef-89bd-4e11-a48c-e7a1e86b2eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316614965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2316614965
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.290538475
Short name T1097
Test name
Test status
Simulation time 508586248 ps
CPU time 3.39 seconds
Started Jul 29 05:08:37 PM PDT 24
Finished Jul 29 05:08:41 PM PDT 24
Peak memory 215308 kb
Host smart-be07d97d-9cf7-438e-b395-2e97598086e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290538475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.290538475
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3176899806
Short name T180
Test name
Test status
Simulation time 1088949790 ps
CPU time 21.78 seconds
Started Jul 29 05:08:03 PM PDT 24
Finished Jul 29 05:08:25 PM PDT 24
Peak memory 215512 kb
Host smart-0698209b-8efe-4f64-af2c-7135e9420615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176899806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3176899806
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2211516742
Short name T1011
Test name
Test status
Simulation time 15500727 ps
CPU time 0.78 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:04 PM PDT 24
Peak memory 203596 kb
Host smart-aef87c2c-a3cd-45ae-9f89-13ac0cbca732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211516742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2211516742
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1313277940
Short name T1014
Test name
Test status
Simulation time 43274092 ps
CPU time 0.7 seconds
Started Jul 29 05:09:02 PM PDT 24
Finished Jul 29 05:09:03 PM PDT 24
Peak memory 203604 kb
Host smart-30909cce-4389-4386-81c6-fde397c56281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313277940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1313277940
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2867373242
Short name T1016
Test name
Test status
Simulation time 44626283 ps
CPU time 0.76 seconds
Started Jul 29 05:08:29 PM PDT 24
Finished Jul 29 05:08:30 PM PDT 24
Peak memory 203540 kb
Host smart-68fe9221-b0a6-4678-887c-6b31003ecd19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867373242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2867373242
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2053641423
Short name T1130
Test name
Test status
Simulation time 30742968 ps
CPU time 0.73 seconds
Started Jul 29 05:09:04 PM PDT 24
Finished Jul 29 05:09:05 PM PDT 24
Peak memory 203528 kb
Host smart-a7500a09-54e2-4978-90b2-f4e755f61b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053641423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2053641423
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.923369329
Short name T1023
Test name
Test status
Simulation time 189732493 ps
CPU time 0.74 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:04 PM PDT 24
Peak memory 203840 kb
Host smart-e1c74bc2-326b-4442-85b8-08cec4778e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923369329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.923369329
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.791922114
Short name T1018
Test name
Test status
Simulation time 32009248 ps
CPU time 0.78 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:09:19 PM PDT 24
Peak memory 203560 kb
Host smart-531af377-a7ec-4050-b2fa-601dfa27eccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791922114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.791922114
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.813411961
Short name T1025
Test name
Test status
Simulation time 39766416 ps
CPU time 0.7 seconds
Started Jul 29 05:08:47 PM PDT 24
Finished Jul 29 05:08:47 PM PDT 24
Peak memory 203532 kb
Host smart-cbc93678-07f4-4b63-992c-6d4700c13be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813411961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.813411961
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.177999807
Short name T1050
Test name
Test status
Simulation time 52567190 ps
CPU time 0.75 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 203584 kb
Host smart-1eae8e30-ca53-47f9-b84f-b2fb6d126b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177999807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.177999807
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1794451485
Short name T1039
Test name
Test status
Simulation time 13538418 ps
CPU time 0.75 seconds
Started Jul 29 05:09:07 PM PDT 24
Finished Jul 29 05:09:08 PM PDT 24
Peak memory 203904 kb
Host smart-4602500b-75bd-4310-b5f5-1ed6d38e60b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794451485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1794451485
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3576445
Short name T1012
Test name
Test status
Simulation time 13792854 ps
CPU time 0.73 seconds
Started Jul 29 05:09:04 PM PDT 24
Finished Jul 29 05:09:05 PM PDT 24
Peak memory 203564 kb
Host smart-78023ba9-2db3-4fd8-a7b7-8460b160c816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.3576445
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1746619351
Short name T1072
Test name
Test status
Simulation time 1665632427 ps
CPU time 9.19 seconds
Started Jul 29 05:08:37 PM PDT 24
Finished Jul 29 05:08:46 PM PDT 24
Peak memory 215016 kb
Host smart-e78c1037-9fde-4105-9298-1c5f0ff2fb58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746619351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1746619351
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1448340540
Short name T1060
Test name
Test status
Simulation time 7201669048 ps
CPU time 35.69 seconds
Started Jul 29 05:07:58 PM PDT 24
Finished Jul 29 05:08:34 PM PDT 24
Peak memory 206916 kb
Host smart-340bc210-8fed-47c7-8dcf-efe4d7c57738
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448340540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1448340540
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1189040748
Short name T85
Test name
Test status
Simulation time 149337086 ps
CPU time 1.36 seconds
Started Jul 29 05:08:47 PM PDT 24
Finished Jul 29 05:08:49 PM PDT 24
Peak memory 206888 kb
Host smart-1c90d48c-e835-4b7f-a96e-a0c0bda4438b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189040748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1189040748
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4089949899
Short name T119
Test name
Test status
Simulation time 491229240 ps
CPU time 2.86 seconds
Started Jul 29 05:07:59 PM PDT 24
Finished Jul 29 05:08:02 PM PDT 24
Peak memory 216180 kb
Host smart-565be54c-a57b-451b-a616-35eae449d247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089949899 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4089949899
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.932795416
Short name T1105
Test name
Test status
Simulation time 136981197 ps
CPU time 2.35 seconds
Started Jul 29 05:08:01 PM PDT 24
Finished Jul 29 05:08:04 PM PDT 24
Peak memory 206748 kb
Host smart-5fddf15c-4a32-47f9-9f40-9ce12f76919b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932795416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.932795416
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2259413298
Short name T1029
Test name
Test status
Simulation time 13425159 ps
CPU time 0.7 seconds
Started Jul 29 05:07:56 PM PDT 24
Finished Jul 29 05:07:57 PM PDT 24
Peak memory 203568 kb
Host smart-c15d9734-efd7-4bd5-bf89-39169d60798e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259413298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
259413298
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3758960489
Short name T1068
Test name
Test status
Simulation time 91266957 ps
CPU time 2.14 seconds
Started Jul 29 05:08:00 PM PDT 24
Finished Jul 29 05:08:02 PM PDT 24
Peak memory 215060 kb
Host smart-597b4a63-76db-4af8-a424-7a2296cfed54
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758960489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3758960489
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.270438910
Short name T1030
Test name
Test status
Simulation time 12738736 ps
CPU time 0.66 seconds
Started Jul 29 05:08:05 PM PDT 24
Finished Jul 29 05:08:05 PM PDT 24
Peak memory 203484 kb
Host smart-eaa72f3c-b1f3-4f89-8c84-8d3a4740778e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270438910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.270438910
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2445665994
Short name T158
Test name
Test status
Simulation time 146491391 ps
CPU time 3.3 seconds
Started Jul 29 05:08:19 PM PDT 24
Finished Jul 29 05:08:22 PM PDT 24
Peak memory 215036 kb
Host smart-643a97e8-4c82-4707-b37c-2755675c080d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445665994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2445665994
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2814939674
Short name T1110
Test name
Test status
Simulation time 70495054 ps
CPU time 2.36 seconds
Started Jul 29 05:07:57 PM PDT 24
Finished Jul 29 05:08:00 PM PDT 24
Peak memory 215232 kb
Host smart-a939a577-689d-4c9e-814b-fbaaf368aa6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814939674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
814939674
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4025095135
Short name T1035
Test name
Test status
Simulation time 1390768397 ps
CPU time 7.13 seconds
Started Jul 29 05:08:00 PM PDT 24
Finished Jul 29 05:08:07 PM PDT 24
Peak memory 215072 kb
Host smart-81983990-4839-41c5-b54e-ac928de687b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025095135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4025095135
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.777622389
Short name T1057
Test name
Test status
Simulation time 74632684 ps
CPU time 0.78 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:36 PM PDT 24
Peak memory 203776 kb
Host smart-f254521e-0744-4f9d-8dad-7e66a198f7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777622389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.777622389
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1505618597
Short name T1020
Test name
Test status
Simulation time 43281701 ps
CPU time 0.69 seconds
Started Jul 29 05:08:54 PM PDT 24
Finished Jul 29 05:08:55 PM PDT 24
Peak memory 203912 kb
Host smart-52878a78-5f74-4c98-a762-a5f93678b4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505618597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1505618597
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.899451002
Short name T1113
Test name
Test status
Simulation time 14355899 ps
CPU time 0.68 seconds
Started Jul 29 05:08:50 PM PDT 24
Finished Jul 29 05:08:50 PM PDT 24
Peak memory 203564 kb
Host smart-3c19f675-a4e2-4dab-905d-bb0bf2114838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899451002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.899451002
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.572327279
Short name T1080
Test name
Test status
Simulation time 24266870 ps
CPU time 0.71 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 203868 kb
Host smart-e5ff18e9-f069-4d16-b234-24f90dcf570f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572327279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.572327279
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3752072999
Short name T1010
Test name
Test status
Simulation time 51650286 ps
CPU time 0.75 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:04 PM PDT 24
Peak memory 203908 kb
Host smart-646ec958-4cc1-4d65-8c50-6b9bdd58c787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752072999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3752072999
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2990769638
Short name T1128
Test name
Test status
Simulation time 14371295 ps
CPU time 0.69 seconds
Started Jul 29 05:08:38 PM PDT 24
Finished Jul 29 05:08:39 PM PDT 24
Peak memory 203840 kb
Host smart-0c2fb19a-f04c-4527-ba7e-bf89301a19a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990769638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2990769638
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2589742456
Short name T1111
Test name
Test status
Simulation time 51460980 ps
CPU time 0.8 seconds
Started Jul 29 05:09:15 PM PDT 24
Finished Jul 29 05:09:16 PM PDT 24
Peak memory 203564 kb
Host smart-f90ee6ff-bb08-432d-8f3f-c41581d17fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589742456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2589742456
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2090139845
Short name T1015
Test name
Test status
Simulation time 46148946 ps
CPU time 0.76 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 203612 kb
Host smart-7a07b315-3ffd-4fe1-ac22-c8edac847112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090139845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2090139845
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.892563724
Short name T1046
Test name
Test status
Simulation time 16154971 ps
CPU time 0.74 seconds
Started Jul 29 05:09:12 PM PDT 24
Finished Jul 29 05:09:13 PM PDT 24
Peak memory 203552 kb
Host smart-db26d619-7af2-4cf9-9eb3-27b3de282619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892563724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.892563724
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.711067517
Short name T1034
Test name
Test status
Simulation time 43568958 ps
CPU time 0.79 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 203520 kb
Host smart-b71b2f14-3a6a-46aa-b22b-18f69c29654a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711067517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.711067517
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.762688328
Short name T130
Test name
Test status
Simulation time 947996502 ps
CPU time 24.26 seconds
Started Jul 29 05:08:22 PM PDT 24
Finished Jul 29 05:08:47 PM PDT 24
Peak memory 215080 kb
Host smart-e3b1b8c6-7a11-40e7-b357-a47fe2591c3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762688328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.762688328
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2356401330
Short name T1026
Test name
Test status
Simulation time 729561997 ps
CPU time 24.6 seconds
Started Jul 29 05:08:24 PM PDT 24
Finished Jul 29 05:08:48 PM PDT 24
Peak memory 206760 kb
Host smart-21ab62f8-1d37-4734-9463-2391fbb2f41d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356401330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2356401330
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2585209453
Short name T88
Test name
Test status
Simulation time 17917181 ps
CPU time 0.99 seconds
Started Jul 29 05:08:34 PM PDT 24
Finished Jul 29 05:08:35 PM PDT 24
Peak memory 206604 kb
Host smart-7971b92c-a4bf-4f6b-8b37-93df5716730b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585209453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2585209453
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3695937864
Short name T1047
Test name
Test status
Simulation time 83665998 ps
CPU time 2.46 seconds
Started Jul 29 05:08:49 PM PDT 24
Finished Jul 29 05:08:52 PM PDT 24
Peak memory 216312 kb
Host smart-4a6110df-e54b-45f7-b4c8-04bdd5054561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695937864 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3695937864
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.414495527
Short name T1044
Test name
Test status
Simulation time 64334661 ps
CPU time 2.47 seconds
Started Jul 29 05:08:02 PM PDT 24
Finished Jul 29 05:08:05 PM PDT 24
Peak memory 215012 kb
Host smart-dd08ce86-1093-441c-9edb-9787c95f7002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414495527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.414495527
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2680095843
Short name T1124
Test name
Test status
Simulation time 50151491 ps
CPU time 0.76 seconds
Started Jul 29 05:08:41 PM PDT 24
Finished Jul 29 05:08:42 PM PDT 24
Peak memory 203880 kb
Host smart-01eca7f4-f3c1-4950-b636-4ebd68faa6d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680095843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
680095843
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3976198838
Short name T1041
Test name
Test status
Simulation time 702200108 ps
CPU time 1.87 seconds
Started Jul 29 05:08:10 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 215084 kb
Host smart-33a6dab0-c008-4eb9-9429-fbdf27136dc1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976198838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3976198838
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2544267928
Short name T1069
Test name
Test status
Simulation time 36410273 ps
CPU time 0.68 seconds
Started Jul 29 05:08:01 PM PDT 24
Finished Jul 29 05:08:01 PM PDT 24
Peak memory 203840 kb
Host smart-9f2cf7bc-7841-4a9c-8d18-838e690a842b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544267928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2544267928
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2217961494
Short name T1086
Test name
Test status
Simulation time 318806570 ps
CPU time 4.34 seconds
Started Jul 29 05:08:00 PM PDT 24
Finished Jul 29 05:08:04 PM PDT 24
Peak memory 214992 kb
Host smart-b40c41a4-fc40-45bb-94ea-b1e859b4bb04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217961494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2217961494
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1460679220
Short name T1078
Test name
Test status
Simulation time 178066603 ps
CPU time 2.47 seconds
Started Jul 29 05:08:09 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 215252 kb
Host smart-e54981ee-2ca1-4145-8b51-9b70eaa0b31a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460679220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
460679220
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4081192886
Short name T178
Test name
Test status
Simulation time 2100722718 ps
CPU time 14.36 seconds
Started Jul 29 05:08:21 PM PDT 24
Finished Jul 29 05:08:35 PM PDT 24
Peak memory 215136 kb
Host smart-f3d95794-d215-4cb9-96fb-86c2a65d19a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081192886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4081192886
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3401895383
Short name T1074
Test name
Test status
Simulation time 41196776 ps
CPU time 0.7 seconds
Started Jul 29 05:08:42 PM PDT 24
Finished Jul 29 05:08:42 PM PDT 24
Peak memory 203584 kb
Host smart-216e4dec-53e5-4e77-8ac4-4f6a6dfd2583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401895383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3401895383
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3935154731
Short name T1017
Test name
Test status
Simulation time 21546718 ps
CPU time 0.71 seconds
Started Jul 29 05:09:06 PM PDT 24
Finished Jul 29 05:09:07 PM PDT 24
Peak memory 203600 kb
Host smart-9f40e884-44e8-479b-b1d4-547f0b95c38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935154731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3935154731
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2692938975
Short name T1040
Test name
Test status
Simulation time 35257125 ps
CPU time 0.78 seconds
Started Jul 29 05:09:24 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 203860 kb
Host smart-d51185aa-5ff5-4243-825c-935dfd798e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692938975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2692938975
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3506508301
Short name T1022
Test name
Test status
Simulation time 31644790 ps
CPU time 0.75 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:09:35 PM PDT 24
Peak memory 203528 kb
Host smart-282dd65e-bf36-4ad1-8b71-fce27c13ca37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506508301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3506508301
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.554330184
Short name T1052
Test name
Test status
Simulation time 13751475 ps
CPU time 0.69 seconds
Started Jul 29 05:09:17 PM PDT 24
Finished Jul 29 05:09:18 PM PDT 24
Peak memory 203488 kb
Host smart-6159c64e-342f-400b-8e77-a0954a5669b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554330184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.554330184
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2235946064
Short name T1122
Test name
Test status
Simulation time 52339327 ps
CPU time 0.71 seconds
Started Jul 29 05:08:37 PM PDT 24
Finished Jul 29 05:08:37 PM PDT 24
Peak memory 203848 kb
Host smart-aeae28c4-527b-49aa-b19c-b7f273ba9da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235946064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2235946064
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2102571742
Short name T1085
Test name
Test status
Simulation time 12622027 ps
CPU time 0.74 seconds
Started Jul 29 05:09:07 PM PDT 24
Finished Jul 29 05:09:07 PM PDT 24
Peak memory 203600 kb
Host smart-82b60cc1-31e0-427c-99bb-c60a863cbbff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102571742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2102571742
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4152133831
Short name T1009
Test name
Test status
Simulation time 42205417 ps
CPU time 0.68 seconds
Started Jul 29 05:08:37 PM PDT 24
Finished Jul 29 05:08:38 PM PDT 24
Peak memory 203532 kb
Host smart-4b2192c7-ca3c-4a2b-afc0-d99aab79908f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152133831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4152133831
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3779480119
Short name T1028
Test name
Test status
Simulation time 234541600 ps
CPU time 0.81 seconds
Started Jul 29 05:09:30 PM PDT 24
Finished Jul 29 05:09:30 PM PDT 24
Peak memory 203568 kb
Host smart-ecdea17a-157f-47de-9243-f8f66f5aab28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779480119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3779480119
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3292817008
Short name T1055
Test name
Test status
Simulation time 34057674 ps
CPU time 0.76 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:04 PM PDT 24
Peak memory 203908 kb
Host smart-d75e22d2-aebb-468a-8c70-d12a505e90b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292817008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3292817008
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1617469654
Short name T1101
Test name
Test status
Simulation time 143140441 ps
CPU time 3.76 seconds
Started Jul 29 05:08:19 PM PDT 24
Finished Jul 29 05:08:22 PM PDT 24
Peak memory 218288 kb
Host smart-afd202ce-cc5d-4cf7-8d79-a6f33b432560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617469654 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1617469654
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1920548827
Short name T129
Test name
Test status
Simulation time 142761659 ps
CPU time 1.96 seconds
Started Jul 29 05:08:57 PM PDT 24
Finished Jul 29 05:08:59 PM PDT 24
Peak memory 215068 kb
Host smart-7a4f13dd-b8bd-4113-b922-876f9554f5e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920548827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
920548827
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2572294634
Short name T1027
Test name
Test status
Simulation time 16345836 ps
CPU time 0.68 seconds
Started Jul 29 05:08:24 PM PDT 24
Finished Jul 29 05:08:24 PM PDT 24
Peak memory 203596 kb
Host smart-add59a63-b4c2-433a-8425-09798f35658d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572294634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
572294634
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.148049299
Short name T1054
Test name
Test status
Simulation time 99774218 ps
CPU time 2.75 seconds
Started Jul 29 05:08:31 PM PDT 24
Finished Jul 29 05:08:34 PM PDT 24
Peak memory 214996 kb
Host smart-0b732568-5c9c-40ef-b2db-129437b822ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148049299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.148049299
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.422144242
Short name T107
Test name
Test status
Simulation time 1025917490 ps
CPU time 4.33 seconds
Started Jul 29 05:08:11 PM PDT 24
Finished Jul 29 05:08:15 PM PDT 24
Peak memory 215288 kb
Host smart-699eef54-ee8a-4da8-a62f-48902e77d637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422144242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.422144242
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1107152447
Short name T174
Test name
Test status
Simulation time 1990895242 ps
CPU time 21.22 seconds
Started Jul 29 05:08:30 PM PDT 24
Finished Jul 29 05:08:51 PM PDT 24
Peak memory 215628 kb
Host smart-c9b508c4-2030-4744-856a-841053b1bfd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107152447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1107152447
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.663647139
Short name T1036
Test name
Test status
Simulation time 187273064 ps
CPU time 3.06 seconds
Started Jul 29 05:08:53 PM PDT 24
Finished Jul 29 05:08:56 PM PDT 24
Peak memory 216612 kb
Host smart-2a49517f-3bb9-4119-92a9-22a4219106e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663647139 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.663647139
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.971015067
Short name T1008
Test name
Test status
Simulation time 56889539 ps
CPU time 0.76 seconds
Started Jul 29 05:08:45 PM PDT 24
Finished Jul 29 05:08:46 PM PDT 24
Peak memory 203888 kb
Host smart-516c0343-93d0-4638-a701-ab92ce323d57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971015067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.971015067
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1435178532
Short name T1076
Test name
Test status
Simulation time 182959436 ps
CPU time 3.18 seconds
Started Jul 29 05:08:48 PM PDT 24
Finished Jul 29 05:08:51 PM PDT 24
Peak memory 215112 kb
Host smart-7b9dd654-0b2f-48fd-a79b-300e3a1bceda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435178532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1435178532
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2779746473
Short name T112
Test name
Test status
Simulation time 49314492 ps
CPU time 2.87 seconds
Started Jul 29 05:08:17 PM PDT 24
Finished Jul 29 05:08:20 PM PDT 24
Peak memory 215112 kb
Host smart-62c50bc6-e099-4871-b79c-5b79e20a9d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779746473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
779746473
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1172714584
Short name T175
Test name
Test status
Simulation time 2549419781 ps
CPU time 14.49 seconds
Started Jul 29 05:08:53 PM PDT 24
Finished Jul 29 05:09:07 PM PDT 24
Peak memory 215484 kb
Host smart-acd00d35-f6d0-426a-8efb-7dba04305ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172714584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1172714584
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.328817817
Short name T117
Test name
Test status
Simulation time 159023566 ps
CPU time 4.04 seconds
Started Jul 29 05:08:09 PM PDT 24
Finished Jul 29 05:08:14 PM PDT 24
Peak memory 216960 kb
Host smart-a6152f86-6c54-41e0-892b-1bf93b04f16e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328817817 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.328817817
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3225566925
Short name T1129
Test name
Test status
Simulation time 67728368 ps
CPU time 1.97 seconds
Started Jul 29 05:08:10 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 215056 kb
Host smart-270eddbf-03bd-4aae-896e-13b58107d6e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225566925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
225566925
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3114940075
Short name T1031
Test name
Test status
Simulation time 31731759 ps
CPU time 0.76 seconds
Started Jul 29 05:08:08 PM PDT 24
Finished Jul 29 05:08:09 PM PDT 24
Peak memory 202720 kb
Host smart-cc31b815-f42f-41dd-a335-1c2d5a05fe0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114940075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
114940075
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2498418639
Short name T1082
Test name
Test status
Simulation time 1061582821 ps
CPU time 4.04 seconds
Started Jul 29 05:08:31 PM PDT 24
Finished Jul 29 05:08:35 PM PDT 24
Peak memory 215060 kb
Host smart-c6660562-a39c-42a3-b156-55ab434f15b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498418639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2498418639
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1842855760
Short name T1056
Test name
Test status
Simulation time 1394130859 ps
CPU time 7.95 seconds
Started Jul 29 05:08:08 PM PDT 24
Finished Jul 29 05:08:16 PM PDT 24
Peak memory 214328 kb
Host smart-78594847-db4c-4d38-9ac4-105e82287cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842855760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1842855760
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4060016354
Short name T1033
Test name
Test status
Simulation time 214346180 ps
CPU time 1.69 seconds
Started Jul 29 05:08:10 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 215124 kb
Host smart-fbc73395-946e-41c5-b972-94a459be963c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060016354 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4060016354
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2767288892
Short name T133
Test name
Test status
Simulation time 32133329 ps
CPU time 1.93 seconds
Started Jul 29 05:08:10 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 206768 kb
Host smart-a90089f2-9c68-4da8-ae2b-4737c8861be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767288892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
767288892
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2008541883
Short name T1042
Test name
Test status
Simulation time 57731638 ps
CPU time 0.71 seconds
Started Jul 29 05:08:24 PM PDT 24
Finished Jul 29 05:08:24 PM PDT 24
Peak memory 203532 kb
Host smart-10e51782-681e-4b3b-9e98-f0edcb2509b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008541883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
008541883
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4114641205
Short name T1077
Test name
Test status
Simulation time 62683842 ps
CPU time 3.52 seconds
Started Jul 29 05:08:53 PM PDT 24
Finished Jul 29 05:08:57 PM PDT 24
Peak memory 215144 kb
Host smart-d1937ed3-0521-4e4f-bd20-27510d16f36f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114641205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4114641205
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4283539067
Short name T111
Test name
Test status
Simulation time 65250403 ps
CPU time 1.82 seconds
Started Jul 29 05:09:27 PM PDT 24
Finished Jul 29 05:09:29 PM PDT 24
Peak memory 215172 kb
Host smart-1001e3fa-b920-4b14-839e-7821af5ae60c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283539067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
283539067
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3772910666
Short name T177
Test name
Test status
Simulation time 912557490 ps
CPU time 21.98 seconds
Started Jul 29 05:08:56 PM PDT 24
Finished Jul 29 05:09:19 PM PDT 24
Peak memory 215116 kb
Host smart-1aafed03-84b8-4326-9243-fbe91c063bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772910666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3772910666
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.58192972
Short name T120
Test name
Test status
Simulation time 247383029 ps
CPU time 4.31 seconds
Started Jul 29 05:08:41 PM PDT 24
Finished Jul 29 05:08:45 PM PDT 24
Peak memory 217356 kb
Host smart-4e760916-e526-44ff-b682-2256818d9990
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58192972 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.58192972
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4113346799
Short name T1067
Test name
Test status
Simulation time 312411592 ps
CPU time 2.29 seconds
Started Jul 29 05:08:48 PM PDT 24
Finished Jul 29 05:08:51 PM PDT 24
Peak memory 215032 kb
Host smart-76a0e393-41fe-44ca-ab9e-35565a84695e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113346799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
113346799
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1010426732
Short name T1099
Test name
Test status
Simulation time 29969993 ps
CPU time 0.7 seconds
Started Jul 29 05:08:31 PM PDT 24
Finished Jul 29 05:08:32 PM PDT 24
Peak memory 203896 kb
Host smart-4d54bc53-0084-4851-9952-0c89415fc4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010426732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
010426732
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2471769063
Short name T149
Test name
Test status
Simulation time 145164105 ps
CPU time 2.03 seconds
Started Jul 29 05:08:09 PM PDT 24
Finished Jul 29 05:08:11 PM PDT 24
Peak memory 215572 kb
Host smart-91d310ab-22b0-44ed-9d6c-2109f03c5e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471769063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2471769063
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2258330315
Short name T1117
Test name
Test status
Simulation time 80324369 ps
CPU time 2.18 seconds
Started Jul 29 05:09:24 PM PDT 24
Finished Jul 29 05:09:26 PM PDT 24
Peak memory 215376 kb
Host smart-575b1af9-d3dd-4935-ad68-f13d141d0495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258330315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
258330315
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3876385457
Short name T181
Test name
Test status
Simulation time 290463970 ps
CPU time 8.06 seconds
Started Jul 29 05:08:32 PM PDT 24
Finished Jul 29 05:08:41 PM PDT 24
Peak memory 215068 kb
Host smart-4167b32f-e282-4fe0-b84c-99a70dec4c98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876385457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3876385457
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.326520522
Short name T972
Test name
Test status
Simulation time 38226328 ps
CPU time 0.73 seconds
Started Jul 29 05:09:05 PM PDT 24
Finished Jul 29 05:09:06 PM PDT 24
Peak memory 205432 kb
Host smart-903900f2-ffd0-49be-babc-84a1c6f940a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326520522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.326520522
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3425411669
Short name T943
Test name
Test status
Simulation time 211526866 ps
CPU time 3.34 seconds
Started Jul 29 05:08:46 PM PDT 24
Finished Jul 29 05:08:49 PM PDT 24
Peak memory 233104 kb
Host smart-6e5347ae-57b9-43e7-ae90-2015e4fda8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425411669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3425411669
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2877992132
Short name T656
Test name
Test status
Simulation time 19504599 ps
CPU time 0.8 seconds
Started Jul 29 05:08:44 PM PDT 24
Finished Jul 29 05:08:45 PM PDT 24
Peak memory 207256 kb
Host smart-84b7e26e-69bf-4c6b-91c9-32d77e55d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877992132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2877992132
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1829122174
Short name T189
Test name
Test status
Simulation time 24433255415 ps
CPU time 58.8 seconds
Started Jul 29 05:08:44 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 233192 kb
Host smart-31f04ec0-6ce8-4234-8939-47262e9c6710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829122174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1829122174
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3455030429
Short name T650
Test name
Test status
Simulation time 13252552130 ps
CPU time 102.12 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:11:16 PM PDT 24
Peak memory 250648 kb
Host smart-1211fb33-a851-45bf-bbd5-ce6493853bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455030429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3455030429
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.756007088
Short name T809
Test name
Test status
Simulation time 9821694993 ps
CPU time 9.36 seconds
Started Jul 29 05:09:02 PM PDT 24
Finished Jul 29 05:09:11 PM PDT 24
Peak memory 238372 kb
Host smart-58b8ba76-cd51-4257-8ee9-bcc6c3e527fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756007088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.756007088
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2547973715
Short name T44
Test name
Test status
Simulation time 87377210398 ps
CPU time 109.49 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:11:31 PM PDT 24
Peak memory 249480 kb
Host smart-cd7afd2e-d756-4d97-bd38-c8772dc047a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547973715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2547973715
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4076754892
Short name T435
Test name
Test status
Simulation time 2090930173 ps
CPU time 24.19 seconds
Started Jul 29 05:08:58 PM PDT 24
Finished Jul 29 05:09:23 PM PDT 24
Peak memory 224852 kb
Host smart-435d19d9-ad57-467e-943d-5e0fc8999136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076754892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4076754892
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1920977562
Short name T272
Test name
Test status
Simulation time 2633684337 ps
CPU time 10.92 seconds
Started Jul 29 05:09:01 PM PDT 24
Finished Jul 29 05:09:12 PM PDT 24
Peak memory 224896 kb
Host smart-1ff32980-33bd-4c82-b710-93fd9c0cbe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920977562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1920977562
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1451633190
Short name T675
Test name
Test status
Simulation time 619543353 ps
CPU time 4.2 seconds
Started Jul 29 05:09:39 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 232992 kb
Host smart-224daef2-aa98-4561-a96d-764ed1fae42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451633190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1451633190
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2732547545
Short name T474
Test name
Test status
Simulation time 1947803153 ps
CPU time 13.68 seconds
Started Jul 29 05:09:02 PM PDT 24
Finished Jul 29 05:09:16 PM PDT 24
Peak memory 220556 kb
Host smart-1b6f850c-636b-4098-ad0c-4f7c7956a813
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2732547545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2732547545
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2598529273
Short name T15
Test name
Test status
Simulation time 1727537248 ps
CPU time 16.8 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:09:12 PM PDT 24
Peak memory 224864 kb
Host smart-517d6b57-3a26-49a0-b111-c9ab52bccf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598529273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2598529273
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3972435715
Short name T986
Test name
Test status
Simulation time 942742134 ps
CPU time 12.5 seconds
Started Jul 29 05:09:02 PM PDT 24
Finished Jul 29 05:09:15 PM PDT 24
Peak memory 216548 kb
Host smart-2b5bfb85-57e9-43d2-8bef-a8a35ca234f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972435715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3972435715
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3406232970
Short name T459
Test name
Test status
Simulation time 23755241 ps
CPU time 0.73 seconds
Started Jul 29 05:08:40 PM PDT 24
Finished Jul 29 05:08:41 PM PDT 24
Peak memory 206032 kb
Host smart-ac175646-0572-41f5-9483-b5a62d293e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406232970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3406232970
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3451098350
Short name T349
Test name
Test status
Simulation time 426107330 ps
CPU time 2.22 seconds
Started Jul 29 05:08:41 PM PDT 24
Finished Jul 29 05:08:44 PM PDT 24
Peak memory 216556 kb
Host smart-b86d62a8-1368-47d5-b058-d8ac0321cb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451098350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3451098350
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3087708270
Short name T509
Test name
Test status
Simulation time 104148753 ps
CPU time 0.75 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:03 PM PDT 24
Peak memory 206216 kb
Host smart-b7b310f3-47d1-4ce7-9cd6-10cb32caac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087708270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3087708270
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4154106464
Short name T875
Test name
Test status
Simulation time 3098946992 ps
CPU time 6.71 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:09:02 PM PDT 24
Peak memory 233048 kb
Host smart-87ce9edf-4d5b-4894-ac81-c97b2c98802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154106464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4154106464
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.238264257
Short name T893
Test name
Test status
Simulation time 17289429 ps
CPU time 0.71 seconds
Started Jul 29 05:08:49 PM PDT 24
Finished Jul 29 05:08:50 PM PDT 24
Peak memory 205744 kb
Host smart-0016b593-f5f0-4875-bf5f-37f3c48e40ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238264257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.238264257
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2653615906
Short name T456
Test name
Test status
Simulation time 729052415 ps
CPU time 5.88 seconds
Started Jul 29 05:09:26 PM PDT 24
Finished Jul 29 05:09:32 PM PDT 24
Peak memory 224780 kb
Host smart-938cb57e-63d4-43b7-a362-6a9114a0c72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653615906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2653615906
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2577649696
Short name T449
Test name
Test status
Simulation time 124577356 ps
CPU time 0.78 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:09:20 PM PDT 24
Peak memory 205940 kb
Host smart-36210ef4-66af-45dd-a30e-9d890dd6b92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577649696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2577649696
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2285606507
Short name T799
Test name
Test status
Simulation time 75494842382 ps
CPU time 169.07 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:12:32 PM PDT 24
Peak memory 259040 kb
Host smart-1b29b049-b26a-45fa-b63c-3fc96f35c797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285606507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2285606507
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.23602164
Short name T600
Test name
Test status
Simulation time 7916896344 ps
CPU time 78.17 seconds
Started Jul 29 05:09:29 PM PDT 24
Finished Jul 29 05:10:47 PM PDT 24
Peak memory 255048 kb
Host smart-a6f12f32-d9c8-401f-825c-e434f156dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23602164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.23602164
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1108621713
Short name T730
Test name
Test status
Simulation time 57820152363 ps
CPU time 221.1 seconds
Started Jul 29 05:09:20 PM PDT 24
Finished Jul 29 05:13:01 PM PDT 24
Peak memory 249528 kb
Host smart-05253001-6bd6-4872-a14a-973985a146bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108621713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1108621713
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.999441923
Short name T183
Test name
Test status
Simulation time 3179969855 ps
CPU time 41.67 seconds
Started Jul 29 05:09:37 PM PDT 24
Finished Jul 29 05:10:19 PM PDT 24
Peak memory 249500 kb
Host smart-726f0ea6-62d1-4b1f-814e-551c4ebfca16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999441923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
999441923
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.48432820
Short name T905
Test name
Test status
Simulation time 648756207 ps
CPU time 7.81 seconds
Started Jul 29 05:09:20 PM PDT 24
Finished Jul 29 05:09:28 PM PDT 24
Peak memory 224884 kb
Host smart-03478512-c4b2-4f76-a827-c969c60911e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48432820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.48432820
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.881913704
Short name T608
Test name
Test status
Simulation time 5199852760 ps
CPU time 15.72 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:09:58 PM PDT 24
Peak memory 234740 kb
Host smart-eda28d6b-fb5b-4d4a-b9b4-0ea369067b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881913704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.881913704
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2469063926
Short name T478
Test name
Test status
Simulation time 831180099 ps
CPU time 5.86 seconds
Started Jul 29 05:09:15 PM PDT 24
Finished Jul 29 05:09:21 PM PDT 24
Peak memory 233000 kb
Host smart-af142072-d222-43c9-8a37-cac5de705156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469063926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2469063926
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.345238314
Short name T499
Test name
Test status
Simulation time 110958221 ps
CPU time 2.54 seconds
Started Jul 29 05:09:08 PM PDT 24
Finished Jul 29 05:09:11 PM PDT 24
Peak memory 232656 kb
Host smart-4f50579a-19be-456c-8426-e037edcec57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345238314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.345238314
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1271661286
Short name T374
Test name
Test status
Simulation time 1979382631 ps
CPU time 5.33 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 223512 kb
Host smart-e3436973-977f-4505-b64d-31595dfa6740
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1271661286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1271661286
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1071984154
Short name T71
Test name
Test status
Simulation time 90557866 ps
CPU time 1.11 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:09:39 PM PDT 24
Peak memory 236236 kb
Host smart-1cfde7bf-f727-4869-ba53-236cc210817e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071984154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1071984154
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1883591104
Short name T988
Test name
Test status
Simulation time 46445919068 ps
CPU time 321.56 seconds
Started Jul 29 05:09:32 PM PDT 24
Finished Jul 29 05:14:54 PM PDT 24
Peak memory 265556 kb
Host smart-e575ce78-a181-4063-959c-5497bb1797f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883591104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1883591104
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3769087802
Short name T357
Test name
Test status
Simulation time 260608688 ps
CPU time 1.76 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 216708 kb
Host smart-5e4e24c4-2fe2-420b-8867-1c46dde2d703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769087802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3769087802
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1291788604
Short name T312
Test name
Test status
Simulation time 958422063 ps
CPU time 7.51 seconds
Started Jul 29 05:09:06 PM PDT 24
Finished Jul 29 05:09:13 PM PDT 24
Peak memory 216552 kb
Host smart-390c2228-8e4b-429d-8585-470a54d55212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291788604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1291788604
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2218432865
Short name T947
Test name
Test status
Simulation time 1789458226 ps
CPU time 3.63 seconds
Started Jul 29 05:08:50 PM PDT 24
Finished Jul 29 05:08:54 PM PDT 24
Peak memory 216504 kb
Host smart-eddf6a81-8c24-4df9-b7f6-46d68800f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218432865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2218432865
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.720416743
Short name T702
Test name
Test status
Simulation time 20978627 ps
CPU time 0.75 seconds
Started Jul 29 05:09:16 PM PDT 24
Finished Jul 29 05:09:17 PM PDT 24
Peak memory 206300 kb
Host smart-779fb0cc-8617-4303-a439-67699031dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720416743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.720416743
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3077787862
Short name T669
Test name
Test status
Simulation time 127049204 ps
CPU time 2.43 seconds
Started Jul 29 05:09:26 PM PDT 24
Finished Jul 29 05:09:28 PM PDT 24
Peak memory 232740 kb
Host smart-a5f083e7-a29d-498e-b700-680cbe8a6ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077787862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3077787862
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.488646267
Short name T494
Test name
Test status
Simulation time 41716818 ps
CPU time 0.74 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:09:58 PM PDT 24
Peak memory 205692 kb
Host smart-bb90ec9a-2641-42dd-a9b7-cbfd2f6ad8cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488646267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.488646267
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1596976879
Short name T707
Test name
Test status
Simulation time 274223175 ps
CPU time 2.34 seconds
Started Jul 29 05:09:52 PM PDT 24
Finished Jul 29 05:09:54 PM PDT 24
Peak memory 233060 kb
Host smart-53bbd3c2-a4f7-4a1c-b105-aedfe7b15eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596976879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1596976879
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2833305361
Short name T316
Test name
Test status
Simulation time 46857702 ps
CPU time 0.77 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:09:58 PM PDT 24
Peak memory 207184 kb
Host smart-70326d18-4ea5-42f6-8ea8-0fe7c07698f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833305361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2833305361
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.166944249
Short name T495
Test name
Test status
Simulation time 12227223021 ps
CPU time 35.4 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:10:30 PM PDT 24
Peak memory 255096 kb
Host smart-2c6d0a8b-bb5e-443e-9d2a-d4e5968c2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166944249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.166944249
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2298051437
Short name T248
Test name
Test status
Simulation time 21808230518 ps
CPU time 130.8 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:12:08 PM PDT 24
Peak memory 272900 kb
Host smart-e4142751-09a9-4ea8-b4ed-792c49ec9829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298051437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2298051437
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2823476426
Short name T368
Test name
Test status
Simulation time 3697433652 ps
CPU time 18.83 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:10:17 PM PDT 24
Peak memory 218028 kb
Host smart-66c602ca-1849-4cb4-b8bb-7aadefae0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823476426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2823476426
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.607990689
Short name T155
Test name
Test status
Simulation time 507515961 ps
CPU time 10.95 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:10:02 PM PDT 24
Peak memory 233012 kb
Host smart-06805ce4-479d-418b-b90d-e9c90b6b885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607990689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.607990689
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2898159261
Short name T93
Test name
Test status
Simulation time 721439783 ps
CPU time 4.59 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 224848 kb
Host smart-af84696e-51fb-438b-99f5-a8d76269ac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898159261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2898159261
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.213658395
Short name T236
Test name
Test status
Simulation time 270672011 ps
CPU time 2.73 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:09:54 PM PDT 24
Peak memory 224736 kb
Host smart-e842fc0c-13d0-4f81-83bc-37757fea7d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213658395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.213658395
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2057409880
Short name T687
Test name
Test status
Simulation time 62881404 ps
CPU time 2.28 seconds
Started Jul 29 05:09:53 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 232772 kb
Host smart-cfa942a9-b23c-4eca-8f3e-2a034dbde74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057409880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2057409880
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3117955614
Short name T693
Test name
Test status
Simulation time 9766938088 ps
CPU time 12.06 seconds
Started Jul 29 05:09:52 PM PDT 24
Finished Jul 29 05:10:04 PM PDT 24
Peak memory 233092 kb
Host smart-2b44e440-159d-479e-9505-703da9b72dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117955614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3117955614
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3317633895
Short name T616
Test name
Test status
Simulation time 535611054 ps
CPU time 6.39 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:09:58 PM PDT 24
Peak memory 223472 kb
Host smart-63cc603e-2dba-44e5-bab1-364627bda2d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3317633895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3317633895
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2342718046
Short name T920
Test name
Test status
Simulation time 285612228 ps
CPU time 0.96 seconds
Started Jul 29 05:10:00 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 207304 kb
Host smart-a060502d-87b2-4ef9-8bb7-384d4f50b7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342718046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2342718046
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1451952227
Short name T528
Test name
Test status
Simulation time 3292889456 ps
CPU time 7.89 seconds
Started Jul 29 05:09:54 PM PDT 24
Finished Jul 29 05:10:02 PM PDT 24
Peak memory 216856 kb
Host smart-5af06180-96ea-4ddb-bf24-7a41713a3b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451952227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1451952227
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.343691007
Short name T646
Test name
Test status
Simulation time 469329550 ps
CPU time 3.42 seconds
Started Jul 29 05:09:56 PM PDT 24
Finished Jul 29 05:09:59 PM PDT 24
Peak memory 216588 kb
Host smart-10fecf9a-ca5b-40dc-8acf-4728be376a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343691007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.343691007
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4198366961
Short name T373
Test name
Test status
Simulation time 147170482 ps
CPU time 2.09 seconds
Started Jul 29 05:09:54 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 216500 kb
Host smart-9f8e0e8e-5fef-4eed-87f2-3c1c3ac6af1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198366961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4198366961
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.870016687
Short name T59
Test name
Test status
Simulation time 175229688 ps
CPU time 0.79 seconds
Started Jul 29 05:09:50 PM PDT 24
Finished Jul 29 05:09:52 PM PDT 24
Peak memory 206264 kb
Host smart-87eef8f4-14e6-4ef1-b508-a6376ceda9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870016687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.870016687
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3511638195
Short name T262
Test name
Test status
Simulation time 131517797 ps
CPU time 2.27 seconds
Started Jul 29 05:09:53 PM PDT 24
Finished Jul 29 05:09:55 PM PDT 24
Peak memory 233112 kb
Host smart-62ad8123-66e8-49b1-b4a7-3530f2b00eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511638195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3511638195
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1440723214
Short name T915
Test name
Test status
Simulation time 62747111 ps
CPU time 0.73 seconds
Started Jul 29 05:10:01 PM PDT 24
Finished Jul 29 05:10:02 PM PDT 24
Peak memory 205712 kb
Host smart-e10475b4-5a52-422b-8f74-90704ff92b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440723214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1440723214
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1980213628
Short name T750
Test name
Test status
Simulation time 3194175389 ps
CPU time 6.17 seconds
Started Jul 29 05:09:56 PM PDT 24
Finished Jul 29 05:10:02 PM PDT 24
Peak memory 224884 kb
Host smart-7017d99d-6db4-4833-beca-89256f674b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980213628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1980213628
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2379952786
Short name T63
Test name
Test status
Simulation time 71567200 ps
CPU time 0.8 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 206932 kb
Host smart-8e84e7eb-0b76-4296-bace-1fe926fef7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379952786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2379952786
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.812837652
Short name T514
Test name
Test status
Simulation time 28155163034 ps
CPU time 220.75 seconds
Started Jul 29 05:09:56 PM PDT 24
Finished Jul 29 05:13:37 PM PDT 24
Peak memory 253876 kb
Host smart-e220dd77-42cd-4c57-a002-9e77e4167ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812837652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.812837652
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3634608609
Short name T53
Test name
Test status
Simulation time 12248336449 ps
CPU time 88.41 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:11:26 PM PDT 24
Peak memory 256456 kb
Host smart-8c96d96d-b3e0-4361-8b81-2d2ef2e09179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634608609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3634608609
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2224135569
Short name T299
Test name
Test status
Simulation time 78310762428 ps
CPU time 70.38 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:11:08 PM PDT 24
Peak memory 249700 kb
Host smart-f5b389a6-5216-468c-b80b-dca9f11559c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224135569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2224135569
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3059089169
Short name T767
Test name
Test status
Simulation time 42655293554 ps
CPU time 258.44 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:14:15 PM PDT 24
Peak memory 249876 kb
Host smart-d52ca32b-fd00-4ff8-af9d-36b73d8c53e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059089169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3059089169
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.267319021
Short name T945
Test name
Test status
Simulation time 504119881 ps
CPU time 5.1 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 232940 kb
Host smart-8c694a42-a302-42bc-ae56-662677eed700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267319021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.267319021
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3288456609
Short name T847
Test name
Test status
Simulation time 158984210 ps
CPU time 2.44 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:10:00 PM PDT 24
Peak memory 224028 kb
Host smart-4b0fff50-ab79-465e-9e8e-62ba965c4c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288456609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3288456609
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3170025585
Short name T473
Test name
Test status
Simulation time 2443587696 ps
CPU time 4.05 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:10:00 PM PDT 24
Peak memory 224796 kb
Host smart-2a1ffc46-9bd9-4118-8780-6722fbfc978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170025585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3170025585
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1874635928
Short name T154
Test name
Test status
Simulation time 4989452476 ps
CPU time 5.59 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 223708 kb
Host smart-9c9673c3-6bfd-45dc-970d-844c193354aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1874635928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1874635928
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.475406701
Short name T942
Test name
Test status
Simulation time 52718674 ps
CPU time 0.95 seconds
Started Jul 29 05:10:00 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 207848 kb
Host smart-229084b8-e023-4a7e-83b3-e842cc64565e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475406701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.475406701
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3947143080
Short name T641
Test name
Test status
Simulation time 19565016454 ps
CPU time 50.29 seconds
Started Jul 29 05:09:56 PM PDT 24
Finished Jul 29 05:10:46 PM PDT 24
Peak memory 216688 kb
Host smart-05f77707-a7ee-4135-a0ef-9ee8cc341c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947143080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3947143080
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2891326769
Short name T591
Test name
Test status
Simulation time 16516318398 ps
CPU time 23.96 seconds
Started Jul 29 05:09:59 PM PDT 24
Finished Jul 29 05:10:23 PM PDT 24
Peak memory 216684 kb
Host smart-b8c90852-14e8-4229-aa59-d6794e58c26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891326769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2891326769
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2312925391
Short name T751
Test name
Test status
Simulation time 20733365 ps
CPU time 1.28 seconds
Started Jul 29 05:09:58 PM PDT 24
Finished Jul 29 05:09:59 PM PDT 24
Peak memory 216544 kb
Host smart-d3f94550-6a94-43cc-862f-fe76895ae5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312925391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2312925391
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.608090357
Short name T699
Test name
Test status
Simulation time 160616843 ps
CPU time 0.92 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 206200 kb
Host smart-ab20a389-4a34-45d5-8919-cb6eb69bcb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608090357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.608090357
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.914599917
Short name T457
Test name
Test status
Simulation time 9357209314 ps
CPU time 18.9 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:10:14 PM PDT 24
Peak memory 249544 kb
Host smart-bddb2683-a0fa-4c93-94fc-9e666b7f5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914599917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.914599917
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3969020828
Short name T144
Test name
Test status
Simulation time 812622548 ps
CPU time 3.64 seconds
Started Jul 29 05:10:02 PM PDT 24
Finished Jul 29 05:10:06 PM PDT 24
Peak memory 224860 kb
Host smart-d559aebe-f297-47a4-81ab-69133de5ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969020828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3969020828
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1264609849
Short name T380
Test name
Test status
Simulation time 45280267 ps
CPU time 0.79 seconds
Started Jul 29 05:10:01 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 205844 kb
Host smart-14f1e94d-fa37-4a12-ae14-d209617438c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264609849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1264609849
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1063935642
Short name T218
Test name
Test status
Simulation time 51947005461 ps
CPU time 385.79 seconds
Started Jul 29 05:10:02 PM PDT 24
Finished Jul 29 05:16:28 PM PDT 24
Peak memory 265068 kb
Host smart-db5dced7-237c-4612-96d9-413b61bec4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063935642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1063935642
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.603697533
Short name T148
Test name
Test status
Simulation time 28061371811 ps
CPU time 284.39 seconds
Started Jul 29 05:10:02 PM PDT 24
Finished Jul 29 05:14:47 PM PDT 24
Peak memory 250420 kb
Host smart-0db85d18-5191-4bcc-bb28-42a5349a2b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603697533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.603697533
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4192871084
Short name T878
Test name
Test status
Simulation time 10010803653 ps
CPU time 47.16 seconds
Started Jul 29 05:10:03 PM PDT 24
Finished Jul 29 05:10:51 PM PDT 24
Peak memory 218024 kb
Host smart-d842c480-fb36-4f28-bb4a-0661aeb84f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192871084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4192871084
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3569466449
Short name T2
Test name
Test status
Simulation time 209941843 ps
CPU time 3.05 seconds
Started Jul 29 05:10:06 PM PDT 24
Finished Jul 29 05:10:09 PM PDT 24
Peak memory 233036 kb
Host smart-1eea0289-f79b-445c-8c5d-db2190d32280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569466449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3569466449
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3566064653
Short name T230
Test name
Test status
Simulation time 195848081061 ps
CPU time 404.44 seconds
Started Jul 29 05:10:05 PM PDT 24
Finished Jul 29 05:16:50 PM PDT 24
Peak memory 273052 kb
Host smart-c5036cbe-5794-4281-92fd-f84ea11b062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566064653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3566064653
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3735614327
Short name T211
Test name
Test status
Simulation time 8499713664 ps
CPU time 9.49 seconds
Started Jul 29 05:10:04 PM PDT 24
Finished Jul 29 05:10:13 PM PDT 24
Peak memory 224932 kb
Host smart-82f12cd8-baca-4cee-a9d6-40d02d8df081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735614327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3735614327
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1318800806
Short name T105
Test name
Test status
Simulation time 5015493366 ps
CPU time 21.68 seconds
Started Jul 29 05:10:02 PM PDT 24
Finished Jul 29 05:10:24 PM PDT 24
Peak memory 249540 kb
Host smart-74cd5d18-1000-485d-b371-e9723d4a0a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318800806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1318800806
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.48896485
Short name T758
Test name
Test status
Simulation time 1292317366 ps
CPU time 4.03 seconds
Started Jul 29 05:10:01 PM PDT 24
Finished Jul 29 05:10:05 PM PDT 24
Peak memory 224748 kb
Host smart-8d9cfa68-7423-413d-b64d-c388bef586e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48896485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.48896485
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3705868469
Short name T60
Test name
Test status
Simulation time 491077839 ps
CPU time 8.22 seconds
Started Jul 29 05:10:02 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 222340 kb
Host smart-388952a7-6297-47a4-b9ac-b2a9110a39c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705868469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3705868469
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2609542049
Short name T609
Test name
Test status
Simulation time 18136113195 ps
CPU time 29.72 seconds
Started Jul 29 05:10:00 PM PDT 24
Finished Jul 29 05:10:30 PM PDT 24
Peak memory 216688 kb
Host smart-2ec10cf0-f48f-4ad0-b293-d3c201566590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609542049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2609542049
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2552876620
Short name T326
Test name
Test status
Simulation time 2321052873 ps
CPU time 5.18 seconds
Started Jul 29 05:09:58 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 216696 kb
Host smart-f56c2c8c-66d6-460b-8187-eac1fbc28bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552876620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2552876620
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3737607096
Short name T27
Test name
Test status
Simulation time 25300311 ps
CPU time 0.83 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 207320 kb
Host smart-b4f7dfdb-1cf3-4110-9bfc-c3fafb26ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737607096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3737607096
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.978761329
Short name T311
Test name
Test status
Simulation time 100968103 ps
CPU time 0.71 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:09:58 PM PDT 24
Peak memory 206212 kb
Host smart-92b5adc8-9b71-48a7-aa52-57e1f2873d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978761329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.978761329
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1467723036
Short name T445
Test name
Test status
Simulation time 167329970 ps
CPU time 2.44 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:12 PM PDT 24
Peak memory 224812 kb
Host smart-d227da18-a576-4dce-802d-4f7aea61d4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467723036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1467723036
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1255798143
Short name T573
Test name
Test status
Simulation time 24758325 ps
CPU time 0.71 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 205128 kb
Host smart-a1c39a92-7ecd-4735-9ffa-69903e52ceb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255798143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1255798143
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.530277418
Short name T674
Test name
Test status
Simulation time 777485371 ps
CPU time 4.01 seconds
Started Jul 29 05:10:07 PM PDT 24
Finished Jul 29 05:10:11 PM PDT 24
Peak memory 232996 kb
Host smart-855c36a6-9e05-49e9-aca7-e04f1361e370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530277418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.530277418
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1759169461
Short name T399
Test name
Test status
Simulation time 54668008 ps
CPU time 0.8 seconds
Started Jul 29 05:10:02 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 205876 kb
Host smart-fad97995-0ac9-4653-8a81-ef3fcc8071c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759169461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1759169461
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4236331947
Short name T201
Test name
Test status
Simulation time 51008577610 ps
CPU time 131.52 seconds
Started Jul 29 05:10:08 PM PDT 24
Finished Jul 29 05:12:19 PM PDT 24
Peak memory 256224 kb
Host smart-b60e020b-6d77-4eee-b62f-2e09486072a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236331947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4236331947
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2026015378
Short name T34
Test name
Test status
Simulation time 140140130684 ps
CPU time 348.58 seconds
Started Jul 29 05:10:06 PM PDT 24
Finished Jul 29 05:15:55 PM PDT 24
Peak memory 257752 kb
Host smart-4ef0abb4-0c31-47c5-bd30-cd1d4c0ebf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026015378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2026015378
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1486541444
Short name T290
Test name
Test status
Simulation time 18363884654 ps
CPU time 43.66 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:53 PM PDT 24
Peak memory 249504 kb
Host smart-ddbcb139-25b7-47a2-a138-1d0e85a7a0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486541444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1486541444
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1228778041
Short name T384
Test name
Test status
Simulation time 881552664 ps
CPU time 2.56 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:12 PM PDT 24
Peak memory 233084 kb
Host smart-d16f9818-12f2-4dea-a1e2-d9f92b0d0efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228778041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1228778041
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2043995269
Short name T779
Test name
Test status
Simulation time 2132614042 ps
CPU time 7.52 seconds
Started Jul 29 05:10:11 PM PDT 24
Finished Jul 29 05:10:18 PM PDT 24
Peak memory 230080 kb
Host smart-f71aa898-04da-44e8-94bd-e244dc14a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043995269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2043995269
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.120535148
Short name T250
Test name
Test status
Simulation time 307503424 ps
CPU time 2.31 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:12 PM PDT 24
Peak memory 224804 kb
Host smart-3b1f4e0d-41b7-405d-8a8e-d6aed95f5229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120535148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.120535148
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1899643829
Short name T788
Test name
Test status
Simulation time 370884609 ps
CPU time 2.85 seconds
Started Jul 29 05:10:08 PM PDT 24
Finished Jul 29 05:10:11 PM PDT 24
Peak memory 224884 kb
Host smart-f5610636-ad11-48b6-9fed-7ed9a9b1a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899643829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1899643829
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.148526295
Short name T922
Test name
Test status
Simulation time 677396818 ps
CPU time 3.72 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:13 PM PDT 24
Peak memory 220640 kb
Host smart-fdd7a3cf-c2f6-4729-9515-c307fb122314
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=148526295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.148526295
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2405130891
Short name T284
Test name
Test status
Simulation time 17977018172 ps
CPU time 113.6 seconds
Started Jul 29 05:10:08 PM PDT 24
Finished Jul 29 05:12:02 PM PDT 24
Peak memory 254820 kb
Host smart-d7795222-de8a-4f7d-98bb-d17b0ac881eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405130891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2405130891
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.295272170
Short name T925
Test name
Test status
Simulation time 679565308 ps
CPU time 10.89 seconds
Started Jul 29 05:10:07 PM PDT 24
Finished Jul 29 05:10:18 PM PDT 24
Peak memory 216672 kb
Host smart-adacbe8c-56fc-468a-9bec-c8a08b87e693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295272170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.295272170
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.256306469
Short name T882
Test name
Test status
Simulation time 2701096557 ps
CPU time 5.44 seconds
Started Jul 29 05:10:11 PM PDT 24
Finished Jul 29 05:10:16 PM PDT 24
Peak memory 216524 kb
Host smart-78bfa4b1-daff-4fa6-ad7f-bce071ba9200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256306469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.256306469
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.417583539
Short name T418
Test name
Test status
Simulation time 72859087 ps
CPU time 1.1 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:11 PM PDT 24
Peak memory 208184 kb
Host smart-494e0c43-ccc9-4901-b210-f557c6256ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417583539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.417583539
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.445201663
Short name T598
Test name
Test status
Simulation time 111516406 ps
CPU time 0.82 seconds
Started Jul 29 05:10:07 PM PDT 24
Finished Jul 29 05:10:08 PM PDT 24
Peak memory 206268 kb
Host smart-8dca35d2-227d-40fb-94e6-98ae65abe1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445201663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.445201663
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1893411730
Short name T635
Test name
Test status
Simulation time 1800714381 ps
CPU time 12.64 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:22 PM PDT 24
Peak memory 249488 kb
Host smart-a1d94f36-5348-45ff-8a34-cbc7171ad4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893411730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1893411730
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3305032523
Short name T490
Test name
Test status
Simulation time 16304835 ps
CPU time 0.75 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:10:17 PM PDT 24
Peak memory 206144 kb
Host smart-7def7576-0365-4fcc-986b-0f87702f06e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305032523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3305032523
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.150014425
Short name T636
Test name
Test status
Simulation time 127931149 ps
CPU time 2.65 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:10:18 PM PDT 24
Peak memory 233012 kb
Host smart-eb035716-4df1-42a7-a4b3-4d3f23982908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150014425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.150014425
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1788920
Short name T547
Test name
Test status
Simulation time 21929308 ps
CPU time 0.81 seconds
Started Jul 29 05:10:08 PM PDT 24
Finished Jul 29 05:10:09 PM PDT 24
Peak memory 206940 kb
Host smart-8024ab49-d2ce-4fdb-ac2a-a93ab4566d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1788920
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4012744710
Short name T807
Test name
Test status
Simulation time 135803356676 ps
CPU time 299.92 seconds
Started Jul 29 05:10:17 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 264932 kb
Host smart-7820d4f6-a655-4031-a171-cf9d37e6d53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012744710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4012744710
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2502336084
Short name T574
Test name
Test status
Simulation time 38486480575 ps
CPU time 112.2 seconds
Started Jul 29 05:10:17 PM PDT 24
Finished Jul 29 05:12:09 PM PDT 24
Peak memory 255144 kb
Host smart-996943db-bd63-4a52-af50-9a8dfaeeb03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502336084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2502336084
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1500483517
Short name T273
Test name
Test status
Simulation time 8687268997 ps
CPU time 114.27 seconds
Started Jul 29 05:10:18 PM PDT 24
Finished Jul 29 05:12:13 PM PDT 24
Peak memory 252584 kb
Host smart-ec324625-324f-4271-a421-50943602c0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500483517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1500483517
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2130064928
Short name T571
Test name
Test status
Simulation time 1304119039 ps
CPU time 21.36 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:10:38 PM PDT 24
Peak memory 241204 kb
Host smart-1600cd7a-ce5f-498e-80e9-5d1725301715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130064928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2130064928
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.7266719
Short name T816
Test name
Test status
Simulation time 16215904223 ps
CPU time 70.63 seconds
Started Jul 29 05:10:17 PM PDT 24
Finished Jul 29 05:11:28 PM PDT 24
Peak memory 249756 kb
Host smart-a56a9105-bec1-4d26-afab-5201c3ac8395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7266719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.7266719
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2659587266
Short name T607
Test name
Test status
Simulation time 577664114 ps
CPU time 4.22 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:10:20 PM PDT 24
Peak memory 228308 kb
Host smart-cdb6a79c-6cb2-42b4-8627-9f08c6eb30e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659587266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2659587266
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1286681392
Short name T10
Test name
Test status
Simulation time 12238401480 ps
CPU time 120.85 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:12:17 PM PDT 24
Peak memory 241216 kb
Host smart-c4c9e866-52b0-4ad2-b166-a107bbd0aae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286681392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1286681392
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1042204554
Short name T940
Test name
Test status
Simulation time 478520162 ps
CPU time 5.51 seconds
Started Jul 29 05:10:15 PM PDT 24
Finished Jul 29 05:10:20 PM PDT 24
Peak memory 233096 kb
Host smart-1b3e83aa-5e53-4848-80f6-72270a3e1dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042204554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1042204554
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2801909316
Short name T634
Test name
Test status
Simulation time 463632185 ps
CPU time 2.36 seconds
Started Jul 29 05:10:08 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 224852 kb
Host smart-823337ee-2517-4b33-a87e-12354d62e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801909316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2801909316
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2661065459
Short name T995
Test name
Test status
Simulation time 568033250 ps
CPU time 7.56 seconds
Started Jul 29 05:10:18 PM PDT 24
Finished Jul 29 05:10:26 PM PDT 24
Peak memory 223416 kb
Host smart-b80e43f8-1c5b-46fd-86ef-3ab98c9ae9ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2661065459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2661065459
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2206666832
Short name T280
Test name
Test status
Simulation time 254351330863 ps
CPU time 679.4 seconds
Started Jul 29 05:10:15 PM PDT 24
Finished Jul 29 05:21:34 PM PDT 24
Peak memory 256824 kb
Host smart-6e9a9a5c-7b97-4742-bc63-dad4fb85c25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206666832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2206666832
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3878939500
Short name T761
Test name
Test status
Simulation time 7872166385 ps
CPU time 23.24 seconds
Started Jul 29 05:10:09 PM PDT 24
Finished Jul 29 05:10:32 PM PDT 24
Peak memory 216748 kb
Host smart-6e209d24-1c01-414c-81da-8c6628dc1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878939500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3878939500
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3829880004
Short name T429
Test name
Test status
Simulation time 8227398290 ps
CPU time 7.89 seconds
Started Jul 29 05:10:11 PM PDT 24
Finished Jul 29 05:10:19 PM PDT 24
Peak memory 216532 kb
Host smart-0a300757-0f5f-42e6-846e-f97de6760cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829880004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3829880004
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1631132306
Short name T825
Test name
Test status
Simulation time 36125087 ps
CPU time 0.82 seconds
Started Jul 29 05:10:10 PM PDT 24
Finished Jul 29 05:10:11 PM PDT 24
Peak memory 206880 kb
Host smart-b3b4242c-432d-4fde-bae9-e90808726628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631132306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1631132306
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.598081616
Short name T946
Test name
Test status
Simulation time 17422324 ps
CPU time 0.74 seconds
Started Jul 29 05:10:11 PM PDT 24
Finished Jul 29 05:10:12 PM PDT 24
Peak memory 206248 kb
Host smart-93ec3f5d-7b0f-4ebe-83dd-2b811660b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598081616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.598081616
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1704828226
Short name T745
Test name
Test status
Simulation time 790014377 ps
CPU time 2.93 seconds
Started Jul 29 05:10:19 PM PDT 24
Finished Jul 29 05:10:22 PM PDT 24
Peak memory 224916 kb
Host smart-0f75cedd-b229-4799-9ba1-fa9ee7ca2a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704828226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1704828226
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3237076133
Short name T781
Test name
Test status
Simulation time 12687395 ps
CPU time 0.69 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:22 PM PDT 24
Peak memory 205756 kb
Host smart-93e8ab9c-4382-47da-9128-38571d0353df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237076133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3237076133
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.435044298
Short name T755
Test name
Test status
Simulation time 508290049 ps
CPU time 4.01 seconds
Started Jul 29 05:10:23 PM PDT 24
Finished Jul 29 05:10:27 PM PDT 24
Peak memory 224748 kb
Host smart-44b2465c-f78f-445e-b40e-591f91a279aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435044298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.435044298
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3262169602
Short name T535
Test name
Test status
Simulation time 61030558 ps
CPU time 0.82 seconds
Started Jul 29 05:10:17 PM PDT 24
Finished Jul 29 05:10:17 PM PDT 24
Peak memory 206888 kb
Host smart-1863c6fc-0418-47fc-8453-127bc43bee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262169602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3262169602
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2949693304
Short name T173
Test name
Test status
Simulation time 60762387092 ps
CPU time 96.65 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:11:57 PM PDT 24
Peak memory 249468 kb
Host smart-b1b524d0-6aea-4739-b037-66347298fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949693304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2949693304
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2054420546
Short name T172
Test name
Test status
Simulation time 1364404922 ps
CPU time 22.96 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:44 PM PDT 24
Peak memory 236788 kb
Host smart-21599441-22ee-43e7-8e27-cece06c6a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054420546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2054420546
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.595992938
Short name T294
Test name
Test status
Simulation time 23760104455 ps
CPU time 99.3 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:12:00 PM PDT 24
Peak memory 249552 kb
Host smart-9f6f0e04-fed1-4eec-a38a-0bdf50438249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595992938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.595992938
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1316413538
Short name T784
Test name
Test status
Simulation time 2006997410 ps
CPU time 4.5 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:25 PM PDT 24
Peak memory 233048 kb
Host smart-9c700073-b3a0-47cb-8644-9a91d543165b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316413538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1316413538
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.966483289
Short name T651
Test name
Test status
Simulation time 17072511713 ps
CPU time 88.95 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:11:50 PM PDT 24
Peak memory 252240 kb
Host smart-fe0c9e91-5234-4d38-80f3-34f108f951e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966483289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.966483289
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4232175151
Short name T700
Test name
Test status
Simulation time 593021441 ps
CPU time 8.88 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:10:25 PM PDT 24
Peak memory 233016 kb
Host smart-c49d7904-cd4e-4507-b1b2-ad7951a37c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232175151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4232175151
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1509964949
Short name T765
Test name
Test status
Simulation time 782140755 ps
CPU time 8.85 seconds
Started Jul 29 05:10:18 PM PDT 24
Finished Jul 29 05:10:27 PM PDT 24
Peak memory 224780 kb
Host smart-13f6f2e2-bf96-44f6-b22e-eaafb9405196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509964949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1509964949
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1405557651
Short name T80
Test name
Test status
Simulation time 13654332165 ps
CPU time 19.13 seconds
Started Jul 29 05:10:15 PM PDT 24
Finished Jul 29 05:10:34 PM PDT 24
Peak memory 233160 kb
Host smart-047c5de9-46fc-429d-a3e9-12c0b28db411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405557651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1405557651
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1235811473
Short name T752
Test name
Test status
Simulation time 8168620901 ps
CPU time 24.55 seconds
Started Jul 29 05:10:15 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 224836 kb
Host smart-81006ee3-e0b3-4ade-850a-d55e40f827fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235811473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1235811473
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1331530701
Short name T877
Test name
Test status
Simulation time 746448569 ps
CPU time 10.26 seconds
Started Jul 29 05:10:20 PM PDT 24
Finished Jul 29 05:10:30 PM PDT 24
Peak memory 220680 kb
Host smart-00a3f477-867a-4124-8ff1-726f36c533db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331530701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1331530701
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3621215934
Short name T838
Test name
Test status
Simulation time 1957853683 ps
CPU time 27.23 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:48 PM PDT 24
Peak memory 233160 kb
Host smart-43501d47-4bbb-427a-9661-a96c88b3843f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621215934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3621215934
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3111886938
Short name T798
Test name
Test status
Simulation time 4970741199 ps
CPU time 29.67 seconds
Started Jul 29 05:10:18 PM PDT 24
Finished Jul 29 05:10:48 PM PDT 24
Peak memory 221072 kb
Host smart-4bd508cc-0a5f-4cb9-9049-c33f59533e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111886938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3111886938
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2009921560
Short name T141
Test name
Test status
Simulation time 26410139 ps
CPU time 0.96 seconds
Started Jul 29 05:10:16 PM PDT 24
Finished Jul 29 05:10:17 PM PDT 24
Peak memory 206196 kb
Host smart-a52d5644-8f1c-4571-97d4-7938f8700931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009921560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2009921560
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3494471338
Short name T768
Test name
Test status
Simulation time 25141380 ps
CPU time 1.07 seconds
Started Jul 29 05:10:14 PM PDT 24
Finished Jul 29 05:10:15 PM PDT 24
Peak memory 208216 kb
Host smart-4a3c1182-cc30-423b-83f3-cfffc3f47455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494471338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3494471338
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1134196881
Short name T531
Test name
Test status
Simulation time 153569870 ps
CPU time 0.85 seconds
Started Jul 29 05:10:17 PM PDT 24
Finished Jul 29 05:10:18 PM PDT 24
Peak memory 207264 kb
Host smart-6f7456b2-2c4a-4587-9964-0ffb369c5c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134196881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1134196881
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.159903163
Short name T410
Test name
Test status
Simulation time 4390176106 ps
CPU time 16.22 seconds
Started Jul 29 05:10:15 PM PDT 24
Finished Jul 29 05:10:31 PM PDT 24
Peak memory 233092 kb
Host smart-7dbfd6b2-6e8b-47fc-9b8d-5f383c2e609b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159903163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.159903163
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.452408226
Short name T387
Test name
Test status
Simulation time 19196931 ps
CPU time 0.69 seconds
Started Jul 29 05:10:26 PM PDT 24
Finished Jul 29 05:10:27 PM PDT 24
Peak memory 206136 kb
Host smart-ec770160-a973-4396-a1fe-9c477086ae04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452408226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.452408226
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.120301018
Short name T851
Test name
Test status
Simulation time 227939077 ps
CPU time 3.2 seconds
Started Jul 29 05:10:20 PM PDT 24
Finished Jul 29 05:10:23 PM PDT 24
Peak memory 233040 kb
Host smart-18c4a111-7e89-4da1-bf0c-9488c80b00f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120301018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.120301018
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2443180002
Short name T529
Test name
Test status
Simulation time 43932405 ps
CPU time 0.71 seconds
Started Jul 29 05:10:24 PM PDT 24
Finished Jul 29 05:10:25 PM PDT 24
Peak memory 207172 kb
Host smart-260e0a3b-2f2a-4c2f-8d4f-ddc4fa21ddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443180002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2443180002
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3025814180
Short name T746
Test name
Test status
Simulation time 12515921529 ps
CPU time 154.71 seconds
Started Jul 29 05:10:23 PM PDT 24
Finished Jul 29 05:12:58 PM PDT 24
Peak memory 256372 kb
Host smart-ba5a6afc-03cd-4dd6-8114-adddb6bee8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025814180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3025814180
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1432603339
Short name T926
Test name
Test status
Simulation time 12693687125 ps
CPU time 185.45 seconds
Started Jul 29 05:10:22 PM PDT 24
Finished Jul 29 05:13:28 PM PDT 24
Peak memory 264020 kb
Host smart-1847126a-95d3-4c2b-b742-41fd43ecca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432603339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1432603339
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3084194458
Short name T954
Test name
Test status
Simulation time 5133076963 ps
CPU time 42.92 seconds
Started Jul 29 05:10:20 PM PDT 24
Finished Jul 29 05:11:03 PM PDT 24
Peak memory 250572 kb
Host smart-87f2bd81-c8b6-4201-9481-7de7428c07c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084194458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3084194458
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1251372866
Short name T335
Test name
Test status
Simulation time 5171232514 ps
CPU time 19.52 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:41 PM PDT 24
Peak memory 241328 kb
Host smart-abf0dad3-83c1-4320-b95a-17af4be6e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251372866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1251372866
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3576888967
Short name T581
Test name
Test status
Simulation time 129044387413 ps
CPU time 209.82 seconds
Started Jul 29 05:10:18 PM PDT 24
Finished Jul 29 05:13:48 PM PDT 24
Peak memory 250644 kb
Host smart-f6a270a1-114e-4628-bd6f-146dd0f60d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576888967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3576888967
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1587641423
Short name T205
Test name
Test status
Simulation time 1235231430 ps
CPU time 12.35 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:34 PM PDT 24
Peak memory 224780 kb
Host smart-ef5867f1-12c3-450c-90f8-5a25bfa35654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587641423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1587641423
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.329110338
Short name T603
Test name
Test status
Simulation time 4345969352 ps
CPU time 5.43 seconds
Started Jul 29 05:10:23 PM PDT 24
Finished Jul 29 05:10:28 PM PDT 24
Peak memory 224804 kb
Host smart-2ea27026-bf05-4692-9115-28948d646ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329110338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.329110338
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1580894507
Short name T488
Test name
Test status
Simulation time 2290701435 ps
CPU time 8.18 seconds
Started Jul 29 05:10:20 PM PDT 24
Finished Jul 29 05:10:28 PM PDT 24
Peak memory 224984 kb
Host smart-ca6856dc-a636-4d60-8a08-6e9c8fffaa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580894507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1580894507
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1751029263
Short name T891
Test name
Test status
Simulation time 856060991 ps
CPU time 5.51 seconds
Started Jul 29 05:10:20 PM PDT 24
Finished Jul 29 05:10:26 PM PDT 24
Peak memory 233048 kb
Host smart-cfb78cca-a60e-452b-9960-30066500f5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751029263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1751029263
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2622077528
Short name T794
Test name
Test status
Simulation time 2073762605 ps
CPU time 7.49 seconds
Started Jul 29 05:10:19 PM PDT 24
Finished Jul 29 05:10:27 PM PDT 24
Peak memory 219560 kb
Host smart-5d370e92-6fea-4dfc-a820-212642e0724c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622077528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2622077528
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2045674148
Short name T394
Test name
Test status
Simulation time 7804702862 ps
CPU time 9.47 seconds
Started Jul 29 05:10:22 PM PDT 24
Finished Jul 29 05:10:32 PM PDT 24
Peak memory 216656 kb
Host smart-3803447f-a618-4a29-99cd-846e76380b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045674148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2045674148
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3952076926
Short name T984
Test name
Test status
Simulation time 3393179502 ps
CPU time 14.1 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 216652 kb
Host smart-c9e1992d-6716-4691-8a35-76b948acb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952076926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3952076926
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1463244876
Short name T625
Test name
Test status
Simulation time 751325785 ps
CPU time 3.69 seconds
Started Jul 29 05:10:21 PM PDT 24
Finished Jul 29 05:10:25 PM PDT 24
Peak memory 216536 kb
Host smart-97cbe78e-2cd4-48a4-8303-b085015d6e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463244876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1463244876
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2292350893
Short name T24
Test name
Test status
Simulation time 76537774 ps
CPU time 0.96 seconds
Started Jul 29 05:10:20 PM PDT 24
Finished Jul 29 05:10:21 PM PDT 24
Peak memory 207264 kb
Host smart-c4afbe34-5f07-41ae-b2be-4e5623eef598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292350893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2292350893
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3962437642
Short name T524
Test name
Test status
Simulation time 839767148 ps
CPU time 6.41 seconds
Started Jul 29 05:10:22 PM PDT 24
Finished Jul 29 05:10:29 PM PDT 24
Peak memory 224764 kb
Host smart-dc2fad28-700d-4f45-9271-4a0b336232b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962437642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3962437642
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1514655177
Short name T690
Test name
Test status
Simulation time 14991224 ps
CPU time 0.76 seconds
Started Jul 29 05:10:36 PM PDT 24
Finished Jul 29 05:10:37 PM PDT 24
Peak memory 205172 kb
Host smart-ad29ee43-66e8-45fe-bee0-1656c1aa69bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514655177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1514655177
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3550939366
Short name T787
Test name
Test status
Simulation time 75805474 ps
CPU time 2.17 seconds
Started Jul 29 05:10:27 PM PDT 24
Finished Jul 29 05:10:29 PM PDT 24
Peak memory 224792 kb
Host smart-291126a8-9c41-46f1-9f3a-904f4b30306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550939366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3550939366
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3374953921
Short name T322
Test name
Test status
Simulation time 13307251 ps
CPU time 0.78 seconds
Started Jul 29 05:10:30 PM PDT 24
Finished Jul 29 05:10:31 PM PDT 24
Peak memory 205900 kb
Host smart-670b56cc-5ad7-46ea-8a2e-d15ac4a458ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374953921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3374953921
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.489331878
Short name T403
Test name
Test status
Simulation time 46565085458 ps
CPU time 48.75 seconds
Started Jul 29 05:10:30 PM PDT 24
Finished Jul 29 05:11:19 PM PDT 24
Peak memory 249536 kb
Host smart-55807fbb-ddd6-429a-a58d-1b4d474823db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489331878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.489331878
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3443385524
Short name T850
Test name
Test status
Simulation time 2974764014 ps
CPU time 47.27 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:11:19 PM PDT 24
Peak memory 249568 kb
Host smart-e742c991-b35f-438c-b9f3-eb1417a08c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443385524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3443385524
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1381060186
Short name T837
Test name
Test status
Simulation time 2084058717 ps
CPU time 26.88 seconds
Started Jul 29 05:10:28 PM PDT 24
Finished Jul 29 05:10:55 PM PDT 24
Peak memory 253004 kb
Host smart-1091a1a3-7bb7-4053-b310-5ef1fcba3794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381060186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1381060186
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1059025689
Short name T866
Test name
Test status
Simulation time 693480870 ps
CPU time 10.12 seconds
Started Jul 29 05:10:29 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 233100 kb
Host smart-86405583-4c86-4573-abd3-3916545893c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059025689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1059025689
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2395434945
Short name T586
Test name
Test status
Simulation time 64086842886 ps
CPU time 110.76 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:12:23 PM PDT 24
Peak memory 237312 kb
Host smart-cabb8849-c200-4a7f-ac86-9bf8e87573b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395434945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2395434945
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.677180658
Short name T789
Test name
Test status
Simulation time 2091195658 ps
CPU time 5.7 seconds
Started Jul 29 05:10:28 PM PDT 24
Finished Jul 29 05:10:34 PM PDT 24
Peak memory 224860 kb
Host smart-56d2bd7f-ad0a-4421-b4ba-1f4d271a579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677180658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.677180658
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3578416993
Short name T96
Test name
Test status
Simulation time 3587570867 ps
CPU time 31.81 seconds
Started Jul 29 05:10:29 PM PDT 24
Finished Jul 29 05:11:01 PM PDT 24
Peak memory 224876 kb
Host smart-257a3369-7061-4342-88d1-88e26245f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578416993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3578416993
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2847139964
Short name T361
Test name
Test status
Simulation time 315467020 ps
CPU time 2.12 seconds
Started Jul 29 05:10:30 PM PDT 24
Finished Jul 29 05:10:32 PM PDT 24
Peak memory 224460 kb
Host smart-36031f11-6360-4259-b218-54dfd634ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847139964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2847139964
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.4021649748
Short name T612
Test name
Test status
Simulation time 1046182321 ps
CPU time 6.44 seconds
Started Jul 29 05:10:29 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 224896 kb
Host smart-f589be88-11ce-40b2-bee8-1d78092c3926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021649748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4021649748
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.172851656
Short name T156
Test name
Test status
Simulation time 86070528 ps
CPU time 3.57 seconds
Started Jul 29 05:10:29 PM PDT 24
Finished Jul 29 05:10:32 PM PDT 24
Peak memory 219512 kb
Host smart-1467f15e-0381-4193-ad7c-f5f760f78925
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=172851656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.172851656
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2791429419
Short name T269
Test name
Test status
Simulation time 152043375805 ps
CPU time 1313.95 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:32:28 PM PDT 24
Peak memory 298776 kb
Host smart-67da7689-6415-41d5-ab9d-485e37da1ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791429419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2791429419
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2915749457
Short name T386
Test name
Test status
Simulation time 1151626578 ps
CPU time 11.16 seconds
Started Jul 29 05:10:28 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 216840 kb
Host smart-80787b5c-287c-4fce-bab6-8bcad46ef145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915749457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2915749457
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3767950936
Short name T951
Test name
Test status
Simulation time 353688167 ps
CPU time 2.56 seconds
Started Jul 29 05:10:29 PM PDT 24
Finished Jul 29 05:10:32 PM PDT 24
Peak memory 216544 kb
Host smart-a8df6eaf-79f8-448b-96e1-76ae39430133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767950936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3767950936
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3350784680
Short name T872
Test name
Test status
Simulation time 99420573 ps
CPU time 2.08 seconds
Started Jul 29 05:10:26 PM PDT 24
Finished Jul 29 05:10:28 PM PDT 24
Peak memory 216824 kb
Host smart-d58bac2d-871f-44a4-a776-c8b613d68291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350784680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3350784680
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.164630452
Short name T33
Test name
Test status
Simulation time 37781261 ps
CPU time 0.72 seconds
Started Jul 29 05:10:27 PM PDT 24
Finished Jul 29 05:10:28 PM PDT 24
Peak memory 206336 kb
Host smart-733e625b-6901-42f9-8bc1-8b930e802333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164630452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.164630452
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3093697639
Short name T409
Test name
Test status
Simulation time 560326321 ps
CPU time 2.37 seconds
Started Jul 29 05:10:28 PM PDT 24
Finished Jul 29 05:10:31 PM PDT 24
Peak memory 224552 kb
Host smart-40f85608-7031-4651-9065-f83bcb93088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093697639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3093697639
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4134420793
Short name T621
Test name
Test status
Simulation time 36449126 ps
CPU time 0.73 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 205112 kb
Host smart-7e51c4e5-7696-4205-89cd-1ace50c377af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134420793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4134420793
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.146282179
Short name T911
Test name
Test status
Simulation time 1567880541 ps
CPU time 7.22 seconds
Started Jul 29 05:10:36 PM PDT 24
Finished Jul 29 05:10:44 PM PDT 24
Peak memory 233076 kb
Host smart-567acb09-249a-4703-816f-75b8ee6a7f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146282179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.146282179
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3710373192
Short name T62
Test name
Test status
Simulation time 80649170 ps
CPU time 0.78 seconds
Started Jul 29 05:10:35 PM PDT 24
Finished Jul 29 05:10:36 PM PDT 24
Peak memory 206988 kb
Host smart-a3f5a381-45de-410c-8257-501f95195500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710373192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3710373192
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.322591749
Short name T737
Test name
Test status
Simulation time 85262196146 ps
CPU time 167.41 seconds
Started Jul 29 05:10:33 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 265828 kb
Host smart-9f61d4f7-7a04-4228-800d-75ecdd143da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322591749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.322591749
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3571637191
Short name T540
Test name
Test status
Simulation time 411323884 ps
CPU time 3.78 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:10:38 PM PDT 24
Peak memory 217824 kb
Host smart-4a143d6d-2722-4404-bb21-9a6b53c1f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571637191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3571637191
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.747653841
Short name T585
Test name
Test status
Simulation time 48601420184 ps
CPU time 340.65 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:16:13 PM PDT 24
Peak memory 257120 kb
Host smart-837bfb8c-7220-4e6e-81fe-7081e5b5f17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747653841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.747653841
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.417633456
Short name T979
Test name
Test status
Simulation time 10763181049 ps
CPU time 34.04 seconds
Started Jul 29 05:10:35 PM PDT 24
Finished Jul 29 05:11:09 PM PDT 24
Peak memory 235892 kb
Host smart-5ce5c49d-ea24-4e06-8d7d-0bd4aafe3f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417633456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.417633456
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1307626756
Short name T434
Test name
Test status
Simulation time 66086867146 ps
CPU time 228.97 seconds
Started Jul 29 05:10:36 PM PDT 24
Finished Jul 29 05:14:25 PM PDT 24
Peak memory 249716 kb
Host smart-14f31cd2-ee15-4b50-8d80-db7fb5ca5a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307626756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1307626756
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3220511588
Short name T366
Test name
Test status
Simulation time 34505260 ps
CPU time 2.22 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:10:36 PM PDT 24
Peak memory 224756 kb
Host smart-5b6056b3-fc88-4620-8522-3d917cae9503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220511588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3220511588
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2722952905
Short name T756
Test name
Test status
Simulation time 804369172 ps
CPU time 8.32 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:48 PM PDT 24
Peak memory 224848 kb
Host smart-fabac2aa-df85-43a3-b25f-42591ee32253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722952905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2722952905
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.725079456
Short name T516
Test name
Test status
Simulation time 152396667 ps
CPU time 2.11 seconds
Started Jul 29 05:10:33 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 224716 kb
Host smart-4710ad73-3376-415e-83df-5cfb02a23071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725079456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.725079456
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2759929505
Short name T97
Test name
Test status
Simulation time 3547797623 ps
CPU time 12.64 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 224932 kb
Host smart-da399335-e307-4f1d-b29a-6e66d9a272d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759929505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2759929505
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.459153328
Short name T780
Test name
Test status
Simulation time 221099446 ps
CPU time 3.83 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:44 PM PDT 24
Peak memory 219692 kb
Host smart-7b8ceec7-98b8-4bbf-96ae-0a3e7611f91d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459153328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.459153328
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1054222830
Short name T161
Test name
Test status
Simulation time 13338543337 ps
CPU time 132.59 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:12:47 PM PDT 24
Peak memory 257832 kb
Host smart-5d9130fa-d29f-4287-92b5-eca5291c0813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054222830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1054222830
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1019238289
Short name T679
Test name
Test status
Simulation time 3895847798 ps
CPU time 30.78 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:11:03 PM PDT 24
Peak memory 216712 kb
Host smart-fe5cbf6f-ca8d-4752-b9b8-1f752871d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019238289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1019238289
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1839023523
Short name T500
Test name
Test status
Simulation time 2249193322 ps
CPU time 6.23 seconds
Started Jul 29 05:10:33 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 216700 kb
Host smart-f3c72851-b54e-4476-a691-8c39ff5b1b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839023523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1839023523
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2340368262
Short name T347
Test name
Test status
Simulation time 136527519 ps
CPU time 5.94 seconds
Started Jul 29 05:10:35 PM PDT 24
Finished Jul 29 05:10:41 PM PDT 24
Peak memory 216608 kb
Host smart-7a6e9ffb-ab04-4743-b497-ee2058279b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340368262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2340368262
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2527745759
Short name T774
Test name
Test status
Simulation time 91070148 ps
CPU time 0.97 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:10:33 PM PDT 24
Peak memory 207312 kb
Host smart-7c082246-ec81-4d62-9290-ddd55c4e4c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527745759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2527745759
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1635084814
Short name T661
Test name
Test status
Simulation time 11320252029 ps
CPU time 11.09 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 225168 kb
Host smart-409e73d4-153d-4fb6-9665-1989690f729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635084814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1635084814
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3509129012
Short name T839
Test name
Test status
Simulation time 13160197 ps
CPU time 0.71 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:42 PM PDT 24
Peak memory 205224 kb
Host smart-cdc4ff23-4e33-4ff7-87c0-e26f1370bd13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509129012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3509129012
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3954382930
Short name T477
Test name
Test status
Simulation time 6607053289 ps
CPU time 4.31 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:10:37 PM PDT 24
Peak memory 233100 kb
Host smart-10188de8-129d-4bc2-a501-42c94c3ef0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954382930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3954382930
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3195676073
Short name T934
Test name
Test status
Simulation time 37123523 ps
CPU time 0.8 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:40 PM PDT 24
Peak memory 207216 kb
Host smart-dfc405df-32bc-436c-9730-2814a82b3c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195676073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3195676073
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2588263026
Short name T83
Test name
Test status
Simulation time 21147481604 ps
CPU time 200.56 seconds
Started Jul 29 05:10:45 PM PDT 24
Finished Jul 29 05:14:05 PM PDT 24
Peak memory 256172 kb
Host smart-ead850c2-c9df-4be9-8db7-3576e1302517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588263026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2588263026
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1202097069
Short name T48
Test name
Test status
Simulation time 21360519502 ps
CPU time 161.07 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 251252 kb
Host smart-021845d4-ff7d-453f-a23f-a3318e0221e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202097069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1202097069
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1284082474
Short name T852
Test name
Test status
Simulation time 5045605507 ps
CPU time 54.3 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:11:35 PM PDT 24
Peak memory 263188 kb
Host smart-222d6fbb-04ab-4332-9c39-cf661c5463ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284082474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1284082474
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2402118822
Short name T828
Test name
Test status
Simulation time 38834993 ps
CPU time 2.5 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:43 PM PDT 24
Peak memory 224900 kb
Host smart-b9345bde-6297-4c01-8aed-7633651da900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402118822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2402118822
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1633344117
Short name T441
Test name
Test status
Simulation time 46696309882 ps
CPU time 51.01 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:11:30 PM PDT 24
Peak memory 254168 kb
Host smart-376b0d18-5b8b-4379-87b5-ba0f38f043fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633344117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1633344117
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3766993438
Short name T836
Test name
Test status
Simulation time 778827322 ps
CPU time 11.27 seconds
Started Jul 29 05:10:32 PM PDT 24
Finished Jul 29 05:10:44 PM PDT 24
Peak memory 233132 kb
Host smart-fc9e4aad-d16c-4c25-afd9-ebcfea6bf61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766993438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3766993438
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3010858069
Short name T991
Test name
Test status
Simulation time 327497680 ps
CPU time 7.08 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:46 PM PDT 24
Peak memory 232976 kb
Host smart-6af874a9-a962-44fd-bcd2-909fc81affe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010858069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3010858069
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1479680392
Short name T279
Test name
Test status
Simulation time 11339125382 ps
CPU time 10.58 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 233020 kb
Host smart-8e7bec20-454f-428c-a8ca-a1560073527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479680392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1479680392
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3567743109
Short name T738
Test name
Test status
Simulation time 849888031 ps
CPU time 5.38 seconds
Started Jul 29 05:10:34 PM PDT 24
Finished Jul 29 05:10:40 PM PDT 24
Peak memory 233136 kb
Host smart-049f950e-193a-4d57-bd81-f347d4103a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567743109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3567743109
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2433465263
Short name T358
Test name
Test status
Simulation time 735597755 ps
CPU time 4.14 seconds
Started Jul 29 05:10:37 PM PDT 24
Finished Jul 29 05:10:41 PM PDT 24
Peak memory 221272 kb
Host smart-6e76ebb5-32ee-4e19-a2d3-19cc63824db0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2433465263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2433465263
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1532205985
Short name T352
Test name
Test status
Simulation time 78028848 ps
CPU time 1.25 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:42 PM PDT 24
Peak memory 208092 kb
Host smart-d5cd0552-a698-4d92-8ade-5e24d2c95dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532205985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1532205985
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.618077082
Short name T354
Test name
Test status
Simulation time 28792979418 ps
CPU time 26.19 seconds
Started Jul 29 05:10:36 PM PDT 24
Finished Jul 29 05:11:03 PM PDT 24
Peak memory 216856 kb
Host smart-b34a475c-34ff-4a5c-867e-3aaa9142f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618077082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.618077082
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2251269837
Short name T919
Test name
Test status
Simulation time 218660898 ps
CPU time 1.48 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:41 PM PDT 24
Peak memory 208156 kb
Host smart-e42a2bb5-8b0a-47ca-9499-d0196c35e6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251269837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2251269837
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2760209142
Short name T873
Test name
Test status
Simulation time 241938843 ps
CPU time 1.93 seconds
Started Jul 29 05:10:33 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 216584 kb
Host smart-154e0850-ede5-4004-9fb8-691a25893732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760209142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2760209142
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1731411574
Short name T977
Test name
Test status
Simulation time 52134394 ps
CPU time 0.85 seconds
Started Jul 29 05:10:35 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 206284 kb
Host smart-5881deae-73a4-40d8-bf8c-3317366cd749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731411574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1731411574
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4084994229
Short name T790
Test name
Test status
Simulation time 2007264451 ps
CPU time 8.73 seconds
Started Jul 29 05:10:36 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 233152 kb
Host smart-38d75cbd-78d1-454e-9c82-272ac13da5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084994229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4084994229
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.975378708
Short name T874
Test name
Test status
Simulation time 14382156 ps
CPU time 0.72 seconds
Started Jul 29 05:09:16 PM PDT 24
Finished Jul 29 05:09:17 PM PDT 24
Peak memory 206132 kb
Host smart-67975dee-ae2a-4e2c-bf0c-487019fb3722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975378708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.975378708
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.870724252
Short name T884
Test name
Test status
Simulation time 2951928075 ps
CPU time 12.61 seconds
Started Jul 29 05:09:30 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 233180 kb
Host smart-ec96afe1-d7c7-44da-80ad-15ff3e8ab218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870724252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.870724252
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3174140988
Short name T462
Test name
Test status
Simulation time 22598589 ps
CPU time 0.75 seconds
Started Jul 29 05:09:11 PM PDT 24
Finished Jul 29 05:09:12 PM PDT 24
Peak memory 206972 kb
Host smart-8233b65b-e5c6-4d29-b88a-afd9c6cb51c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174140988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3174140988
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3150668820
Short name T627
Test name
Test status
Simulation time 28767954187 ps
CPU time 74.18 seconds
Started Jul 29 05:09:25 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 256104 kb
Host smart-55ba18bc-afb3-4cbd-af86-ba26985f0b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150668820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3150668820
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.594202761
Short name T135
Test name
Test status
Simulation time 38299388222 ps
CPU time 95.13 seconds
Started Jul 29 05:09:10 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 257776 kb
Host smart-c05e0d12-4366-449e-b35a-73727b3d87f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594202761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.594202761
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2171644724
Short name T170
Test name
Test status
Simulation time 10280743863 ps
CPU time 70.38 seconds
Started Jul 29 05:09:29 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 257648 kb
Host smart-0d6b4c01-42ad-40ef-b9bb-c29c71045afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171644724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2171644724
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2127414171
Short name T1004
Test name
Test status
Simulation time 42345256 ps
CPU time 2.99 seconds
Started Jul 29 05:09:09 PM PDT 24
Finished Jul 29 05:09:12 PM PDT 24
Peak memory 233136 kb
Host smart-bcbd3499-588d-4c0a-80c6-404d0f795e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127414171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2127414171
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4055879783
Short name T187
Test name
Test status
Simulation time 4461504864 ps
CPU time 26.46 seconds
Started Jul 29 05:09:13 PM PDT 24
Finished Jul 29 05:09:40 PM PDT 24
Peak memory 249164 kb
Host smart-5c713bcd-8bc5-422f-b9c9-caa628df0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055879783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4055879783
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3131199165
Short name T626
Test name
Test status
Simulation time 2272151844 ps
CPU time 13.75 seconds
Started Jul 29 05:09:03 PM PDT 24
Finished Jul 29 05:09:17 PM PDT 24
Peak memory 233052 kb
Host smart-91281afd-e371-467f-864b-21250091d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131199165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3131199165
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.485448014
Short name T830
Test name
Test status
Simulation time 28567671999 ps
CPU time 48.29 seconds
Started Jul 29 05:08:59 PM PDT 24
Finished Jul 29 05:09:48 PM PDT 24
Peak memory 233136 kb
Host smart-fe4fecf2-339f-411a-bfb9-edf4694aab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485448014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.485448014
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2590845650
Short name T258
Test name
Test status
Simulation time 3663668945 ps
CPU time 7.06 seconds
Started Jul 29 05:08:55 PM PDT 24
Finished Jul 29 05:09:02 PM PDT 24
Peak memory 233104 kb
Host smart-bbd74d50-83bd-451f-860c-b1d0fd6bd643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590845650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2590845650
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2452491089
Short name T245
Test name
Test status
Simulation time 21553171426 ps
CPU time 16.83 seconds
Started Jul 29 05:09:12 PM PDT 24
Finished Jul 29 05:09:29 PM PDT 24
Peak memory 238284 kb
Host smart-feb1e5f6-b7ed-4522-8897-2f81b54f8af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452491089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2452491089
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3328066839
Short name T931
Test name
Test status
Simulation time 961669698 ps
CPU time 10.01 seconds
Started Jul 29 05:09:00 PM PDT 24
Finished Jul 29 05:09:10 PM PDT 24
Peak memory 222132 kb
Host smart-1d453b95-da55-4513-8244-9d09e5ed596d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3328066839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3328066839
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.204319657
Short name T72
Test name
Test status
Simulation time 304012275 ps
CPU time 1.18 seconds
Started Jul 29 05:09:06 PM PDT 24
Finished Jul 29 05:09:08 PM PDT 24
Peak memory 236752 kb
Host smart-529bcf2a-f1db-422b-8b2f-0061f672c7d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204319657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.204319657
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4198736285
Short name T224
Test name
Test status
Simulation time 6498349371 ps
CPU time 143.71 seconds
Started Jul 29 05:09:22 PM PDT 24
Finished Jul 29 05:11:46 PM PDT 24
Peak memory 268580 kb
Host smart-133af4ab-7783-48a9-a798-a9640ded5371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198736285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4198736285
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3465212851
Short name T844
Test name
Test status
Simulation time 3752732071 ps
CPU time 21.3 seconds
Started Jul 29 05:09:11 PM PDT 24
Finished Jul 29 05:09:33 PM PDT 24
Peak memory 220928 kb
Host smart-63c929b6-b688-4304-9595-673c0d71a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465212851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3465212851
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1773308435
Short name T362
Test name
Test status
Simulation time 460371603 ps
CPU time 1.6 seconds
Started Jul 29 05:09:04 PM PDT 24
Finished Jul 29 05:09:05 PM PDT 24
Peak memory 208112 kb
Host smart-2d05ad42-14eb-41f6-98ba-674e053144f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773308435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1773308435
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2706004176
Short name T37
Test name
Test status
Simulation time 41544029 ps
CPU time 0.95 seconds
Started Jul 29 05:09:04 PM PDT 24
Finished Jul 29 05:09:05 PM PDT 24
Peak memory 206952 kb
Host smart-08cfad4e-61f8-4b24-b48f-cd29b09abd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706004176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2706004176
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3544181953
Short name T682
Test name
Test status
Simulation time 369721629 ps
CPU time 0.93 seconds
Started Jul 29 05:09:05 PM PDT 24
Finished Jul 29 05:09:06 PM PDT 24
Peak memory 206288 kb
Host smart-e6c1a4ee-258d-4ad9-9d98-e42794ba2594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544181953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3544181953
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3076081670
Short name T389
Test name
Test status
Simulation time 4720517150 ps
CPU time 6.24 seconds
Started Jul 29 05:09:09 PM PDT 24
Finished Jul 29 05:09:15 PM PDT 24
Peak memory 230608 kb
Host smart-3e6850bc-b5af-4c76-9e9a-daad7cb65ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076081670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3076081670
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2065916259
Short name T570
Test name
Test status
Simulation time 12348078 ps
CPU time 0.77 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:42 PM PDT 24
Peak memory 205764 kb
Host smart-e256dd6e-e872-4a09-919e-10bcfe5ee031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065916259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2065916259
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1577471337
Short name T869
Test name
Test status
Simulation time 1155519016 ps
CPU time 13.76 seconds
Started Jul 29 05:10:38 PM PDT 24
Finished Jul 29 05:10:52 PM PDT 24
Peak memory 224876 kb
Host smart-a94cd341-98fa-46bb-8bab-6b3430a52597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577471337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1577471337
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3485293737
Short name T902
Test name
Test status
Simulation time 55114369 ps
CPU time 0.79 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:41 PM PDT 24
Peak memory 207252 kb
Host smart-bdb80aca-5a72-4c9b-97c7-7d730139fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485293737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3485293737
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.930976462
Short name T526
Test name
Test status
Simulation time 426591577 ps
CPU time 8.32 seconds
Started Jul 29 05:10:42 PM PDT 24
Finished Jul 29 05:10:51 PM PDT 24
Peak memory 237876 kb
Host smart-a1debab7-60e4-46c2-a357-84e4657bc5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930976462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.930976462
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1820439023
Short name T31
Test name
Test status
Simulation time 1864913437 ps
CPU time 3.61 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 218080 kb
Host smart-79e240ce-13d8-46dd-b8ff-18667de20715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820439023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1820439023
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2487347834
Short name T277
Test name
Test status
Simulation time 21926378611 ps
CPU time 102.51 seconds
Started Jul 29 05:10:42 PM PDT 24
Finished Jul 29 05:12:25 PM PDT 24
Peak memory 266568 kb
Host smart-22655b60-2940-4bca-a00f-cd8b70c0253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487347834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2487347834
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2384381600
Short name T405
Test name
Test status
Simulation time 37550169236 ps
CPU time 140.13 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:12:59 PM PDT 24
Peak memory 256436 kb
Host smart-e0795047-d906-4efb-a479-55e04527e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384381600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2384381600
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2459707869
Short name T658
Test name
Test status
Simulation time 999324971 ps
CPU time 4.37 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 233312 kb
Host smart-6e97482c-f78a-4d39-b3ac-e676490697ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459707869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2459707869
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.714667846
Short name T572
Test name
Test status
Simulation time 12010236560 ps
CPU time 64.28 seconds
Started Jul 29 05:10:38 PM PDT 24
Finished Jul 29 05:11:42 PM PDT 24
Peak memory 257376 kb
Host smart-28ea1c8e-62ad-424b-8fda-d1718ce068f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714667846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.714667846
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2020075704
Short name T251
Test name
Test status
Simulation time 3760585279 ps
CPU time 3.99 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:10:56 PM PDT 24
Peak memory 224800 kb
Host smart-f19a5f99-1dd3-45d1-96bc-9c08674797ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020075704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2020075704
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1746633478
Short name T973
Test name
Test status
Simulation time 9285788235 ps
CPU time 15.03 seconds
Started Jul 29 05:10:44 PM PDT 24
Finished Jul 29 05:10:59 PM PDT 24
Peak memory 239924 kb
Host smart-06c2b70d-b230-4e78-8014-6428063daa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746633478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1746633478
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2818842575
Short name T7
Test name
Test status
Simulation time 493914974 ps
CPU time 6.45 seconds
Started Jul 29 05:10:43 PM PDT 24
Finished Jul 29 05:10:49 PM PDT 24
Peak memory 219248 kb
Host smart-2df4b1d3-9872-4c51-9eb1-cf4aa145cfaf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2818842575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2818842575
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3171569362
Short name T486
Test name
Test status
Simulation time 219296659 ps
CPU time 1.13 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:42 PM PDT 24
Peak memory 207976 kb
Host smart-1faf6fc5-188b-4afe-b10d-909e18bfb34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171569362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3171569362
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2166517585
Short name T430
Test name
Test status
Simulation time 844189641 ps
CPU time 8.54 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:50 PM PDT 24
Peak memory 216676 kb
Host smart-2a46ca11-78c5-4876-94d9-e6ff22624624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166517585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2166517585
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2386671098
Short name T808
Test name
Test status
Simulation time 20444481735 ps
CPU time 10.96 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:50 PM PDT 24
Peak memory 216564 kb
Host smart-2eea2abc-88e1-4446-a092-4098291346b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386671098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2386671098
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1853172762
Short name T801
Test name
Test status
Simulation time 24094345 ps
CPU time 0.76 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:41 PM PDT 24
Peak memory 206300 kb
Host smart-d835d662-a39e-480c-9633-d552d7c01fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853172762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1853172762
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.807826730
Short name T757
Test name
Test status
Simulation time 208871603 ps
CPU time 0.92 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:40 PM PDT 24
Peak memory 207240 kb
Host smart-8a64dbba-13d9-48ba-9197-ce20c4ec25af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807826730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.807826730
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3031033765
Short name T706
Test name
Test status
Simulation time 1414270551 ps
CPU time 4.49 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:43 PM PDT 24
Peak memory 233060 kb
Host smart-8e308b0d-2462-46fc-8bd9-f7288139c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031033765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3031033765
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4244016808
Short name T1001
Test name
Test status
Simulation time 16030202 ps
CPU time 0.74 seconds
Started Jul 29 05:10:47 PM PDT 24
Finished Jul 29 05:10:48 PM PDT 24
Peak memory 205756 kb
Host smart-9e9d4272-212e-49b2-a091-1ef28f28f42d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244016808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4244016808
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1616517363
Short name T242
Test name
Test status
Simulation time 5108460099 ps
CPU time 13.37 seconds
Started Jul 29 05:10:49 PM PDT 24
Finished Jul 29 05:11:02 PM PDT 24
Peak memory 232980 kb
Host smart-a0217dff-c23c-4166-a16d-b2807aea7d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616517363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1616517363
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3085460105
Short name T419
Test name
Test status
Simulation time 17868957 ps
CPU time 0.78 seconds
Started Jul 29 05:10:42 PM PDT 24
Finished Jul 29 05:10:43 PM PDT 24
Peak memory 206876 kb
Host smart-cec845af-5583-4cab-b9cc-6b705e359a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085460105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3085460105
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3984421422
Short name T5
Test name
Test status
Simulation time 21665152866 ps
CPU time 133 seconds
Started Jul 29 05:10:46 PM PDT 24
Finished Jul 29 05:12:59 PM PDT 24
Peak memory 265924 kb
Host smart-84c3b6c4-f3d8-48dc-ae83-3e1c673b2734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984421422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3984421422
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.844364726
Short name T222
Test name
Test status
Simulation time 20846063707 ps
CPU time 202.18 seconds
Started Jul 29 05:10:53 PM PDT 24
Finished Jul 29 05:14:15 PM PDT 24
Peak memory 252528 kb
Host smart-27a82086-c5fd-4472-bb7b-e401141fc966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844364726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.844364726
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2114918983
Short name T719
Test name
Test status
Simulation time 3687606790 ps
CPU time 10.53 seconds
Started Jul 29 05:10:46 PM PDT 24
Finished Jul 29 05:10:57 PM PDT 24
Peak memory 217888 kb
Host smart-d326aa50-c0d1-4186-b63f-b0710363810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114918983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2114918983
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2826310367
Short name T815
Test name
Test status
Simulation time 3474298945 ps
CPU time 14.58 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:11:07 PM PDT 24
Peak memory 224928 kb
Host smart-ab735575-3a59-48f2-9b60-30f5a11f8ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826310367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2826310367
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3539408282
Short name T95
Test name
Test status
Simulation time 90780150011 ps
CPU time 157.84 seconds
Started Jul 29 05:10:49 PM PDT 24
Finished Jul 29 05:13:26 PM PDT 24
Peak memory 265172 kb
Host smart-eb863ef2-8a64-4498-bc9c-eb85b3c16c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539408282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3539408282
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4114291822
Short name T213
Test name
Test status
Simulation time 2243386878 ps
CPU time 9.36 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:11:01 PM PDT 24
Peak memory 224864 kb
Host smart-423595ac-b56d-4614-8d88-d6aab739dd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114291822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4114291822
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1552788094
Short name T554
Test name
Test status
Simulation time 58236003464 ps
CPU time 102.94 seconds
Started Jul 29 05:10:46 PM PDT 24
Finished Jul 29 05:12:29 PM PDT 24
Peak memory 241352 kb
Host smart-e9937c27-c0f7-4eb1-9448-503d2c74a5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552788094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1552788094
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4096412189
Short name T253
Test name
Test status
Simulation time 9985792158 ps
CPU time 15.67 seconds
Started Jul 29 05:10:49 PM PDT 24
Finished Jul 29 05:11:05 PM PDT 24
Peak memory 233208 kb
Host smart-891942cc-2004-4dd1-8fb2-c4c7c42afe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096412189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4096412189
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3865128875
Short name T402
Test name
Test status
Simulation time 23097336543 ps
CPU time 12.36 seconds
Started Jul 29 05:10:41 PM PDT 24
Finished Jul 29 05:10:54 PM PDT 24
Peak memory 225004 kb
Host smart-88827b6d-6757-4494-8da8-a3a8d6af1fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865128875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3865128875
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2271560091
Short name T151
Test name
Test status
Simulation time 1152668922 ps
CPU time 13.3 seconds
Started Jul 29 05:10:53 PM PDT 24
Finished Jul 29 05:11:06 PM PDT 24
Peak memory 219176 kb
Host smart-488f9bbc-a753-4770-a867-b167e6adb608
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271560091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2271560091
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3681104870
Short name T688
Test name
Test status
Simulation time 3112768697 ps
CPU time 13.11 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:52 PM PDT 24
Peak memory 216604 kb
Host smart-a19b3ac1-940b-4e50-8b61-c19a4c9e606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681104870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3681104870
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.743248529
Short name T800
Test name
Test status
Simulation time 3903876057 ps
CPU time 7 seconds
Started Jul 29 05:10:39 PM PDT 24
Finished Jul 29 05:10:46 PM PDT 24
Peak memory 216556 kb
Host smart-e0b91cf7-922c-40bd-a9c4-820182e88043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743248529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.743248529
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1405816141
Short name T382
Test name
Test status
Simulation time 544872653 ps
CPU time 11.11 seconds
Started Jul 29 05:10:40 PM PDT 24
Finished Jul 29 05:10:51 PM PDT 24
Peak memory 216552 kb
Host smart-bf52a660-c957-498b-ae6c-d912b06c98e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405816141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1405816141
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.476285197
Short name T640
Test name
Test status
Simulation time 379799361 ps
CPU time 1 seconds
Started Jul 29 05:10:42 PM PDT 24
Finished Jul 29 05:10:43 PM PDT 24
Peak memory 207268 kb
Host smart-bddb940b-1773-477d-b1a9-aee9ecbab4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476285197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.476285197
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3983427351
Short name T191
Test name
Test status
Simulation time 1188347334 ps
CPU time 7.3 seconds
Started Jul 29 05:10:44 PM PDT 24
Finished Jul 29 05:10:52 PM PDT 24
Peak memory 224896 kb
Host smart-047aa3e4-3d08-40c7-b6a9-80939ff1250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983427351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3983427351
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2353623483
Short name T856
Test name
Test status
Simulation time 24518773 ps
CPU time 0.72 seconds
Started Jul 29 05:10:54 PM PDT 24
Finished Jul 29 05:10:55 PM PDT 24
Peak memory 205728 kb
Host smart-83b8765b-c7da-4964-8247-f3444d69d41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353623483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2353623483
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.531642516
Short name T453
Test name
Test status
Simulation time 903605603 ps
CPU time 10.99 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:11:04 PM PDT 24
Peak memory 224860 kb
Host smart-efec2b23-0e18-47c9-a03b-da2b448940d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531642516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.531642516
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2794263108
Short name T727
Test name
Test status
Simulation time 33463446 ps
CPU time 0.78 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:10:53 PM PDT 24
Peak memory 205788 kb
Host smart-175ec66f-44df-4544-8a75-b81c87006e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794263108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2794263108
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1973289943
Short name T355
Test name
Test status
Simulation time 16755949373 ps
CPU time 35.6 seconds
Started Jul 29 05:10:53 PM PDT 24
Finished Jul 29 05:11:29 PM PDT 24
Peak memory 249472 kb
Host smart-45d2c205-fd77-4062-8f57-4912e0a35d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973289943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1973289943
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1932939654
Short name T278
Test name
Test status
Simulation time 16522465296 ps
CPU time 199.44 seconds
Started Jul 29 05:10:54 PM PDT 24
Finished Jul 29 05:14:13 PM PDT 24
Peak memory 250552 kb
Host smart-34e66ba4-c21a-4507-b3f4-329e9bb87f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932939654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1932939654
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3886324877
Short name T171
Test name
Test status
Simulation time 26575968060 ps
CPU time 103.94 seconds
Started Jul 29 05:11:08 PM PDT 24
Finished Jul 29 05:12:52 PM PDT 24
Peak memory 238068 kb
Host smart-f5d277d5-e15e-4fb9-86ff-ab208d554586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886324877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3886324877
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1218837824
Short name T26
Test name
Test status
Simulation time 53727316 ps
CPU time 3.18 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:10:55 PM PDT 24
Peak memory 233088 kb
Host smart-d6beb1dd-85f2-498d-ac7d-d385a0514cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218837824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1218837824
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3042670451
Short name T413
Test name
Test status
Simulation time 5458363367 ps
CPU time 17.27 seconds
Started Jul 29 05:10:54 PM PDT 24
Finished Jul 29 05:11:11 PM PDT 24
Peak memory 237324 kb
Host smart-5c06f87c-c96d-41d2-b6ee-a3b18620722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042670451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3042670451
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.218064338
Short name T726
Test name
Test status
Simulation time 2920080177 ps
CPU time 7.47 seconds
Started Jul 29 05:10:53 PM PDT 24
Finished Jul 29 05:11:00 PM PDT 24
Peak memory 224868 kb
Host smart-650c2a18-cd8f-4da3-9d98-45f0cbb26a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218064338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.218064338
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4051295028
Short name T898
Test name
Test status
Simulation time 3832049275 ps
CPU time 3.97 seconds
Started Jul 29 05:10:50 PM PDT 24
Finished Jul 29 05:10:54 PM PDT 24
Peak memory 233100 kb
Host smart-8a54ccb0-bcb0-4ff7-830a-089c6a01a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051295028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4051295028
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.271779813
Short name T853
Test name
Test status
Simulation time 6132092639 ps
CPU time 19.08 seconds
Started Jul 29 05:10:51 PM PDT 24
Finished Jul 29 05:11:10 PM PDT 24
Peak memory 240064 kb
Host smart-da7d4d5e-4c89-43de-8a3c-c4fdfaaca951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271779813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.271779813
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2442330619
Short name T237
Test name
Test status
Simulation time 15448947179 ps
CPU time 30.61 seconds
Started Jul 29 05:10:54 PM PDT 24
Finished Jul 29 05:11:25 PM PDT 24
Peak memory 241184 kb
Host smart-7a0416c5-bf2f-4a04-a7b0-296ec94ea3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442330619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2442330619
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4153562298
Short name T39
Test name
Test status
Simulation time 921765477 ps
CPU time 9.11 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:11:01 PM PDT 24
Peak memory 219160 kb
Host smart-2b86404e-f0a8-4b8e-aa06-90b2f2ef0f6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4153562298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4153562298
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2134148585
Short name T164
Test name
Test status
Simulation time 28135422507 ps
CPU time 304.94 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:15:57 PM PDT 24
Peak memory 266968 kb
Host smart-1935b5f9-8b91-4d4a-ae51-028943775afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134148585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2134148585
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3727176539
Short name T671
Test name
Test status
Simulation time 2262333753 ps
CPU time 13.31 seconds
Started Jul 29 05:10:46 PM PDT 24
Finished Jul 29 05:10:59 PM PDT 24
Peak memory 216736 kb
Host smart-46b46c88-8385-4ed1-abfa-d3da451c1392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727176539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3727176539
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.223309810
Short name T759
Test name
Test status
Simulation time 1948381637 ps
CPU time 10.23 seconds
Started Jul 29 05:10:47 PM PDT 24
Finished Jul 29 05:10:57 PM PDT 24
Peak memory 216592 kb
Host smart-dd7c7cda-8210-475e-954b-cccc96266c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223309810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.223309810
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1904309683
Short name T777
Test name
Test status
Simulation time 35622112 ps
CPU time 0.77 seconds
Started Jul 29 05:10:51 PM PDT 24
Finished Jul 29 05:10:52 PM PDT 24
Peak memory 206256 kb
Host smart-ebf0ef53-1fa0-4ef3-9a12-b782b03445d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904309683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1904309683
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2646845820
Short name T796
Test name
Test status
Simulation time 151361079 ps
CPU time 0.9 seconds
Started Jul 29 05:10:47 PM PDT 24
Finished Jul 29 05:10:48 PM PDT 24
Peak memory 206276 kb
Host smart-59f90919-73b4-4bb1-95cf-484c74df523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646845820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2646845820
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2583768378
Short name T240
Test name
Test status
Simulation time 841698717 ps
CPU time 5.16 seconds
Started Jul 29 05:10:54 PM PDT 24
Finished Jul 29 05:10:59 PM PDT 24
Peak memory 235956 kb
Host smart-62df694d-716c-46e3-a104-62b947f0218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583768378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2583768378
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3337367182
Short name T835
Test name
Test status
Simulation time 14056367 ps
CPU time 0.71 seconds
Started Jul 29 05:11:05 PM PDT 24
Finished Jul 29 05:11:05 PM PDT 24
Peak memory 205120 kb
Host smart-deba29d0-745e-4c73-85c1-aa03077cfae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337367182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3337367182
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2959633136
Short name T121
Test name
Test status
Simulation time 250338708 ps
CPU time 4.57 seconds
Started Jul 29 05:11:11 PM PDT 24
Finished Jul 29 05:11:16 PM PDT 24
Peak memory 233036 kb
Host smart-dae28c4b-66a5-4c83-a119-ca68eb792d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959633136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2959633136
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.559880799
Short name T392
Test name
Test status
Simulation time 102804173 ps
CPU time 0.82 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:10:53 PM PDT 24
Peak memory 206852 kb
Host smart-8064b453-9039-4795-862f-c4a7c67ab064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559880799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.559880799
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.591455684
Short name T696
Test name
Test status
Simulation time 2191288865 ps
CPU time 23.68 seconds
Started Jul 29 05:11:20 PM PDT 24
Finished Jul 29 05:11:44 PM PDT 24
Peak memory 233592 kb
Host smart-476353d9-dab7-4516-889e-e2c156d8fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591455684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.591455684
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.258422644
Short name T232
Test name
Test status
Simulation time 5332306383 ps
CPU time 44.09 seconds
Started Jul 29 05:10:58 PM PDT 24
Finished Jul 29 05:11:42 PM PDT 24
Peak memory 249528 kb
Host smart-03de9811-cde8-443f-b194-392112ee654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258422644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.258422644
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3029728473
Short name T94
Test name
Test status
Simulation time 3403207371 ps
CPU time 18.35 seconds
Started Jul 29 05:11:00 PM PDT 24
Finished Jul 29 05:11:19 PM PDT 24
Peak memory 233100 kb
Host smart-25094a46-67fc-4819-95d1-a024d9b5ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029728473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3029728473
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3827450640
Short name T549
Test name
Test status
Simulation time 70726744 ps
CPU time 0.75 seconds
Started Jul 29 05:11:12 PM PDT 24
Finished Jul 29 05:11:12 PM PDT 24
Peak memory 216152 kb
Host smart-5b68aeb1-c09c-4ca1-9ed7-c267e16e3cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827450640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3827450640
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2698683471
Short name T868
Test name
Test status
Simulation time 7867686985 ps
CPU time 18.96 seconds
Started Jul 29 05:11:06 PM PDT 24
Finished Jul 29 05:11:25 PM PDT 24
Peak memory 233196 kb
Host smart-10df7598-53b8-4e75-b94c-d71f1be3875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698683471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2698683471
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2386948229
Short name T683
Test name
Test status
Simulation time 14312065012 ps
CPU time 125.48 seconds
Started Jul 29 05:11:04 PM PDT 24
Finished Jul 29 05:13:10 PM PDT 24
Peak memory 233168 kb
Host smart-623bb40d-7ccb-4dce-8926-d1c119135446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386948229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2386948229
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1454147053
Short name T729
Test name
Test status
Simulation time 13363803571 ps
CPU time 5.61 seconds
Started Jul 29 05:11:06 PM PDT 24
Finished Jul 29 05:11:12 PM PDT 24
Peak memory 233100 kb
Host smart-805461f9-1d14-4a57-93d9-80edbe3d7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454147053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1454147053
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3400725515
Short name T168
Test name
Test status
Simulation time 96107504962 ps
CPU time 29.94 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:11:22 PM PDT 24
Peak memory 233108 kb
Host smart-15f49ae6-469f-4423-8655-8c8076e65f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400725515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3400725515
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.348160605
Short name T510
Test name
Test status
Simulation time 2901995074 ps
CPU time 10.49 seconds
Started Jul 29 05:11:10 PM PDT 24
Finished Jul 29 05:11:20 PM PDT 24
Peak memory 220792 kb
Host smart-4ad5df67-a1cd-4a57-97aa-325e20a91db4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=348160605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.348160605
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4267210982
Short name T666
Test name
Test status
Simulation time 12190165 ps
CPU time 0.7 seconds
Started Jul 29 05:10:53 PM PDT 24
Finished Jul 29 05:10:54 PM PDT 24
Peak memory 206312 kb
Host smart-dd7f7fce-5c47-4ce7-babf-16e3d608d52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267210982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4267210982
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.904570030
Short name T900
Test name
Test status
Simulation time 4933221688 ps
CPU time 11.32 seconds
Started Jul 29 05:10:53 PM PDT 24
Finished Jul 29 05:11:04 PM PDT 24
Peak memory 216572 kb
Host smart-7909be6f-6c93-4584-91d0-5127f273fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904570030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.904570030
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3080027691
Short name T860
Test name
Test status
Simulation time 141598754 ps
CPU time 1 seconds
Started Jul 29 05:10:52 PM PDT 24
Finished Jul 29 05:10:53 PM PDT 24
Peak memory 207812 kb
Host smart-059b74cd-f2ef-47a2-849b-f1fce27896e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080027691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3080027691
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2198203687
Short name T827
Test name
Test status
Simulation time 121095536 ps
CPU time 0.81 seconds
Started Jul 29 05:10:51 PM PDT 24
Finished Jul 29 05:10:52 PM PDT 24
Peak memory 206304 kb
Host smart-e5a3d3ff-d44b-4802-b80c-53d597602c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198203687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2198203687
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2982826341
Short name T660
Test name
Test status
Simulation time 293668479 ps
CPU time 4.75 seconds
Started Jul 29 05:11:05 PM PDT 24
Finished Jul 29 05:11:10 PM PDT 24
Peak memory 232952 kb
Host smart-60bbc46a-9719-436c-8bb3-df9292c40f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982826341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2982826341
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.493523456
Short name T448
Test name
Test status
Simulation time 26807931 ps
CPU time 0.75 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:24 PM PDT 24
Peak memory 206052 kb
Host smart-8903437a-a537-4697-b89e-30139348e175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493523456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.493523456
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3555678585
Short name T879
Test name
Test status
Simulation time 2226526796 ps
CPU time 8.15 seconds
Started Jul 29 05:11:09 PM PDT 24
Finished Jul 29 05:11:17 PM PDT 24
Peak memory 224844 kb
Host smart-339d3ec2-c7c0-4e9d-af60-5699813bd18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555678585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3555678585
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1319531014
Short name T57
Test name
Test status
Simulation time 19086718 ps
CPU time 0.76 seconds
Started Jul 29 05:11:01 PM PDT 24
Finished Jul 29 05:11:02 PM PDT 24
Peak memory 205860 kb
Host smart-8db081c1-30b2-4bff-83cd-023bafdd159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319531014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1319531014
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3797425625
Short name T883
Test name
Test status
Simulation time 61504858122 ps
CPU time 155.7 seconds
Started Jul 29 05:11:06 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 257132 kb
Host smart-2a21b7c2-591f-43f2-8cbf-3a6874103428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797425625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3797425625
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.949252052
Short name T228
Test name
Test status
Simulation time 24835958928 ps
CPU time 227.09 seconds
Started Jul 29 05:11:14 PM PDT 24
Finished Jul 29 05:15:01 PM PDT 24
Peak memory 249712 kb
Host smart-32461dba-33bb-498a-8cea-1c090b0abdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949252052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.949252052
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1421621002
Short name T924
Test name
Test status
Simulation time 29052740967 ps
CPU time 206.08 seconds
Started Jul 29 05:11:11 PM PDT 24
Finished Jul 29 05:14:37 PM PDT 24
Peak memory 250556 kb
Host smart-6ce8c34a-7a83-4a4a-a0d1-2c20018453d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421621002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1421621002
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2699052970
Short name T906
Test name
Test status
Simulation time 1310794329 ps
CPU time 4.05 seconds
Started Jul 29 05:11:06 PM PDT 24
Finished Jul 29 05:11:10 PM PDT 24
Peak memory 224816 kb
Host smart-7fd08673-e349-41bb-bb95-78364608e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699052970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2699052970
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3689695685
Short name T899
Test name
Test status
Simulation time 46147576 ps
CPU time 0.76 seconds
Started Jul 29 05:11:26 PM PDT 24
Finished Jul 29 05:11:27 PM PDT 24
Peak memory 216128 kb
Host smart-8d5b02c8-bc55-4a15-828b-2e380b29ce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689695685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3689695685
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3954389876
Short name T140
Test name
Test status
Simulation time 978597932 ps
CPU time 6.78 seconds
Started Jul 29 05:11:07 PM PDT 24
Finished Jul 29 05:11:14 PM PDT 24
Peak memory 233040 kb
Host smart-a5e8e8a5-128d-4da2-8f96-a1bb15cfbbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954389876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3954389876
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.435384050
Short name T3
Test name
Test status
Simulation time 959369321 ps
CPU time 8.71 seconds
Started Jul 29 05:11:07 PM PDT 24
Finished Jul 29 05:11:16 PM PDT 24
Peak memory 233312 kb
Host smart-0c35a2c1-b26f-47d0-878a-44640b9b61b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435384050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.435384050
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3708953341
Short name T558
Test name
Test status
Simulation time 1840678259 ps
CPU time 8.86 seconds
Started Jul 29 05:11:17 PM PDT 24
Finished Jul 29 05:11:26 PM PDT 24
Peak memory 241040 kb
Host smart-cec56d16-3b50-4122-9443-6ee76b0c28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708953341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3708953341
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3936591654
Short name T681
Test name
Test status
Simulation time 610593156 ps
CPU time 4.67 seconds
Started Jul 29 05:11:09 PM PDT 24
Finished Jul 29 05:11:13 PM PDT 24
Peak memory 224808 kb
Host smart-cad28f40-9626-495a-a332-423e505b17d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936591654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3936591654
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.218810358
Short name T333
Test name
Test status
Simulation time 115246569 ps
CPU time 3.76 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 220532 kb
Host smart-c91c1929-0fc8-4e34-a4d7-e7f97833bb33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218810358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.218810358
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.797405814
Short name T992
Test name
Test status
Simulation time 21060731477 ps
CPU time 160.46 seconds
Started Jul 29 05:11:25 PM PDT 24
Finished Jul 29 05:14:05 PM PDT 24
Peak memory 249552 kb
Host smart-ad9726ae-7e1a-4c64-9764-b6f93f51edbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797405814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.797405814
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3188239866
Short name T578
Test name
Test status
Simulation time 2323238908 ps
CPU time 16.37 seconds
Started Jul 29 05:11:06 PM PDT 24
Finished Jul 29 05:11:23 PM PDT 24
Peak memory 219812 kb
Host smart-91bffad1-0bcd-43b0-beec-af3180e66eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188239866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3188239866
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1959771153
Short name T996
Test name
Test status
Simulation time 7956936417 ps
CPU time 6.89 seconds
Started Jul 29 05:11:03 PM PDT 24
Finished Jul 29 05:11:10 PM PDT 24
Peak memory 216640 kb
Host smart-8a94a284-c80e-41bf-8a2d-d32dcdf85e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959771153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1959771153
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3222805055
Short name T502
Test name
Test status
Simulation time 35277086 ps
CPU time 1.3 seconds
Started Jul 29 05:11:12 PM PDT 24
Finished Jul 29 05:11:14 PM PDT 24
Peak memory 216512 kb
Host smart-b295eb25-1205-47a2-bb23-0fce06e89c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222805055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3222805055
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1324955579
Short name T1003
Test name
Test status
Simulation time 89826521 ps
CPU time 0.91 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:29 PM PDT 24
Peak memory 206284 kb
Host smart-a487832d-ee89-42f4-a11b-28adf33cdc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324955579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1324955579
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3355905678
Short name T439
Test name
Test status
Simulation time 122903975 ps
CPU time 2.19 seconds
Started Jul 29 05:11:10 PM PDT 24
Finished Jul 29 05:11:12 PM PDT 24
Peak memory 224452 kb
Host smart-c6f65559-3cab-4dee-be27-d1bd55a27965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355905678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3355905678
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1747162915
Short name T64
Test name
Test status
Simulation time 12959269 ps
CPU time 0.72 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:30 PM PDT 24
Peak memory 205152 kb
Host smart-58f08050-d441-4858-8f02-b0bce5b65821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747162915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1747162915
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1422403059
Short name T243
Test name
Test status
Simulation time 996186157 ps
CPU time 10.37 seconds
Started Jul 29 05:11:09 PM PDT 24
Finished Jul 29 05:11:20 PM PDT 24
Peak memory 233052 kb
Host smart-3facf468-5e7b-4fb2-ac24-00d031e79123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422403059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1422403059
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1172055008
Short name T978
Test name
Test status
Simulation time 57445406 ps
CPU time 0.76 seconds
Started Jul 29 05:11:19 PM PDT 24
Finished Jul 29 05:11:20 PM PDT 24
Peak memory 207308 kb
Host smart-c0330434-49d0-4751-a650-83a7d4103af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172055008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1172055008
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2802911970
Short name T983
Test name
Test status
Simulation time 32653341030 ps
CPU time 257.79 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:15:50 PM PDT 24
Peak memory 267648 kb
Host smart-5e570264-405d-4332-9ccd-3970344fb6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802911970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2802911970
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1757187062
Short name T623
Test name
Test status
Simulation time 47779692707 ps
CPU time 360.2 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:17:30 PM PDT 24
Peak memory 250628 kb
Host smart-7bff30b5-e34a-4121-985f-c549b6d29616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757187062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1757187062
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1279183668
Short name T705
Test name
Test status
Simulation time 11711558077 ps
CPU time 77.32 seconds
Started Jul 29 05:11:15 PM PDT 24
Finished Jul 29 05:12:32 PM PDT 24
Peak memory 249844 kb
Host smart-da546cb1-6bc6-4e3e-97c0-cedfe50c8987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279183668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1279183668
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.891047798
Short name T542
Test name
Test status
Simulation time 6069404343 ps
CPU time 73.68 seconds
Started Jul 29 05:11:24 PM PDT 24
Finished Jul 29 05:12:37 PM PDT 24
Peak memory 251800 kb
Host smart-9003cb4c-dbda-493d-b5ae-5de9ddda473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891047798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.891047798
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2441624558
Short name T624
Test name
Test status
Simulation time 1835298451 ps
CPU time 21.37 seconds
Started Jul 29 05:11:33 PM PDT 24
Finished Jul 29 05:11:54 PM PDT 24
Peak memory 233092 kb
Host smart-906e8062-a187-4bc1-b015-7d7c9557779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441624558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2441624558
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1832002269
Short name T762
Test name
Test status
Simulation time 1638778624 ps
CPU time 7.63 seconds
Started Jul 29 05:11:09 PM PDT 24
Finished Jul 29 05:11:17 PM PDT 24
Peak memory 241016 kb
Host smart-5cc9d7de-bbea-4296-ac46-63f2339dd8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832002269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1832002269
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4015947496
Short name T195
Test name
Test status
Simulation time 7659096834 ps
CPU time 10.08 seconds
Started Jul 29 05:11:05 PM PDT 24
Finished Jul 29 05:11:15 PM PDT 24
Peak memory 224872 kb
Host smart-32e37617-5fcf-48b7-8eca-80c6b7b8d3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015947496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4015947496
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1025073514
Short name T678
Test name
Test status
Simulation time 2189618329 ps
CPU time 4.21 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:27 PM PDT 24
Peak memory 233052 kb
Host smart-a6b38b8c-6b5f-4c75-8909-c676a8b22f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025073514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1025073514
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1209367569
Short name T472
Test name
Test status
Simulation time 499106836 ps
CPU time 5.01 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:28 PM PDT 24
Peak memory 219708 kb
Host smart-8af59259-171d-4d87-a655-6588ae93bf14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1209367569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1209367569
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3811358370
Short name T17
Test name
Test status
Simulation time 97350926 ps
CPU time 0.98 seconds
Started Jul 29 05:11:18 PM PDT 24
Finished Jul 29 05:11:19 PM PDT 24
Peak memory 207344 kb
Host smart-f0a9cdd0-f3e7-4d72-9b05-85e3d5c3b931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811358370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3811358370
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1504657509
Short name T703
Test name
Test status
Simulation time 1792053939 ps
CPU time 4.41 seconds
Started Jul 29 05:11:11 PM PDT 24
Finished Jul 29 05:11:16 PM PDT 24
Peak memory 218568 kb
Host smart-3c10c4f9-af18-4d9f-889b-b6be18cb531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504657509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1504657509
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3244953169
Short name T697
Test name
Test status
Simulation time 5358131335 ps
CPU time 4.96 seconds
Started Jul 29 05:11:20 PM PDT 24
Finished Jul 29 05:11:25 PM PDT 24
Peak memory 216688 kb
Host smart-37220626-db29-490e-be18-b9b4df897d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244953169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3244953169
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1896184904
Short name T821
Test name
Test status
Simulation time 123627061 ps
CPU time 1.21 seconds
Started Jul 29 05:11:08 PM PDT 24
Finished Jul 29 05:11:10 PM PDT 24
Peak memory 216544 kb
Host smart-aa573f58-d983-4e85-8a24-c81e3c0996fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896184904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1896184904
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.667562205
Short name T812
Test name
Test status
Simulation time 36332070 ps
CPU time 0.7 seconds
Started Jul 29 05:11:20 PM PDT 24
Finished Jul 29 05:11:21 PM PDT 24
Peak memory 205912 kb
Host smart-3b32cb65-c819-4f1c-a392-1cf6448af662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667562205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.667562205
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2922776479
Short name T676
Test name
Test status
Simulation time 17976942282 ps
CPU time 9.08 seconds
Started Jul 29 05:11:10 PM PDT 24
Finished Jul 29 05:11:20 PM PDT 24
Peak memory 238424 kb
Host smart-dfe69217-4300-4a25-8938-1c59578a15d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922776479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2922776479
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3459992833
Short name T604
Test name
Test status
Simulation time 16356012 ps
CPU time 0.75 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:31 PM PDT 24
Peak memory 206136 kb
Host smart-5d8ecde4-3ac4-4ac2-aa93-ce0430074a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459992833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3459992833
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1399897005
Short name T917
Test name
Test status
Simulation time 59234481 ps
CPU time 2.06 seconds
Started Jul 29 05:11:21 PM PDT 24
Finished Jul 29 05:11:23 PM PDT 24
Peak memory 224816 kb
Host smart-265a3241-9586-4803-9d4c-1f780b578e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399897005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1399897005
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1505045154
Short name T338
Test name
Test status
Simulation time 61971060 ps
CPU time 0.8 seconds
Started Jul 29 05:11:26 PM PDT 24
Finished Jul 29 05:11:27 PM PDT 24
Peak memory 206852 kb
Host smart-a3295be9-bd87-4038-a612-39ab5d56ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505045154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1505045154
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.876145641
Short name T202
Test name
Test status
Simulation time 5199443285 ps
CPU time 115.85 seconds
Started Jul 29 05:11:27 PM PDT 24
Finished Jul 29 05:13:23 PM PDT 24
Peak memory 273144 kb
Host smart-ef3033f2-e9fd-4037-8a12-c0194154247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876145641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.876145641
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3363710733
Short name T221
Test name
Test status
Simulation time 108040252537 ps
CPU time 239.63 seconds
Started Jul 29 05:11:17 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 254292 kb
Host smart-f5debdd8-07b3-43ef-ac71-bbb8dbf391ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363710733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3363710733
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1158684286
Short name T857
Test name
Test status
Simulation time 200426668878 ps
CPU time 472.67 seconds
Started Jul 29 05:11:36 PM PDT 24
Finished Jul 29 05:19:29 PM PDT 24
Peak memory 264000 kb
Host smart-941cade4-75d5-4d23-b84f-cf59e3a35a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158684286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1158684286
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2366753713
Short name T541
Test name
Test status
Simulation time 557198925 ps
CPU time 5.15 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:28 PM PDT 24
Peak memory 224880 kb
Host smart-d449fb2a-6c7e-4776-ae35-4dbeff4d3877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366753713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2366753713
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.651295708
Short name T593
Test name
Test status
Simulation time 9157753940 ps
CPU time 54.64 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:12:26 PM PDT 24
Peak memory 249452 kb
Host smart-2d3f9e51-3247-47c1-8a5f-bd872121699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651295708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.651295708
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.397665739
Short name T200
Test name
Test status
Simulation time 1084310367 ps
CPU time 4.91 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:38 PM PDT 24
Peak memory 233080 kb
Host smart-a61636a4-7472-46c5-be41-39dbf5c69d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397665739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.397665739
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.366145028
Short name T481
Test name
Test status
Simulation time 24461004131 ps
CPU time 92.95 seconds
Started Jul 29 05:11:18 PM PDT 24
Finished Jul 29 05:12:51 PM PDT 24
Peak memory 233180 kb
Host smart-a52d4474-158d-4a3c-b026-db8010ba1142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366145028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.366145028
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3318406283
Short name T274
Test name
Test status
Simulation time 308465631 ps
CPU time 4.71 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:37 PM PDT 24
Peak memory 233332 kb
Host smart-bba9f682-db09-4498-89e0-1b02c596a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318406283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3318406283
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2661450818
Short name T498
Test name
Test status
Simulation time 6876863797 ps
CPU time 5.68 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 224872 kb
Host smart-eae9fe40-6423-4af6-b5d7-10be96982344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661450818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2661450818
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.110792792
Short name T468
Test name
Test status
Simulation time 154880525 ps
CPU time 4.31 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 219676 kb
Host smart-72143943-6066-445f-a796-dde0fb36922c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=110792792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.110792792
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1581594797
Short name T49
Test name
Test status
Simulation time 45306185863 ps
CPU time 480.55 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:19:31 PM PDT 24
Peak memory 282320 kb
Host smart-437f2877-1c10-4133-a78d-29ac43d63fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581594797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1581594797
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2078200956
Short name T1002
Test name
Test status
Simulation time 24676193899 ps
CPU time 8.38 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 216952 kb
Host smart-9a10cd96-253a-4811-a20a-424298b8f890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078200956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2078200956
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3251033882
Short name T319
Test name
Test status
Simulation time 7955196791 ps
CPU time 11.79 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:35 PM PDT 24
Peak memory 216664 kb
Host smart-3dba72ee-e751-4afe-b0e1-8ef23d9a3e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251033882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3251033882
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.524856681
Short name T330
Test name
Test status
Simulation time 33811977 ps
CPU time 1.74 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 216576 kb
Host smart-5f7a677c-c596-4f4d-abcd-40b8fd2de63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524856681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.524856681
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1676897923
Short name T385
Test name
Test status
Simulation time 141156989 ps
CPU time 1.03 seconds
Started Jul 29 05:11:22 PM PDT 24
Finished Jul 29 05:11:23 PM PDT 24
Peak memory 207260 kb
Host smart-efe79c0a-8ff4-4a96-bc7b-673b6fa8f836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676897923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1676897923
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2469312484
Short name T346
Test name
Test status
Simulation time 675338770 ps
CPU time 2.77 seconds
Started Jul 29 05:11:20 PM PDT 24
Finished Jul 29 05:11:23 PM PDT 24
Peak memory 224880 kb
Host smart-50a2bce5-10f9-4291-8726-d0309cb187ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469312484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2469312484
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3154882420
Short name T642
Test name
Test status
Simulation time 109869874 ps
CPU time 0.73 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:33 PM PDT 24
Peak memory 205220 kb
Host smart-6f2ec493-e407-403a-b9ff-15b297aba524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154882420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3154882420
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1285073085
Short name T769
Test name
Test status
Simulation time 1129828842 ps
CPU time 12.18 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 224740 kb
Host smart-07424c56-4020-4714-8b08-679c6533ec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285073085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1285073085
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1299789443
Short name T732
Test name
Test status
Simulation time 38240363 ps
CPU time 0.78 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:29 PM PDT 24
Peak memory 207188 kb
Host smart-c41b69e8-96b4-4bf7-b569-509ba18074f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299789443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1299789443
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.252706590
Short name T597
Test name
Test status
Simulation time 12598947981 ps
CPU time 42.69 seconds
Started Jul 29 05:11:33 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 255600 kb
Host smart-64ac8301-a27b-4d88-9a25-b99d7e22bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252706590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.252706590
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3954988056
Short name T887
Test name
Test status
Simulation time 4909484257 ps
CPU time 66.41 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:12:36 PM PDT 24
Peak memory 254192 kb
Host smart-1d42b15e-7fa4-4172-af4c-cdd6c354e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954988056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3954988056
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3360626729
Short name T6
Test name
Test status
Simulation time 13776896318 ps
CPU time 122.98 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:13:32 PM PDT 24
Peak memory 240784 kb
Host smart-4cb30268-4faa-4d85-8c3a-bc5aa75cc544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360626729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3360626729
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3228981197
Short name T152
Test name
Test status
Simulation time 223485177 ps
CPU time 4.94 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:33 PM PDT 24
Peak memory 233136 kb
Host smart-c8778e9c-0b1f-4ce8-acf1-d4a5f92f99cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228981197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3228981197
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1488136810
Short name T543
Test name
Test status
Simulation time 5836624728 ps
CPU time 48.79 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:12:18 PM PDT 24
Peak memory 237816 kb
Host smart-d6248709-51e4-4a98-91d5-63a883f1e296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488136810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1488136810
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1196487832
Short name T489
Test name
Test status
Simulation time 118883202 ps
CPU time 2.35 seconds
Started Jul 29 05:11:37 PM PDT 24
Finished Jul 29 05:11:40 PM PDT 24
Peak memory 227080 kb
Host smart-e02afd45-350c-4bb5-8e45-3a84ce4e1ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196487832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1196487832
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1157552310
Short name T580
Test name
Test status
Simulation time 989845051 ps
CPU time 12 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:40 PM PDT 24
Peak memory 224756 kb
Host smart-9ce13c98-9e26-480e-8903-ad06c50a2e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157552310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1157552310
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4156053027
Short name T923
Test name
Test status
Simulation time 20325189939 ps
CPU time 19.38 seconds
Started Jul 29 05:11:17 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 233096 kb
Host smart-19765e1e-a833-4e3b-96e9-0f92a341f4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156053027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4156053027
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.722110733
Short name T966
Test name
Test status
Simulation time 418173132 ps
CPU time 2.66 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 224716 kb
Host smart-ccf387b7-b83a-4dea-90a8-29a4bc4acad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722110733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.722110733
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3257737651
Short name T525
Test name
Test status
Simulation time 172136941 ps
CPU time 4.9 seconds
Started Jul 29 05:11:26 PM PDT 24
Finished Jul 29 05:11:31 PM PDT 24
Peak memory 223436 kb
Host smart-a64bc84f-3202-44ed-b97b-d6663ebe9399
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3257737651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3257737651
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2938000007
Short name T721
Test name
Test status
Simulation time 8597574928 ps
CPU time 69.04 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:12:39 PM PDT 24
Peak memory 249920 kb
Host smart-64eefdf1-149f-4d95-a84c-7c1b92dfa590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938000007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2938000007
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4017792426
Short name T304
Test name
Test status
Simulation time 6118857059 ps
CPU time 36.69 seconds
Started Jul 29 05:11:21 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 216820 kb
Host smart-f069d117-c5eb-4d84-90be-b911f14a0c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017792426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4017792426
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2259996144
Short name T32
Test name
Test status
Simulation time 698600633 ps
CPU time 2.99 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:34 PM PDT 24
Peak memory 216608 kb
Host smart-2af7abf6-a714-484c-8c3e-400818ae9f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259996144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2259996144
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.440840888
Short name T712
Test name
Test status
Simulation time 1059708660 ps
CPU time 4.84 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 216604 kb
Host smart-8fc4c1f9-c8ae-495e-b5c1-aa6a89c41e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440840888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.440840888
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.79655848
Short name T407
Test name
Test status
Simulation time 25203187 ps
CPU time 0.82 seconds
Started Jul 29 05:11:18 PM PDT 24
Finished Jul 29 05:11:19 PM PDT 24
Peak memory 206332 kb
Host smart-9d24c737-a426-4b3b-9e29-a9b4f7a770f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79655848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.79655848
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.799773698
Short name T466
Test name
Test status
Simulation time 35500377 ps
CPU time 2.58 seconds
Started Jul 29 05:11:34 PM PDT 24
Finished Jul 29 05:11:37 PM PDT 24
Peak memory 233056 kb
Host smart-51315f06-0425-4411-b54d-1e54cad0f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799773698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.799773698
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2936041200
Short name T56
Test name
Test status
Simulation time 20552785 ps
CPU time 0.68 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 205132 kb
Host smart-ea68b9f2-f4e8-4c6d-973c-a391b354c4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936041200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2936041200
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1484327611
Short name T388
Test name
Test status
Simulation time 258269239 ps
CPU time 3.07 seconds
Started Jul 29 05:11:40 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 224932 kb
Host smart-c5730c26-0912-430a-b172-b80100bb7b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484327611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1484327611
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3251162527
Short name T396
Test name
Test status
Simulation time 16150679 ps
CPU time 0.76 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:29 PM PDT 24
Peak memory 206244 kb
Host smart-4dd83efd-4eaa-495f-ade4-e2370aeec267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251162527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3251162527
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4214747685
Short name T427
Test name
Test status
Simulation time 10947264099 ps
CPU time 15.85 seconds
Started Jul 29 05:11:28 PM PDT 24
Finished Jul 29 05:11:44 PM PDT 24
Peak memory 235044 kb
Host smart-511104f1-1580-4e4c-903d-0b03c7aa6c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214747685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4214747685
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.413580196
Short name T199
Test name
Test status
Simulation time 93933503823 ps
CPU time 553.13 seconds
Started Jul 29 05:11:25 PM PDT 24
Finished Jul 29 05:20:38 PM PDT 24
Peak memory 272324 kb
Host smart-218a2f6b-431a-461c-a69e-a310c3967ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413580196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.413580196
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.358062876
Short name T981
Test name
Test status
Simulation time 230569518 ps
CPU time 5.86 seconds
Started Jul 29 05:11:38 PM PDT 24
Finished Jul 29 05:11:44 PM PDT 24
Peak memory 224788 kb
Host smart-e3a61d7a-5160-4f50-b86a-7bcd83a8d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358062876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.358062876
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2028167303
Short name T9
Test name
Test status
Simulation time 15353511272 ps
CPU time 37.89 seconds
Started Jul 29 05:11:25 PM PDT 24
Finished Jul 29 05:12:03 PM PDT 24
Peak memory 241332 kb
Host smart-6cf44165-fd23-4eb9-bcad-bbfcbb20d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028167303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2028167303
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4196743176
Short name T662
Test name
Test status
Simulation time 282962882 ps
CPU time 5.77 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 233032 kb
Host smart-6b896c03-f5a1-4a0d-b94a-8f8413570fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196743176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4196743176
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.371272562
Short name T479
Test name
Test status
Simulation time 6560483250 ps
CPU time 60.39 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:12:31 PM PDT 24
Peak memory 224956 kb
Host smart-406cd902-ec81-4181-a15d-9ec74597e1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371272562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.371272562
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.959685329
Short name T630
Test name
Test status
Simulation time 980710365 ps
CPU time 2.82 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:34 PM PDT 24
Peak memory 233088 kb
Host smart-180d5acb-e82a-479b-a6bd-85095ba85898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959685329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.959685329
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1360811576
Short name T483
Test name
Test status
Simulation time 787741926 ps
CPU time 4.06 seconds
Started Jul 29 05:11:39 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 233308 kb
Host smart-a2a36c0e-fdb7-4e57-a3eb-272669abf567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360811576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1360811576
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3806393297
Short name T876
Test name
Test status
Simulation time 2307191379 ps
CPU time 10.47 seconds
Started Jul 29 05:11:37 PM PDT 24
Finished Jul 29 05:11:47 PM PDT 24
Peak memory 223692 kb
Host smart-72d67aec-c075-46d9-89f4-1f7fb2d8f2bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3806393297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3806393297
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1386828561
Short name T163
Test name
Test status
Simulation time 24419729688 ps
CPU time 232.31 seconds
Started Jul 29 05:11:36 PM PDT 24
Finished Jul 29 05:15:29 PM PDT 24
Peak memory 266204 kb
Host smart-4ae16f36-3544-4e8f-8f52-6c2f4f6c0ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386828561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1386828561
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1333890332
Short name T791
Test name
Test status
Simulation time 694498592 ps
CPU time 4.03 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:11:33 PM PDT 24
Peak memory 216624 kb
Host smart-d8f1a37a-9a6b-43e8-bdda-c1095d41b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333890332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1333890332
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1259171820
Short name T754
Test name
Test status
Simulation time 1012109883 ps
CPU time 3.23 seconds
Started Jul 29 05:11:27 PM PDT 24
Finished Jul 29 05:11:31 PM PDT 24
Peak memory 216580 kb
Host smart-e701ae0a-cfc5-40ef-b30e-1df70235511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259171820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1259171820
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.852475631
Short name T408
Test name
Test status
Simulation time 748794756 ps
CPU time 2.44 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:33 PM PDT 24
Peak memory 216620 kb
Host smart-d1198a5c-5699-4a8d-9999-1647f5304c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852475631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.852475631
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.165926694
Short name T968
Test name
Test status
Simulation time 132259156 ps
CPU time 0.74 seconds
Started Jul 29 05:11:26 PM PDT 24
Finished Jul 29 05:11:27 PM PDT 24
Peak memory 206296 kb
Host smart-36032158-7763-4f25-87a6-5f84df78b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165926694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.165926694
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2967353915
Short name T912
Test name
Test status
Simulation time 7056777940 ps
CPU time 14.66 seconds
Started Jul 29 05:11:25 PM PDT 24
Finished Jul 29 05:11:40 PM PDT 24
Peak memory 233144 kb
Host smart-59a8bbb1-362b-43b2-ac13-e2521c7fa366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967353915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2967353915
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2113164849
Short name T340
Test name
Test status
Simulation time 11879163 ps
CPU time 0.71 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:11:30 PM PDT 24
Peak memory 205796 kb
Host smart-dce3fafc-d64d-459f-8054-aa156587bf5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113164849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2113164849
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1080185532
Short name T22
Test name
Test status
Simulation time 1804299364 ps
CPU time 4.8 seconds
Started Jul 29 05:11:47 PM PDT 24
Finished Jul 29 05:11:52 PM PDT 24
Peak memory 224848 kb
Host smart-0a6aea60-ae32-4aca-97d8-586d22118356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080185532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1080185532
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.638616309
Short name T337
Test name
Test status
Simulation time 54249553 ps
CPU time 0.77 seconds
Started Jul 29 05:11:27 PM PDT 24
Finished Jul 29 05:11:28 PM PDT 24
Peak memory 205944 kb
Host smart-7c5a0303-ad7e-4ead-a157-6fb05892c9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638616309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.638616309
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3054649081
Short name T275
Test name
Test status
Simulation time 91763978695 ps
CPU time 188.8 seconds
Started Jul 29 05:11:29 PM PDT 24
Finished Jul 29 05:14:38 PM PDT 24
Peak memory 250500 kb
Host smart-fb087cf0-2fca-4181-8b90-42caef41a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054649081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3054649081
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1203150274
Short name T51
Test name
Test status
Simulation time 8618817411 ps
CPU time 68.52 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:12:56 PM PDT 24
Peak memory 241356 kb
Host smart-5ad4e924-16e5-4afa-904c-89308d03e93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203150274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1203150274
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1316115313
Short name T619
Test name
Test status
Simulation time 272701699689 ps
CPU time 258.37 seconds
Started Jul 29 05:11:45 PM PDT 24
Finished Jul 29 05:16:03 PM PDT 24
Peak memory 254188 kb
Host smart-cfca2e6c-9c78-45c3-8892-6a810d731faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316115313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1316115313
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3871482732
Short name T300
Test name
Test status
Simulation time 6931450066 ps
CPU time 27.63 seconds
Started Jul 29 05:11:50 PM PDT 24
Finished Jul 29 05:12:18 PM PDT 24
Peak memory 234084 kb
Host smart-26e1ea64-3068-4462-ae9d-bd642e538ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871482732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3871482732
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1876216006
Short name T223
Test name
Test status
Simulation time 658059885 ps
CPU time 4.7 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:37 PM PDT 24
Peak memory 224828 kb
Host smart-1ddbd8d3-04c3-4a3c-8564-55e5402b71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876216006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1876216006
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2653777255
Short name T710
Test name
Test status
Simulation time 146133603 ps
CPU time 2.25 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:11:45 PM PDT 24
Peak memory 224520 kb
Host smart-c1804a1b-917e-44f3-9f4e-32c22937ca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653777255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2653777255
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3083451481
Short name T271
Test name
Test status
Simulation time 1325353468 ps
CPU time 5.91 seconds
Started Jul 29 05:11:39 PM PDT 24
Finished Jul 29 05:11:45 PM PDT 24
Peak memory 233108 kb
Host smart-3eac8217-cffe-4d0c-9e4a-1274f8d85021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083451481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3083451481
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1034136533
Short name T749
Test name
Test status
Simulation time 6773476616 ps
CPU time 16.18 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:48 PM PDT 24
Peak memory 233072 kb
Host smart-80f773da-2e55-4736-9d56-71bd56863d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034136533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1034136533
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.700659188
Short name T820
Test name
Test status
Simulation time 835671417 ps
CPU time 5.67 seconds
Started Jul 29 05:11:36 PM PDT 24
Finished Jul 29 05:11:42 PM PDT 24
Peak memory 220824 kb
Host smart-01aee199-0d16-4055-8141-6b1aa4bee0d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=700659188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.700659188
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.731302246
Short name T862
Test name
Test status
Simulation time 193549685 ps
CPU time 1.01 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:31 PM PDT 24
Peak memory 216272 kb
Host smart-47c38806-2dba-4f8e-91c1-81eede2958da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731302246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.731302246
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.344183790
Short name T501
Test name
Test status
Simulation time 11007146796 ps
CPU time 14.22 seconds
Started Jul 29 05:11:23 PM PDT 24
Finished Jul 29 05:11:37 PM PDT 24
Peak memory 216728 kb
Host smart-fd73d5ec-8c44-41ac-9556-ee73084498d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344183790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.344183790
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3828155256
Short name T999
Test name
Test status
Simulation time 18647646144 ps
CPU time 18.08 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:48 PM PDT 24
Peak memory 216700 kb
Host smart-77bbe7c7-faa5-43ae-b37b-89c85196e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828155256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3828155256
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1692886485
Short name T989
Test name
Test status
Simulation time 59509251 ps
CPU time 1.03 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 208204 kb
Host smart-71839b0e-34e0-475f-be5d-ae37ebd9459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692886485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1692886485
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2306552613
Short name T375
Test name
Test status
Simulation time 80765469 ps
CPU time 0.85 seconds
Started Jul 29 05:11:26 PM PDT 24
Finished Jul 29 05:11:27 PM PDT 24
Peak memory 206308 kb
Host smart-3f2c7e3c-a6d1-47a1-a43a-a941f8d194b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306552613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2306552613
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2789392368
Short name T785
Test name
Test status
Simulation time 492607348 ps
CPU time 8.26 seconds
Started Jul 29 05:11:32 PM PDT 24
Finished Jul 29 05:11:40 PM PDT 24
Peak memory 249480 kb
Host smart-f863971e-3c16-41b4-958e-284a0bf263ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789392368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2789392368
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4112101537
Short name T643
Test name
Test status
Simulation time 20026203 ps
CPU time 0.73 seconds
Started Jul 29 05:09:18 PM PDT 24
Finished Jul 29 05:09:19 PM PDT 24
Peak memory 206020 kb
Host smart-3d7b42e5-cce1-4432-a0ea-d7a98f2dccaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112101537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
112101537
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3194094308
Short name T238
Test name
Test status
Simulation time 4416397408 ps
CPU time 22.83 seconds
Started Jul 29 05:09:09 PM PDT 24
Finished Jul 29 05:09:32 PM PDT 24
Peak memory 233072 kb
Host smart-25d90d2e-66bf-4735-ad7e-0dfa5d0262e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194094308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3194094308
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2499664631
Short name T652
Test name
Test status
Simulation time 20031129 ps
CPU time 0.79 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:09:20 PM PDT 24
Peak memory 205824 kb
Host smart-7e20bfa0-55d1-43dc-84fa-4d0cd57f7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499664631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2499664631
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.728544635
Short name T731
Test name
Test status
Simulation time 13614302149 ps
CPU time 102.21 seconds
Started Jul 29 05:09:17 PM PDT 24
Finished Jul 29 05:10:59 PM PDT 24
Peak memory 238964 kb
Host smart-7526eb6a-5df7-4625-9400-80ef81ecf737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728544635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.728544635
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2800947271
Short name T142
Test name
Test status
Simulation time 13179548466 ps
CPU time 140.03 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:11:39 PM PDT 24
Peak memory 241048 kb
Host smart-72220572-d6d4-4dc1-94c0-448b0d718c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800947271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2800947271
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2804422092
Short name T196
Test name
Test status
Simulation time 4146761725 ps
CPU time 109.08 seconds
Started Jul 29 05:09:13 PM PDT 24
Finished Jul 29 05:11:02 PM PDT 24
Peak memory 252464 kb
Host smart-184805ff-a566-4ec2-b149-25c45f5e30f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804422092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2804422092
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3293278288
Short name T353
Test name
Test status
Simulation time 90432729 ps
CPU time 3.62 seconds
Started Jul 29 05:09:17 PM PDT 24
Finished Jul 29 05:09:21 PM PDT 24
Peak memory 239044 kb
Host smart-93b3f6fc-b3ee-4880-8aa0-3a890423b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293278288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3293278288
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.117876362
Short name T824
Test name
Test status
Simulation time 7171443110 ps
CPU time 56.32 seconds
Started Jul 29 05:09:30 PM PDT 24
Finished Jul 29 05:10:26 PM PDT 24
Peak memory 241336 kb
Host smart-b0d3bfbe-8b5b-4847-a80f-0b5f698e6419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117876362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
117876362
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2320979372
Short name T654
Test name
Test status
Simulation time 149972006 ps
CPU time 3.39 seconds
Started Jul 29 05:09:27 PM PDT 24
Finished Jul 29 05:09:31 PM PDT 24
Peak memory 224732 kb
Host smart-32fe8086-c2b9-4db3-926b-357c9235ed04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320979372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2320979372
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.829560239
Short name T691
Test name
Test status
Simulation time 23070935994 ps
CPU time 36.32 seconds
Started Jul 29 05:09:12 PM PDT 24
Finished Jul 29 05:09:49 PM PDT 24
Peak memory 233336 kb
Host smart-c09c13d8-4f81-43ac-a3d4-5aed53a0740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829560239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.829560239
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.821826530
Short name T723
Test name
Test status
Simulation time 52920936 ps
CPU time 2.24 seconds
Started Jul 29 05:09:16 PM PDT 24
Finished Jul 29 05:09:19 PM PDT 24
Peak memory 224732 kb
Host smart-c350ba40-4f5a-4717-ad65-fe547d75b63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821826530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
821826530
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3628826067
Short name T76
Test name
Test status
Simulation time 2413664766 ps
CPU time 8.85 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:09:28 PM PDT 24
Peak memory 233060 kb
Host smart-d86a38b3-db56-4676-b7c5-9d11a9d7f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628826067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3628826067
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2963692358
Short name T990
Test name
Test status
Simulation time 1278418627 ps
CPU time 9.51 seconds
Started Jul 29 05:09:24 PM PDT 24
Finished Jul 29 05:09:34 PM PDT 24
Peak memory 222400 kb
Host smart-ca5e304d-f81e-4497-b6f3-6ccec00d311a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2963692358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2963692358
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.388895982
Short name T73
Test name
Test status
Simulation time 115773073 ps
CPU time 1.1 seconds
Started Jul 29 05:09:20 PM PDT 24
Finished Jul 29 05:09:21 PM PDT 24
Peak memory 236304 kb
Host smart-73953560-8961-41db-98f9-730c79cafd9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388895982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.388895982
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.631542915
Short name T792
Test name
Test status
Simulation time 45745458 ps
CPU time 1.07 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:37 PM PDT 24
Peak memory 207420 kb
Host smart-ad6ce392-b400-4f1b-85ef-b18df2eea39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631542915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.631542915
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.611719188
Short name T503
Test name
Test status
Simulation time 17468561472 ps
CPU time 24.29 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:09:59 PM PDT 24
Peak memory 216704 kb
Host smart-1f2f7d9c-1c7d-4a94-a69b-ab3bf3cdb760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611719188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.611719188
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4050449263
Short name T711
Test name
Test status
Simulation time 4776049441 ps
CPU time 8.76 seconds
Started Jul 29 05:09:16 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 216656 kb
Host smart-6deb341d-7683-4572-9a4d-ba86603fb5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050449263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4050449263
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2747328903
Short name T896
Test name
Test status
Simulation time 5209427273 ps
CPU time 8.03 seconds
Started Jul 29 05:09:12 PM PDT 24
Finished Jul 29 05:09:20 PM PDT 24
Peak memory 216584 kb
Host smart-f9472778-39c8-4d90-8e38-dc5fbb098a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747328903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2747328903
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2873439599
Short name T395
Test name
Test status
Simulation time 80608823 ps
CPU time 0.84 seconds
Started Jul 29 05:09:08 PM PDT 24
Finished Jul 29 05:09:09 PM PDT 24
Peak memory 206316 kb
Host smart-cdf5a6f5-7316-48ae-ab6e-49588f6b2529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873439599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2873439599
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.852033283
Short name T994
Test name
Test status
Simulation time 549569997 ps
CPU time 2.82 seconds
Started Jul 29 05:09:18 PM PDT 24
Finished Jul 29 05:09:21 PM PDT 24
Peak memory 224880 kb
Host smart-af683ab7-81c2-4f7a-96e6-b333b9c5e7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852033283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.852033283
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.590546612
Short name T424
Test name
Test status
Simulation time 26202665 ps
CPU time 0.69 seconds
Started Jul 29 05:11:39 PM PDT 24
Finished Jul 29 05:11:40 PM PDT 24
Peak memory 205128 kb
Host smart-aeb83e0f-f002-4ba5-b04f-22c82519165e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590546612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.590546612
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.14348554
Short name T420
Test name
Test status
Simulation time 57224234 ps
CPU time 2.07 seconds
Started Jul 29 05:11:30 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 224812 kb
Host smart-83d8117d-3a22-4552-852a-1dc4510f610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14348554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.14348554
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2953186073
Short name T391
Test name
Test status
Simulation time 53242352 ps
CPU time 0.81 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:32 PM PDT 24
Peak memory 206940 kb
Host smart-7265c1a2-f85e-428a-b1b3-61dc7658df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953186073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2953186073
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.617126966
Short name T216
Test name
Test status
Simulation time 2244871142 ps
CPU time 21.89 seconds
Started Jul 29 05:11:36 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 239924 kb
Host smart-444dcb49-d3e2-4525-be0e-9ed295262649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617126966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.617126966
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2621841915
Short name T1006
Test name
Test status
Simulation time 4424308001 ps
CPU time 30.24 seconds
Started Jul 29 05:11:35 PM PDT 24
Finished Jul 29 05:12:06 PM PDT 24
Peak memory 241252 kb
Host smart-54c8669b-5843-492d-8e65-bff5b4e5ad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621841915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2621841915
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2788134114
Short name T497
Test name
Test status
Simulation time 5186159384 ps
CPU time 42.49 seconds
Started Jul 29 05:11:52 PM PDT 24
Finished Jul 29 05:12:34 PM PDT 24
Peak memory 241312 kb
Host smart-24dd809f-2031-4484-bdd2-af2a10461050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788134114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2788134114
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.481309917
Short name T414
Test name
Test status
Simulation time 430748984 ps
CPU time 4.6 seconds
Started Jul 29 05:11:31 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 233048 kb
Host smart-cfe63aa2-a1b6-4eaf-8455-ec92586bbf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481309917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.481309917
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2080168173
Short name T286
Test name
Test status
Simulation time 8036208710 ps
CPU time 113.38 seconds
Started Jul 29 05:11:35 PM PDT 24
Finished Jul 29 05:13:28 PM PDT 24
Peak memory 251480 kb
Host smart-0db63a8f-79a2-4528-9594-1424cd16e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080168173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2080168173
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1143519628
Short name T267
Test name
Test status
Simulation time 7743652221 ps
CPU time 20.28 seconds
Started Jul 29 05:11:34 PM PDT 24
Finished Jul 29 05:11:54 PM PDT 24
Peak memory 233052 kb
Host smart-9375c695-00b3-4c5b-8a77-90209e450f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143519628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1143519628
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2974003402
Short name T259
Test name
Test status
Simulation time 14495819261 ps
CPU time 42.18 seconds
Started Jul 29 05:11:34 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 225192 kb
Host smart-2c97aa86-e9ce-44da-b615-976b3964390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974003402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2974003402
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4205831765
Short name T804
Test name
Test status
Simulation time 675726433 ps
CPU time 5.36 seconds
Started Jul 29 05:11:34 PM PDT 24
Finished Jul 29 05:11:39 PM PDT 24
Peak memory 232960 kb
Host smart-3513a561-6535-47bc-ba3a-b04d881e000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205831765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4205831765
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.132269967
Short name T672
Test name
Test status
Simulation time 521646501 ps
CPU time 4.7 seconds
Started Jul 29 05:11:40 PM PDT 24
Finished Jul 29 05:11:45 PM PDT 24
Peak memory 232988 kb
Host smart-02369f51-781a-4a7a-9858-51f79e52a6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132269967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.132269967
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4212327743
Short name T339
Test name
Test status
Simulation time 182954944 ps
CPU time 3.54 seconds
Started Jul 29 05:11:39 PM PDT 24
Finished Jul 29 05:11:42 PM PDT 24
Peak memory 223072 kb
Host smart-0c9e16d1-9097-477d-b041-e044ee5e492d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4212327743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4212327743
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2002651184
Short name T631
Test name
Test status
Simulation time 317726468471 ps
CPU time 461.13 seconds
Started Jul 29 05:11:38 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 254708 kb
Host smart-95a9e0cb-a969-43eb-a77f-f43e6017bafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002651184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2002651184
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4214315180
Short name T974
Test name
Test status
Simulation time 2538113924 ps
CPU time 7 seconds
Started Jul 29 05:11:33 PM PDT 24
Finished Jul 29 05:11:41 PM PDT 24
Peak memory 216972 kb
Host smart-3fce9777-4983-4a4a-99e1-9062f01cf6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214315180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4214315180
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2439157352
Short name T336
Test name
Test status
Simulation time 7228947612 ps
CPU time 5.23 seconds
Started Jul 29 05:11:40 PM PDT 24
Finished Jul 29 05:11:46 PM PDT 24
Peak memory 217624 kb
Host smart-b1c1489d-966a-4bb2-b65b-fdce36ef7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439157352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2439157352
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1513289582
Short name T77
Test name
Test status
Simulation time 129707313 ps
CPU time 1.19 seconds
Started Jul 29 05:11:34 PM PDT 24
Finished Jul 29 05:11:35 PM PDT 24
Peak memory 208380 kb
Host smart-504d7eac-724c-4b97-b27e-dc976c55a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513289582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1513289582
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3764615839
Short name T370
Test name
Test status
Simulation time 216387174 ps
CPU time 0.86 seconds
Started Jul 29 05:11:47 PM PDT 24
Finished Jul 29 05:11:47 PM PDT 24
Peak memory 207276 kb
Host smart-c81c01c6-6298-4047-a688-2218b1b86884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764615839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3764615839
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3851546385
Short name T904
Test name
Test status
Simulation time 17377380203 ps
CPU time 27.24 seconds
Started Jul 29 05:11:36 PM PDT 24
Finished Jul 29 05:12:03 PM PDT 24
Peak memory 237928 kb
Host smart-e5ae15b4-f9fc-4751-ba61-3b2b2be84b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851546385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3851546385
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3999418016
Short name T864
Test name
Test status
Simulation time 55219777 ps
CPU time 0.74 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:11:44 PM PDT 24
Peak memory 205780 kb
Host smart-24c1e17a-3b56-4044-ba75-f5f807ef59d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999418016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3999418016
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4270642219
Short name T264
Test name
Test status
Simulation time 442207898 ps
CPU time 2.24 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 224828 kb
Host smart-70e5bd3d-ddac-4e8a-bfc5-db38ffe8546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270642219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4270642219
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4096040317
Short name T718
Test name
Test status
Simulation time 14336609 ps
CPU time 0.76 seconds
Started Jul 29 05:11:35 PM PDT 24
Finished Jul 29 05:11:36 PM PDT 24
Peak memory 206880 kb
Host smart-1c2324c5-b6cb-4746-be85-9bb978e9ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096040317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4096040317
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1323104437
Short name T249
Test name
Test status
Simulation time 13817922451 ps
CPU time 84.83 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:13:08 PM PDT 24
Peak memory 256476 kb
Host smart-0a3c82c3-0c4e-4f22-be4c-19aa529accda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323104437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1323104437
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3268958229
Short name T169
Test name
Test status
Simulation time 169096655629 ps
CPU time 239.43 seconds
Started Jul 29 05:11:40 PM PDT 24
Finished Jul 29 05:15:40 PM PDT 24
Peak memory 251740 kb
Host smart-f8922eec-3590-4ac2-8682-c2772a1875c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268958229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3268958229
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2680004988
Short name T285
Test name
Test status
Simulation time 11414333312 ps
CPU time 48.1 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:12:32 PM PDT 24
Peak memory 238712 kb
Host smart-e39a5a1f-d495-4f87-991a-1315f1b44065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680004988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2680004988
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.754028162
Short name T763
Test name
Test status
Simulation time 1144208430 ps
CPU time 5.8 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:11:49 PM PDT 24
Peak memory 224844 kb
Host smart-7a11cd71-5ddf-4af3-8dae-b68bb2eaa2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754028162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.754028162
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2041690240
Short name T438
Test name
Test status
Simulation time 4351927390 ps
CPU time 23.51 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:12:06 PM PDT 24
Peak memory 249512 kb
Host smart-7377adce-c637-44ac-8680-1b473c439dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041690240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2041690240
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1470609338
Short name T849
Test name
Test status
Simulation time 435047738 ps
CPU time 3.4 seconds
Started Jul 29 05:11:37 PM PDT 24
Finished Jul 29 05:11:41 PM PDT 24
Peak memory 224788 kb
Host smart-420e5b84-6c86-4f17-a88a-4e5b4d1e5c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470609338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1470609338
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4238639306
Short name T894
Test name
Test status
Simulation time 4403074934 ps
CPU time 44.84 seconds
Started Jul 29 05:11:38 PM PDT 24
Finished Jul 29 05:12:22 PM PDT 24
Peak memory 232996 kb
Host smart-60e855a1-4bb4-4467-b4e2-feba5fc7ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238639306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4238639306
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1728251274
Short name T256
Test name
Test status
Simulation time 3738096434 ps
CPU time 8.26 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:11:51 PM PDT 24
Peak memory 224940 kb
Host smart-e0123878-1c05-4736-835e-e6e82158bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728251274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1728251274
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1540186461
Short name T649
Test name
Test status
Simulation time 862166457 ps
CPU time 4.87 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:11:48 PM PDT 24
Peak memory 224856 kb
Host smart-e5e7e410-27b4-49fd-a508-c583d7953c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540186461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1540186461
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2273532341
Short name T553
Test name
Test status
Simulation time 1093386619 ps
CPU time 8.02 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:11:49 PM PDT 24
Peak memory 222600 kb
Host smart-9ff545f8-f371-42e2-a400-1ab194775160
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2273532341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2273532341
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1711483392
Short name T13
Test name
Test status
Simulation time 118325317 ps
CPU time 1.17 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 207240 kb
Host smart-f2b85b8b-09da-426d-aa84-48e5f2adcf49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711483392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1711483392
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3915734783
Short name T1
Test name
Test status
Simulation time 6649006601 ps
CPU time 31.72 seconds
Started Jul 29 05:11:39 PM PDT 24
Finished Jul 29 05:12:11 PM PDT 24
Peak memory 216644 kb
Host smart-b846ec44-4d27-4c55-be73-aed6918391ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915734783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3915734783
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2902307231
Short name T744
Test name
Test status
Simulation time 36356060723 ps
CPU time 19.21 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:12:00 PM PDT 24
Peak memory 216536 kb
Host smart-cbd564b7-b886-4c79-aee0-805a9f1e6d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902307231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2902307231
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1151819573
Short name T465
Test name
Test status
Simulation time 356938626 ps
CPU time 2.92 seconds
Started Jul 29 05:11:39 PM PDT 24
Finished Jul 29 05:11:42 PM PDT 24
Peak memory 216564 kb
Host smart-5ea02dd7-d1a3-4b8a-b4b0-a3421b755567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151819573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1151819573
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3830458738
Short name T668
Test name
Test status
Simulation time 24068943 ps
CPU time 0.86 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:11:44 PM PDT 24
Peak memory 206284 kb
Host smart-630ba7d1-e42f-4479-bc02-4ddd1753e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830458738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3830458738
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3771975711
Short name T614
Test name
Test status
Simulation time 135345532 ps
CPU time 2.52 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:11:44 PM PDT 24
Peak memory 233068 kb
Host smart-8ad89680-5d82-429d-8c08-7b8217e538ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771975711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3771975711
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.505996677
Short name T594
Test name
Test status
Simulation time 39251671 ps
CPU time 0.69 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:11:48 PM PDT 24
Peak memory 205232 kb
Host smart-1107a02e-da49-4317-b416-a761b975b0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505996677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.505996677
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2385294128
Short name T583
Test name
Test status
Simulation time 38216343 ps
CPU time 2.55 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 232948 kb
Host smart-382bfe62-9927-4e55-863b-2d81c6c64132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385294128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2385294128
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2723023377
Short name T512
Test name
Test status
Simulation time 77412314 ps
CPU time 0.81 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 206972 kb
Host smart-7baec2e0-c605-4d33-8dfb-05c455698b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723023377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2723023377
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.816510702
Short name T210
Test name
Test status
Simulation time 3009442677 ps
CPU time 67.12 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:12:55 PM PDT 24
Peak memory 268068 kb
Host smart-b486a801-2956-4d6d-b294-82b4732ced1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816510702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.816510702
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4114826078
Short name T276
Test name
Test status
Simulation time 272133786932 ps
CPU time 319.34 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:17:07 PM PDT 24
Peak memory 264268 kb
Host smart-363841f3-2cd7-4a9f-86e9-7bbff6f1d4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114826078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4114826078
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2166813846
Short name T283
Test name
Test status
Simulation time 2521207370 ps
CPU time 49.5 seconds
Started Jul 29 05:11:47 PM PDT 24
Finished Jul 29 05:12:36 PM PDT 24
Peak memory 240980 kb
Host smart-93cfdee0-5b75-4ddb-900d-d5f4b2c93905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166813846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2166813846
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.724113772
Short name T818
Test name
Test status
Simulation time 412591956 ps
CPU time 8.58 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:11:57 PM PDT 24
Peak memory 224824 kb
Host smart-d62d71a9-5827-4278-9b37-248eedb68dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724113772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.724113772
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3338320678
Short name T42
Test name
Test status
Simulation time 14567467277 ps
CPU time 111.28 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:13:34 PM PDT 24
Peak memory 249624 kb
Host smart-a31f4a94-013f-4431-8633-fae36fd72573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338320678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3338320678
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.557932906
Short name T261
Test name
Test status
Simulation time 1487154920 ps
CPU time 17.58 seconds
Started Jul 29 05:11:43 PM PDT 24
Finished Jul 29 05:12:01 PM PDT 24
Peak memory 233132 kb
Host smart-b2a46b12-7cbf-444a-a480-4f5bc30fb2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557932906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.557932906
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.942840369
Short name T776
Test name
Test status
Simulation time 1387178118 ps
CPU time 20.41 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:12:02 PM PDT 24
Peak memory 232936 kb
Host smart-d0cb8fcd-24fe-4677-8c53-d5cf6bf9c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942840369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.942840369
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2556964470
Short name T613
Test name
Test status
Simulation time 175561855 ps
CPU time 3.09 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:11:45 PM PDT 24
Peak memory 233048 kb
Host smart-03cfd255-2f63-4fbb-a640-3cc9f4b3047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556964470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2556964470
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4177974030
Short name T458
Test name
Test status
Simulation time 37465443 ps
CPU time 2.48 seconds
Started Jul 29 05:11:47 PM PDT 24
Finished Jul 29 05:11:50 PM PDT 24
Peak memory 233044 kb
Host smart-11cbfa53-d901-4a6c-8f91-da8294d212fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177974030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4177974030
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1950128055
Short name T960
Test name
Test status
Simulation time 676627643 ps
CPU time 7.04 seconds
Started Jul 29 05:11:47 PM PDT 24
Finished Jul 29 05:11:54 PM PDT 24
Peak memory 222508 kb
Host smart-ef3c4407-bd9b-47a6-8fd8-0bc120cff3d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1950128055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1950128055
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.74280303
Short name T1000
Test name
Test status
Simulation time 21968327888 ps
CPU time 112.58 seconds
Started Jul 29 05:11:50 PM PDT 24
Finished Jul 29 05:13:42 PM PDT 24
Peak memory 252060 kb
Host smart-837dd65e-7eab-440e-94c9-ae1743fbb7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74280303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress
_all.74280303
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.479687713
Short name T910
Test name
Test status
Simulation time 7099335881 ps
CPU time 33.88 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 220248 kb
Host smart-505fe2aa-e9c6-4bf3-9038-e56795faed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479687713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.479687713
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.656420500
Short name T476
Test name
Test status
Simulation time 4356592210 ps
CPU time 14.14 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:11:56 PM PDT 24
Peak memory 216628 kb
Host smart-46a3aa58-87c7-4527-bc71-7f7eff7cfefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656420500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.656420500
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.566112388
Short name T579
Test name
Test status
Simulation time 489084066 ps
CPU time 5.23 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:11:47 PM PDT 24
Peak memory 216548 kb
Host smart-d5d10408-4569-42ae-9861-90f051ab2ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566112388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.566112388
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2764087803
Short name T698
Test name
Test status
Simulation time 28555789 ps
CPU time 0.82 seconds
Started Jul 29 05:11:42 PM PDT 24
Finished Jul 29 05:11:43 PM PDT 24
Peak memory 206240 kb
Host smart-140527dc-1705-4b1b-a695-b67c43d5da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764087803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2764087803
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1789374954
Short name T701
Test name
Test status
Simulation time 1133575765 ps
CPU time 5.62 seconds
Started Jul 29 05:11:41 PM PDT 24
Finished Jul 29 05:11:46 PM PDT 24
Peak memory 233072 kb
Host smart-04726eb5-2444-44ec-9397-8e1e2f851255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789374954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1789374954
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1063676222
Short name T321
Test name
Test status
Simulation time 15189134 ps
CPU time 0.75 seconds
Started Jul 29 05:11:54 PM PDT 24
Finished Jul 29 05:11:55 PM PDT 24
Peak memory 205116 kb
Host smart-aced2aeb-a123-4604-afff-9a21e5bc2ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063676222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1063676222
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.628902819
Short name T428
Test name
Test status
Simulation time 1590373132 ps
CPU time 2.66 seconds
Started Jul 29 05:11:54 PM PDT 24
Finished Jul 29 05:11:57 PM PDT 24
Peak memory 224772 kb
Host smart-fcd82f75-f2cf-407a-a245-89a69d189690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628902819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.628902819
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.807893
Short name T364
Test name
Test status
Simulation time 59463495 ps
CPU time 0.77 seconds
Started Jul 29 05:11:50 PM PDT 24
Finished Jul 29 05:11:51 PM PDT 24
Peak memory 206152 kb
Host smart-1697edde-92fd-410e-b14b-1e5fb161e886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.807893
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2138676247
Short name T281
Test name
Test status
Simulation time 237893253728 ps
CPU time 393.81 seconds
Started Jul 29 05:11:56 PM PDT 24
Finished Jul 29 05:18:30 PM PDT 24
Peak memory 265812 kb
Host smart-0a252a66-723b-43e4-a750-cda73e885649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138676247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2138676247
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2667155693
Short name T803
Test name
Test status
Simulation time 20548136985 ps
CPU time 43.15 seconds
Started Jul 29 05:11:56 PM PDT 24
Finished Jul 29 05:12:39 PM PDT 24
Peak memory 256468 kb
Host smart-bd241030-6b26-4eff-b074-8c72a241314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667155693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2667155693
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2020894187
Short name T58
Test name
Test status
Simulation time 22885799349 ps
CPU time 106.81 seconds
Started Jul 29 05:11:56 PM PDT 24
Finished Jul 29 05:13:43 PM PDT 24
Peak memory 249944 kb
Host smart-b8b1dcfe-e2f9-4cef-90d6-3b0f959c9275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020894187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2020894187
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2049481265
Short name T137
Test name
Test status
Simulation time 189040531 ps
CPU time 2.71 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:11:57 PM PDT 24
Peak memory 233016 kb
Host smart-195d49ff-7bf8-4093-bf09-9f63ab0125b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049481265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2049481265
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2036561782
Short name T266
Test name
Test status
Simulation time 1718831105 ps
CPU time 7.72 seconds
Started Jul 29 05:11:50 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 224748 kb
Host smart-60a901fe-438f-4da7-a44d-b84a36ffc4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036561782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2036561782
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1969519000
Short name T234
Test name
Test status
Simulation time 2326018231 ps
CPU time 11.8 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:12:00 PM PDT 24
Peak memory 233120 kb
Host smart-d21354fa-11bb-486d-8359-2b600fcfe014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969519000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1969519000
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2566265601
Short name T680
Test name
Test status
Simulation time 9648362965 ps
CPU time 8.35 seconds
Started Jul 29 05:11:49 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 224920 kb
Host smart-86fb295e-a81d-477e-8a8a-7b52cab72f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566265601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2566265601
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4216230263
Short name T927
Test name
Test status
Simulation time 3833133204 ps
CPU time 9.7 seconds
Started Jul 29 05:11:49 PM PDT 24
Finished Jul 29 05:11:59 PM PDT 24
Peak memory 224960 kb
Host smart-39fd08ae-3a92-4500-af32-aff62f5f8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216230263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4216230263
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1353580401
Short name T566
Test name
Test status
Simulation time 527718996 ps
CPU time 6.84 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:12:02 PM PDT 24
Peak memory 221896 kb
Host smart-c3bf6633-93ea-48cf-b7cf-eb38affd1deb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1353580401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1353580401
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3062700185
Short name T78
Test name
Test status
Simulation time 55762907895 ps
CPU time 156.11 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:14:31 PM PDT 24
Peak memory 251080 kb
Host smart-e8a3af1d-7b5e-44ec-9c6d-a7d0b2c685d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062700185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3062700185
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3289465952
Short name T537
Test name
Test status
Simulation time 42612742210 ps
CPU time 27.48 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 216520 kb
Host smart-755ac466-c1fa-4675-94ec-447e0892c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289465952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3289465952
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3420624577
Short name T742
Test name
Test status
Simulation time 43463278136 ps
CPU time 8.74 seconds
Started Jul 29 05:11:49 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 216628 kb
Host smart-cecc0eed-f305-4dd1-b154-06b352477bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420624577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3420624577
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.978711268
Short name T772
Test name
Test status
Simulation time 94042220 ps
CPU time 1.04 seconds
Started Jul 29 05:11:48 PM PDT 24
Finished Jul 29 05:11:49 PM PDT 24
Peak memory 208184 kb
Host smart-b9a82db4-0a9c-4584-a2be-69e3c5a2ac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978711268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.978711268
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1474395913
Short name T743
Test name
Test status
Simulation time 277349263 ps
CPU time 0.8 seconds
Started Jul 29 05:11:49 PM PDT 24
Finished Jul 29 05:11:50 PM PDT 24
Peak memory 206332 kb
Host smart-f6d3d8e2-73a5-4e62-9775-95a5afe4a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474395913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1474395913
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3467952023
Short name T822
Test name
Test status
Simulation time 6568375440 ps
CPU time 27.26 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:12:22 PM PDT 24
Peak memory 233108 kb
Host smart-375c9a13-cf97-4bb4-a7a5-e5fe26085446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467952023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3467952023
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4089641908
Short name T826
Test name
Test status
Simulation time 97715021 ps
CPU time 0.73 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:02 PM PDT 24
Peak memory 205644 kb
Host smart-c632cc7c-4b8a-4ef8-be96-0772a56b6848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089641908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4089641908
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3390776072
Short name T30
Test name
Test status
Simulation time 871378151 ps
CPU time 4.05 seconds
Started Jul 29 05:11:57 PM PDT 24
Finished Jul 29 05:12:01 PM PDT 24
Peak memory 224812 kb
Host smart-15d9a8bd-1f8b-46db-839e-139c48898899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390776072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3390776072
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.943004357
Short name T559
Test name
Test status
Simulation time 32296226 ps
CPU time 0.77 seconds
Started Jul 29 05:11:54 PM PDT 24
Finished Jul 29 05:11:55 PM PDT 24
Peak memory 205812 kb
Host smart-1db2da94-3f68-40dd-91dc-aa88fe047322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943004357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.943004357
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.795853368
Short name T913
Test name
Test status
Simulation time 42176893289 ps
CPU time 227.23 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:15:48 PM PDT 24
Peak memory 254076 kb
Host smart-d23a9b23-0f70-4823-916a-da62460d3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795853368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.795853368
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3482511802
Short name T980
Test name
Test status
Simulation time 5608954381 ps
CPU time 22.64 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:24 PM PDT 24
Peak memory 217908 kb
Host smart-20f72d79-2d9e-47da-b40b-bcdffcfe07c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482511802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3482511802
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3584827606
Short name T997
Test name
Test status
Simulation time 3130295921 ps
CPU time 26.87 seconds
Started Jul 29 05:12:03 PM PDT 24
Finished Jul 29 05:12:30 PM PDT 24
Peak memory 218148 kb
Host smart-9ffc604f-3416-4a1d-b868-483ce7eff7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584827606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3584827606
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1219020743
Short name T54
Test name
Test status
Simulation time 638821326 ps
CPU time 7.57 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:08 PM PDT 24
Peak memory 235944 kb
Host smart-8496711c-b00b-48aa-9d65-7a9664859230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219020743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1219020743
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1756879954
Short name T859
Test name
Test status
Simulation time 698644034 ps
CPU time 17.97 seconds
Started Jul 29 05:12:02 PM PDT 24
Finished Jul 29 05:12:20 PM PDT 24
Peak memory 249368 kb
Host smart-8d017122-7d86-4670-8a20-e7357c02cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756879954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1756879954
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.142646287
Short name T523
Test name
Test status
Simulation time 3869253743 ps
CPU time 11.57 seconds
Started Jul 29 05:11:54 PM PDT 24
Finished Jul 29 05:12:06 PM PDT 24
Peak memory 233084 kb
Host smart-9cd6409e-b2c1-4d21-a88a-68bd2627243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142646287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.142646287
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3113868020
Short name T871
Test name
Test status
Simulation time 911567852 ps
CPU time 6.16 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:12:02 PM PDT 24
Peak memory 232928 kb
Host smart-b91f9dfb-15cb-4a40-a9bf-a56c2c5dfd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113868020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3113868020
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2442156561
Short name T296
Test name
Test status
Simulation time 907469031 ps
CPU time 5.91 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:12:01 PM PDT 24
Peak memory 232964 kb
Host smart-0077fd0d-29e5-4844-83dc-9101a884ffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442156561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2442156561
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.438716296
Short name T717
Test name
Test status
Simulation time 676744091 ps
CPU time 5.84 seconds
Started Jul 29 05:11:54 PM PDT 24
Finished Jul 29 05:12:00 PM PDT 24
Peak memory 233008 kb
Host smart-7e6af822-ab5c-4383-9104-dd5f789cd8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438716296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.438716296
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2921834385
Short name T425
Test name
Test status
Simulation time 378959137 ps
CPU time 3.78 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:05 PM PDT 24
Peak memory 223372 kb
Host smart-6eae7c01-daa2-4c1a-a812-503ab9c0c59c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2921834385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2921834385
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2252887762
Short name T588
Test name
Test status
Simulation time 3425973117 ps
CPU time 7.75 seconds
Started Jul 29 05:12:00 PM PDT 24
Finished Jul 29 05:12:08 PM PDT 24
Peak memory 224816 kb
Host smart-87bcde64-c5b6-46a6-8110-9cb8bbe3282c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252887762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2252887762
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3867382182
Short name T390
Test name
Test status
Simulation time 6862914528 ps
CPU time 8.85 seconds
Started Jul 29 05:11:56 PM PDT 24
Finished Jul 29 05:12:05 PM PDT 24
Peak memory 216592 kb
Host smart-1a7b989c-1ffb-4389-b305-154882af6f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867382182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3867382182
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2106164615
Short name T143
Test name
Test status
Simulation time 6223889940 ps
CPU time 12.77 seconds
Started Jul 29 05:11:56 PM PDT 24
Finished Jul 29 05:12:09 PM PDT 24
Peak memory 216680 kb
Host smart-c35363fe-d023-4bf6-af35-3a6d88589df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106164615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2106164615
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3975635988
Short name T907
Test name
Test status
Simulation time 77718759 ps
CPU time 1.01 seconds
Started Jul 29 05:11:57 PM PDT 24
Finished Jul 29 05:11:58 PM PDT 24
Peak memory 207316 kb
Host smart-1043fc1e-0127-40dc-9bb6-c161b9f9f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975635988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3975635988
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2146667428
Short name T880
Test name
Test status
Simulation time 17510466 ps
CPU time 0.73 seconds
Started Jul 29 05:11:55 PM PDT 24
Finished Jul 29 05:11:56 PM PDT 24
Peak memory 206280 kb
Host smart-63d03967-3c5d-4424-a860-aec083782896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146667428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2146667428
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.592825571
Short name T231
Test name
Test status
Simulation time 22379635705 ps
CPU time 17.44 seconds
Started Jul 29 05:11:56 PM PDT 24
Finished Jul 29 05:12:13 PM PDT 24
Peak memory 240096 kb
Host smart-195605c2-bf65-4f95-bc80-3392f8af563c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592825571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.592825571
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4163573054
Short name T704
Test name
Test status
Simulation time 31797564 ps
CPU time 0.74 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:08 PM PDT 24
Peak memory 205656 kb
Host smart-5bfe547d-ff06-40c4-95f4-2a203c8f8ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163573054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4163573054
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1277350360
Short name T929
Test name
Test status
Simulation time 445952620 ps
CPU time 2.89 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:04 PM PDT 24
Peak memory 233112 kb
Host smart-77ee1430-a7da-48d2-a46b-915bc2f25961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277350360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1277350360
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3794964641
Short name T351
Test name
Test status
Simulation time 26649466 ps
CPU time 0.76 seconds
Started Jul 29 05:12:04 PM PDT 24
Finished Jul 29 05:12:05 PM PDT 24
Peak memory 206924 kb
Host smart-1846e936-0300-4f62-b4c4-5224e6eca610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794964641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3794964641
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4162694244
Short name T356
Test name
Test status
Simulation time 2407260708 ps
CPU time 17.36 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:25 PM PDT 24
Peak memory 255608 kb
Host smart-6c2e061a-5b27-4cc2-ae63-7b689a9655d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162694244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4162694244
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2992136642
Short name T886
Test name
Test status
Simulation time 55928118618 ps
CPU time 201.99 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:15:29 PM PDT 24
Peak memory 268428 kb
Host smart-47a75ba1-7dc9-4e31-80fe-e456383a5169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992136642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2992136642
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3553705508
Short name T958
Test name
Test status
Simulation time 34706993609 ps
CPU time 254.8 seconds
Started Jul 29 05:12:09 PM PDT 24
Finished Jul 29 05:16:24 PM PDT 24
Peak memory 255672 kb
Host smart-5116cee2-3493-4536-b9f6-0e7a59bc2ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553705508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3553705508
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.40533382
Short name T659
Test name
Test status
Simulation time 41237206 ps
CPU time 2.84 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:10 PM PDT 24
Peak memory 232988 kb
Host smart-1978e565-7ddf-4fbb-88e3-243dfeee07f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40533382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.40533382
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1839095152
Short name T423
Test name
Test status
Simulation time 16554345042 ps
CPU time 27.35 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:35 PM PDT 24
Peak memory 224896 kb
Host smart-1235ce51-02c8-4eff-92d0-7a51c778f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839095152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1839095152
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1820659457
Short name T848
Test name
Test status
Simulation time 6346697025 ps
CPU time 5.62 seconds
Started Jul 29 05:12:02 PM PDT 24
Finished Jul 29 05:12:07 PM PDT 24
Peak memory 224960 kb
Host smart-86480d99-7b75-496c-9d08-feb1166a8c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820659457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1820659457
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1018015093
Short name T771
Test name
Test status
Simulation time 11192601829 ps
CPU time 19.85 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:21 PM PDT 24
Peak memory 224864 kb
Host smart-d894068f-30b0-4a95-9083-b3e1ea3bbf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018015093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1018015093
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2904896159
Short name T475
Test name
Test status
Simulation time 406985460 ps
CPU time 5.62 seconds
Started Jul 29 05:12:01 PM PDT 24
Finished Jul 29 05:12:07 PM PDT 24
Peak memory 224732 kb
Host smart-dc0ba922-e4bb-4203-9fa9-b7ce1b37e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904896159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2904896159
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2053509556
Short name T870
Test name
Test status
Simulation time 681901246 ps
CPU time 2.81 seconds
Started Jul 29 05:12:00 PM PDT 24
Finished Jul 29 05:12:03 PM PDT 24
Peak memory 224848 kb
Host smart-06a88d99-3fcf-473b-89a9-ddd8cff65db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053509556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2053509556
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3364861552
Short name T843
Test name
Test status
Simulation time 1658080844 ps
CPU time 7.78 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 223212 kb
Host smart-df06efbe-7e26-4986-ae97-8ab731317e03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3364861552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3364861552
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2754129499
Short name T444
Test name
Test status
Simulation time 7484395300 ps
CPU time 94.86 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:13:49 PM PDT 24
Peak memory 250196 kb
Host smart-51c1a4e0-977a-4680-8066-5dd9be0b8280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754129499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2754129499
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.109700958
Short name T633
Test name
Test status
Simulation time 22488539274 ps
CPU time 30.41 seconds
Started Jul 29 05:12:02 PM PDT 24
Finished Jul 29 05:12:32 PM PDT 24
Peak memory 216708 kb
Host smart-68cd1853-f0ab-4fc5-bb08-96eb7741d063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109700958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.109700958
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1045548827
Short name T728
Test name
Test status
Simulation time 400553004 ps
CPU time 2.78 seconds
Started Jul 29 05:12:00 PM PDT 24
Finished Jul 29 05:12:03 PM PDT 24
Peak memory 216596 kb
Host smart-88ce73c3-6440-4240-9241-18197fcdea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045548827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1045548827
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3167764502
Short name T546
Test name
Test status
Simulation time 28696515 ps
CPU time 1.16 seconds
Started Jul 29 05:12:02 PM PDT 24
Finished Jul 29 05:12:03 PM PDT 24
Peak memory 216572 kb
Host smart-d92dd45a-bbe3-4853-b3e6-f82832187cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167764502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3167764502
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2258006157
Short name T310
Test name
Test status
Simulation time 17596813 ps
CPU time 0.71 seconds
Started Jul 29 05:12:03 PM PDT 24
Finished Jul 29 05:12:04 PM PDT 24
Peak memory 205948 kb
Host smart-0561d38d-1f6a-4c3f-93df-54207b16d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258006157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2258006157
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.334205208
Short name T967
Test name
Test status
Simulation time 226307220 ps
CPU time 4.98 seconds
Started Jul 29 05:12:02 PM PDT 24
Finished Jul 29 05:12:07 PM PDT 24
Peak memory 240180 kb
Host smart-6b955c64-33ac-434d-b2f0-90a5695cef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334205208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.334205208
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.507512179
Short name T892
Test name
Test status
Simulation time 72007186 ps
CPU time 0.71 seconds
Started Jul 29 05:12:09 PM PDT 24
Finished Jul 29 05:12:10 PM PDT 24
Peak memory 205732 kb
Host smart-7c9372dd-8139-401c-9a14-925adfcee78b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507512179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.507512179
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1826648250
Short name T81
Test name
Test status
Simulation time 244013562 ps
CPU time 5.11 seconds
Started Jul 29 05:12:08 PM PDT 24
Finished Jul 29 05:12:14 PM PDT 24
Peak memory 233100 kb
Host smart-a3f207db-61e4-47d3-8449-b0829e2ee6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826648250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1826648250
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.383804445
Short name T446
Test name
Test status
Simulation time 13742594 ps
CPU time 0.76 seconds
Started Jul 29 05:12:08 PM PDT 24
Finished Jul 29 05:12:09 PM PDT 24
Peak memory 206876 kb
Host smart-e57cd773-c57c-44fb-9fff-45c30d558723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383804445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.383804445
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3591954811
Short name T432
Test name
Test status
Simulation time 58175801042 ps
CPU time 196.83 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:15:30 PM PDT 24
Peak memory 253984 kb
Host smart-cf0fd159-0a2a-49de-b600-2e8a2a09694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591954811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3591954811
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2380571618
Short name T308
Test name
Test status
Simulation time 28498990308 ps
CPU time 232.17 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:16:05 PM PDT 24
Peak memory 250828 kb
Host smart-1c551570-d785-4026-a308-3268b032dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380571618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2380571618
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.160656409
Short name T406
Test name
Test status
Simulation time 501038812 ps
CPU time 3.6 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 233328 kb
Host smart-3e117696-ed61-4ee9-b400-ca5bcefb861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160656409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.160656409
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.189676228
Short name T246
Test name
Test status
Simulation time 6518647566 ps
CPU time 87.08 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 241396 kb
Host smart-61276382-a78f-4d92-a6e4-380181977dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189676228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.189676228
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2007753457
Short name T139
Test name
Test status
Simulation time 2502771485 ps
CPU time 20 seconds
Started Jul 29 05:12:08 PM PDT 24
Finished Jul 29 05:12:28 PM PDT 24
Peak memory 233132 kb
Host smart-3ddd0380-ca60-47af-9589-ec1cd1594486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007753457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2007753457
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.53976002
Short name T239
Test name
Test status
Simulation time 1822649627 ps
CPU time 11.24 seconds
Started Jul 29 05:12:15 PM PDT 24
Finished Jul 29 05:12:26 PM PDT 24
Peak memory 240812 kb
Host smart-48d27193-581e-4659-a8d4-e2b1affe2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53976002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.53976002
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3063266342
Short name T949
Test name
Test status
Simulation time 5502835086 ps
CPU time 13.24 seconds
Started Jul 29 05:12:09 PM PDT 24
Finished Jul 29 05:12:22 PM PDT 24
Peak memory 224920 kb
Host smart-4fcbf3fd-0a71-427e-b325-e784181e81e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063266342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3063266342
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3922440141
Short name T715
Test name
Test status
Simulation time 5568082637 ps
CPU time 7.14 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:21 PM PDT 24
Peak memory 233056 kb
Host smart-7eb7f898-12e8-4309-9bf7-21ff593711d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922440141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3922440141
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.128217648
Short name T935
Test name
Test status
Simulation time 1798120642 ps
CPU time 6.97 seconds
Started Jul 29 05:12:06 PM PDT 24
Finished Jul 29 05:12:13 PM PDT 24
Peak memory 220752 kb
Host smart-3ea0b079-9837-454b-a8c7-45d94dbcc0f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=128217648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.128217648
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3696148573
Short name T303
Test name
Test status
Simulation time 57899318508 ps
CPU time 33.31 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:46 PM PDT 24
Peak memory 217032 kb
Host smart-72664539-2604-445e-b578-70f1fa07869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696148573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3696148573
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1122631404
Short name T464
Test name
Test status
Simulation time 3166540016 ps
CPU time 6.46 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:14 PM PDT 24
Peak memory 216568 kb
Host smart-13906e42-db75-4b18-8d1c-6ea56a917242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122631404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1122631404
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2545051274
Short name T344
Test name
Test status
Simulation time 747609246 ps
CPU time 3.22 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:17 PM PDT 24
Peak memory 216584 kb
Host smart-b7a6a4eb-6a6e-48fe-9597-362ebc5732c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545051274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2545051274
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2815775351
Short name T677
Test name
Test status
Simulation time 78988500 ps
CPU time 0.87 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 207272 kb
Host smart-d1325484-9777-4465-a2e2-830f5caaf64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815775351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2815775351
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2726380454
Short name T939
Test name
Test status
Simulation time 98297607 ps
CPU time 2.11 seconds
Started Jul 29 05:12:06 PM PDT 24
Finished Jul 29 05:12:08 PM PDT 24
Peak memory 224428 kb
Host smart-24a843b3-90cc-44c7-b716-7f90441d2989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726380454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2726380454
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.75253617
Short name T345
Test name
Test status
Simulation time 18962771 ps
CPU time 0.72 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:13 PM PDT 24
Peak memory 206028 kb
Host smart-270674b3-b7f5-41d2-bea3-f0e5e297fa99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75253617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.75253617
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.780048001
Short name T773
Test name
Test status
Simulation time 756825591 ps
CPU time 3.29 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 224808 kb
Host smart-f2133d32-0bae-4c60-85f2-0ff329577941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780048001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.780048001
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.704341183
Short name T916
Test name
Test status
Simulation time 48074881 ps
CPU time 0.75 seconds
Started Jul 29 05:12:08 PM PDT 24
Finished Jul 29 05:12:09 PM PDT 24
Peak memory 205880 kb
Host smart-09b835bc-2d6d-4c32-8acf-3e1dc2292730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704341183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.704341183
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4012935572
Short name T530
Test name
Test status
Simulation time 1016948395 ps
CPU time 9.02 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:12:22 PM PDT 24
Peak memory 234588 kb
Host smart-913554c4-2813-4906-893a-8245bc3cd9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012935572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4012935572
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2736089002
Short name T411
Test name
Test status
Simulation time 64481152811 ps
CPU time 135.02 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:14:28 PM PDT 24
Peak memory 249532 kb
Host smart-b0b2f6af-2f8c-41d4-aa4b-ddd1dbb2b6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736089002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2736089002
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.110369288
Short name T82
Test name
Test status
Simulation time 12640193182 ps
CPU time 74.7 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:13:27 PM PDT 24
Peak memory 256644 kb
Host smart-a2c974c0-68f9-4509-806c-f342a3210053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110369288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.110369288
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1019266754
Short name T467
Test name
Test status
Simulation time 12202296023 ps
CPU time 34.24 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:12:48 PM PDT 24
Peak memory 241368 kb
Host smart-f08f132d-685d-48da-ac5a-d3224267d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019266754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1019266754
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2713220810
Short name T433
Test name
Test status
Simulation time 26786347293 ps
CPU time 50.8 seconds
Started Jul 29 05:12:15 PM PDT 24
Finished Jul 29 05:13:06 PM PDT 24
Peak memory 233224 kb
Host smart-52c46ecf-13e3-459a-9012-dc659492d791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713220810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2713220810
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4244573475
Short name T99
Test name
Test status
Simulation time 443661861 ps
CPU time 5.58 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:18 PM PDT 24
Peak memory 220088 kb
Host smart-f4f478f7-5db5-4d12-bf95-535a255ba377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244573475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4244573475
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3986184181
Short name T567
Test name
Test status
Simulation time 4828166966 ps
CPU time 31.58 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:43 PM PDT 24
Peak memory 233200 kb
Host smart-b81cf665-2bb4-4742-a061-04aace1d4353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986184181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3986184181
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3220112491
Short name T982
Test name
Test status
Simulation time 4637930053 ps
CPU time 13.64 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 224896 kb
Host smart-f8a5cbee-7872-44d4-a4a2-3a1e59ee5a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220112491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3220112491
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2459661186
Short name T841
Test name
Test status
Simulation time 774927618 ps
CPU time 3.26 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 233072 kb
Host smart-28344dbc-fefb-45fc-93cd-585ab9b0b5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459661186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2459661186
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1288087395
Short name T739
Test name
Test status
Simulation time 3195786522 ps
CPU time 7.11 seconds
Started Jul 29 05:12:18 PM PDT 24
Finished Jul 29 05:12:25 PM PDT 24
Peak memory 223056 kb
Host smart-6f29962b-111f-402b-81ff-582067a1d97e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1288087395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1288087395
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1068203609
Short name T162
Test name
Test status
Simulation time 254914059 ps
CPU time 1.16 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 207580 kb
Host smart-233e7a90-a747-4ffc-a3e9-b662094e1984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068203609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1068203609
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.178992692
Short name T881
Test name
Test status
Simulation time 2602734651 ps
CPU time 23.56 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:38 PM PDT 24
Peak memory 216856 kb
Host smart-ccfb6a62-9561-4c58-a690-9bef102bd56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178992692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.178992692
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1288741643
Short name T369
Test name
Test status
Simulation time 2155240017 ps
CPU time 6.91 seconds
Started Jul 29 05:12:07 PM PDT 24
Finished Jul 29 05:12:14 PM PDT 24
Peak memory 216592 kb
Host smart-6381f67f-a81c-41a2-8f41-dc20ee7b543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288741643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1288741643
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3737254718
Short name T865
Test name
Test status
Simulation time 244847651 ps
CPU time 0.8 seconds
Started Jul 29 05:12:15 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 206932 kb
Host smart-10ca6d35-e6b9-4a0f-b233-07e607103589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737254718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3737254718
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3342424434
Short name T4
Test name
Test status
Simulation time 37985806 ps
CPU time 0.88 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:20 PM PDT 24
Peak memory 207264 kb
Host smart-a8d5d9af-75a1-4d40-948a-ab799b42045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342424434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3342424434
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.430561986
Short name T644
Test name
Test status
Simulation time 1614374616 ps
CPU time 6.89 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:19 PM PDT 24
Peak memory 224832 kb
Host smart-eef63ac8-92b5-4a01-aaae-b5278ab6243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430561986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.430561986
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.423034380
Short name T442
Test name
Test status
Simulation time 36083684 ps
CPU time 0.71 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:19 PM PDT 24
Peak memory 205168 kb
Host smart-074d8e80-d6ca-4c0a-9be6-b2032d71de99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423034380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.423034380
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3699893047
Short name T936
Test name
Test status
Simulation time 3217517320 ps
CPU time 7.89 seconds
Started Jul 29 05:12:20 PM PDT 24
Finished Jul 29 05:12:28 PM PDT 24
Peak memory 224812 kb
Host smart-56faba0d-eddb-4c28-9653-df41a953be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699893047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3699893047
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2984272820
Short name T324
Test name
Test status
Simulation time 34497492 ps
CPU time 0.76 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:12:14 PM PDT 24
Peak memory 207252 kb
Host smart-308d6987-05d9-4df5-b506-5ba8e28f04cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984272820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2984272820
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2171592512
Short name T517
Test name
Test status
Simulation time 89760474968 ps
CPU time 168.92 seconds
Started Jul 29 05:12:17 PM PDT 24
Finished Jul 29 05:15:07 PM PDT 24
Peak memory 256708 kb
Host smart-8e9e5915-65e4-4815-bbec-96de2b1f9340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171592512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2171592512
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.524779149
Short name T639
Test name
Test status
Simulation time 9756841553 ps
CPU time 31.38 seconds
Started Jul 29 05:12:20 PM PDT 24
Finished Jul 29 05:12:51 PM PDT 24
Peak memory 225004 kb
Host smart-1188f4f8-e45f-4e90-8dfc-3404e3583fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524779149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.524779149
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3357865934
Short name T970
Test name
Test status
Simulation time 9862239245 ps
CPU time 81.75 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:13:41 PM PDT 24
Peak memory 249552 kb
Host smart-4d676d98-3089-4ca2-a09d-bc332d211045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357865934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3357865934
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2632055090
Short name T890
Test name
Test status
Simulation time 82650012 ps
CPU time 3.34 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:12:24 PM PDT 24
Peak memory 233108 kb
Host smart-6c6637ec-2a89-40c2-bdf9-febcccaddc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632055090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2632055090
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2314928890
Short name T25
Test name
Test status
Simulation time 31739471 ps
CPU time 2.09 seconds
Started Jul 29 05:12:20 PM PDT 24
Finished Jul 29 05:12:22 PM PDT 24
Peak memory 232764 kb
Host smart-32f324b9-68b7-4588-bce8-096840c0b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314928890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2314928890
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.691255566
Short name T450
Test name
Test status
Simulation time 103137859 ps
CPU time 2.32 seconds
Started Jul 29 05:12:23 PM PDT 24
Finished Jul 29 05:12:26 PM PDT 24
Peak memory 232764 kb
Host smart-8a73a860-7721-48f8-a713-acb2d300fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691255566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.691255566
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1884616279
Short name T961
Test name
Test status
Simulation time 960059219 ps
CPU time 7.66 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 240324 kb
Host smart-a85bde81-6bcc-44a8-84c1-a2f0e614bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884616279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1884616279
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1284849064
Short name T534
Test name
Test status
Simulation time 3576003522 ps
CPU time 10.23 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:24 PM PDT 24
Peak memory 233056 kb
Host smart-4234e832-eb52-4624-b691-b19b2cded571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284849064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1284849064
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4209220671
Short name T908
Test name
Test status
Simulation time 211958436 ps
CPU time 3.79 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:12:25 PM PDT 24
Peak memory 220964 kb
Host smart-6ec80876-cccf-4bea-b97f-2713f0db0d0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209220671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4209220671
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.704327531
Short name T160
Test name
Test status
Simulation time 14673739689 ps
CPU time 158.17 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:14:59 PM PDT 24
Peak memory 250640 kb
Host smart-44dd4b83-dfde-4281-b738-f63e1fcfeaf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704327531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.704327531
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3355144143
Short name T379
Test name
Test status
Simulation time 987491541 ps
CPU time 5.8 seconds
Started Jul 29 05:12:12 PM PDT 24
Finished Jul 29 05:12:18 PM PDT 24
Peak memory 216692 kb
Host smart-5cf20953-58d7-48ed-8102-5a05e478d4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355144143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3355144143
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2217664655
Short name T416
Test name
Test status
Simulation time 31745282981 ps
CPU time 21.81 seconds
Started Jul 29 05:12:13 PM PDT 24
Finished Jul 29 05:12:35 PM PDT 24
Peak memory 216740 kb
Host smart-00186be3-96e0-4bef-8db3-654c194b794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217664655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2217664655
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1183054522
Short name T764
Test name
Test status
Simulation time 199473714 ps
CPU time 1.13 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 208164 kb
Host smart-8ef7f46f-f03a-4432-b7b9-ba85f2042791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183054522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1183054522
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1982972171
Short name T496
Test name
Test status
Simulation time 54147449 ps
CPU time 0.88 seconds
Started Jul 29 05:12:14 PM PDT 24
Finished Jul 29 05:12:15 PM PDT 24
Peak memory 206296 kb
Host smart-78029837-15d0-49be-bf53-cfcc0f0c7dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982972171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1982972171
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3590140440
Short name T519
Test name
Test status
Simulation time 1626046928 ps
CPU time 6.85 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:26 PM PDT 24
Peak memory 233020 kb
Host smart-f5c5bca2-35d5-466e-aad4-2130dd206634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590140440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3590140440
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1747373326
Short name T325
Test name
Test status
Simulation time 59626479 ps
CPU time 0.69 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:25 PM PDT 24
Peak memory 205776 kb
Host smart-b9328c71-c33d-4209-8212-57e155f7f733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747373326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1747373326
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2771252693
Short name T670
Test name
Test status
Simulation time 124523512 ps
CPU time 2.32 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:12:23 PM PDT 24
Peak memory 233080 kb
Host smart-1c5a744b-e314-41fd-8d66-6197f48fab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771252693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2771252693
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3471583566
Short name T592
Test name
Test status
Simulation time 46395450 ps
CPU time 0.77 seconds
Started Jul 29 05:12:20 PM PDT 24
Finished Jul 29 05:12:21 PM PDT 24
Peak memory 206912 kb
Host smart-20a191e9-c217-46b4-b867-8a0c952fbcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471583566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3471583566
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2822598307
Short name T122
Test name
Test status
Simulation time 131970505241 ps
CPU time 312.1 seconds
Started Jul 29 05:12:22 PM PDT 24
Finished Jul 29 05:17:34 PM PDT 24
Peak memory 254760 kb
Host smart-4e30bf2d-b79b-40c7-911a-df9feb67eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822598307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2822598307
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2541604688
Short name T233
Test name
Test status
Simulation time 7778093739 ps
CPU time 46.26 seconds
Started Jul 29 05:12:26 PM PDT 24
Finished Jul 29 05:13:13 PM PDT 24
Peak memory 249720 kb
Host smart-b7380f9e-ff8c-4275-903a-8487df6d68ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541604688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2541604688
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3368444196
Short name T854
Test name
Test status
Simulation time 1241012654 ps
CPU time 21.9 seconds
Started Jul 29 05:12:18 PM PDT 24
Finished Jul 29 05:12:40 PM PDT 24
Peak memory 240204 kb
Host smart-63d439ed-6138-4690-af7c-f6b7eb310b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368444196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3368444196
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2283113908
Short name T214
Test name
Test status
Simulation time 7546042094 ps
CPU time 82.71 seconds
Started Jul 29 05:12:20 PM PDT 24
Finished Jul 29 05:13:43 PM PDT 24
Peak memory 257532 kb
Host smart-3e3ab160-60a4-4cd8-ab16-2d26d9fe6224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283113908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2283113908
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3393729882
Short name T89
Test name
Test status
Simulation time 700991085 ps
CPU time 3.66 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:23 PM PDT 24
Peak memory 233028 kb
Host smart-31e0e444-6916-4652-b7b3-873916dc8b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393729882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3393729882
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3307083489
Short name T447
Test name
Test status
Simulation time 732848226 ps
CPU time 8.53 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 233088 kb
Host smart-740ff6a7-5b57-4305-95b3-52cfd5618e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307083489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3307083489
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.383938990
Short name T734
Test name
Test status
Simulation time 3497313536 ps
CPU time 11.43 seconds
Started Jul 29 05:12:20 PM PDT 24
Finished Jul 29 05:12:31 PM PDT 24
Peak memory 233024 kb
Host smart-327123ac-ab8c-495b-a575-17b57c46d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383938990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.383938990
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.383867936
Short name T398
Test name
Test status
Simulation time 3706177734 ps
CPU time 3.65 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:23 PM PDT 24
Peak memory 224880 kb
Host smart-3a0895bd-ded6-4845-8b74-1c1da6a78f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383867936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.383867936
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3382596733
Short name T713
Test name
Test status
Simulation time 2546845597 ps
CPU time 7.95 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:12:29 PM PDT 24
Peak memory 223136 kb
Host smart-1f8d04dc-adf9-4c12-970b-3468bf56d28d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3382596733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3382596733
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2588713385
Short name T855
Test name
Test status
Simulation time 533108672792 ps
CPU time 664.2 seconds
Started Jul 29 05:12:28 PM PDT 24
Finished Jul 29 05:23:32 PM PDT 24
Peak memory 273804 kb
Host smart-7bb87ffe-9760-4262-8333-45e6346031f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588713385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2588713385
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3127714218
Short name T305
Test name
Test status
Simulation time 7266109551 ps
CPU time 24.15 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:12:45 PM PDT 24
Peak memory 216664 kb
Host smart-ab7e3cfb-5857-497b-bed7-2ab5e238598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127714218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3127714218
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2163460292
Short name T601
Test name
Test status
Simulation time 2485168052 ps
CPU time 9.23 seconds
Started Jul 29 05:12:18 PM PDT 24
Finished Jul 29 05:12:28 PM PDT 24
Peak memory 216688 kb
Host smart-7a11233a-25c7-403d-b154-5c92360a6b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163460292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2163460292
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2200603635
Short name T556
Test name
Test status
Simulation time 494509749 ps
CPU time 0.99 seconds
Started Jul 29 05:12:21 PM PDT 24
Finished Jul 29 05:12:22 PM PDT 24
Peak memory 208196 kb
Host smart-6b48f3a4-3723-4703-89d9-410a7109ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200603635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2200603635
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4177971863
Short name T685
Test name
Test status
Simulation time 83106795 ps
CPU time 0.86 seconds
Started Jul 29 05:12:18 PM PDT 24
Finished Jul 29 05:12:19 PM PDT 24
Peak memory 206312 kb
Host smart-85cfd142-bb44-4944-a21b-d618d29be822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177971863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4177971863
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3940878559
Short name T736
Test name
Test status
Simulation time 37387021980 ps
CPU time 21.75 seconds
Started Jul 29 05:12:19 PM PDT 24
Finished Jul 29 05:12:41 PM PDT 24
Peak memory 233164 kb
Host smart-1001425a-a50d-443d-ad28-6aadd6cf1e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940878559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3940878559
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.961718343
Short name T318
Test name
Test status
Simulation time 14158755 ps
CPU time 0.72 seconds
Started Jul 29 05:09:30 PM PDT 24
Finished Jul 29 05:09:31 PM PDT 24
Peak memory 205752 kb
Host smart-53add0ff-8025-4697-84ec-eb6e6689cb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961718343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.961718343
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2644993932
Short name T309
Test name
Test status
Simulation time 300072882 ps
CPU time 5.08 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:09:38 PM PDT 24
Peak memory 233120 kb
Host smart-ab33b3cc-0514-4300-9800-f2921e7c8d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644993932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2644993932
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3340815875
Short name T618
Test name
Test status
Simulation time 17464910 ps
CPU time 0.81 seconds
Started Jul 29 05:09:31 PM PDT 24
Finished Jul 29 05:09:32 PM PDT 24
Peak memory 205732 kb
Host smart-9392c7ff-86f4-4282-b36d-e1a991fde95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340815875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3340815875
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2120445339
Short name T842
Test name
Test status
Simulation time 17806123382 ps
CPU time 29.88 seconds
Started Jul 29 05:09:31 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 241376 kb
Host smart-07b90e5c-dfdc-48a1-beab-6eeacef34c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120445339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2120445339
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1108730832
Short name T190
Test name
Test status
Simulation time 75305384916 ps
CPU time 96.36 seconds
Started Jul 29 05:09:45 PM PDT 24
Finished Jul 29 05:11:22 PM PDT 24
Peak memory 250136 kb
Host smart-ea0c79e2-9abc-4988-8a67-0e1c93f14691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108730832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1108730832
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2745932371
Short name T506
Test name
Test status
Simulation time 1188270842 ps
CPU time 8.54 seconds
Started Jul 29 05:09:27 PM PDT 24
Finished Jul 29 05:09:35 PM PDT 24
Peak memory 224900 kb
Host smart-5a328d02-8d9e-4553-a192-276c1080057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745932371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2745932371
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1953936091
Short name T263
Test name
Test status
Simulation time 2609277046 ps
CPU time 12.15 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:09:31 PM PDT 24
Peak memory 233060 kb
Host smart-9adf34c4-2c2a-4e0b-8aaa-ab25dd85c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953936091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1953936091
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.845729853
Short name T521
Test name
Test status
Simulation time 10945569106 ps
CPU time 83.85 seconds
Started Jul 29 05:09:15 PM PDT 24
Finished Jul 29 05:10:39 PM PDT 24
Peak memory 251576 kb
Host smart-3e394590-725d-4813-8702-410c578ab880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845729853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.845729853
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.645830368
Short name T282
Test name
Test status
Simulation time 5170716522 ps
CPU time 18.04 seconds
Started Jul 29 05:09:20 PM PDT 24
Finished Jul 29 05:09:38 PM PDT 24
Peak memory 241320 kb
Host smart-209c99d5-9ad8-40fa-a9f3-2574ffa63ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645830368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
645830368
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2082294866
Short name T962
Test name
Test status
Simulation time 865070786 ps
CPU time 2.81 seconds
Started Jul 29 05:09:24 PM PDT 24
Finished Jul 29 05:09:27 PM PDT 24
Peak memory 224832 kb
Host smart-4413621e-a1fa-40f6-96ef-7759a6803ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082294866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2082294866
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3527076107
Short name T563
Test name
Test status
Simulation time 470717730 ps
CPU time 4.54 seconds
Started Jul 29 05:09:39 PM PDT 24
Finished Jul 29 05:09:44 PM PDT 24
Peak memory 219496 kb
Host smart-1a434bbc-02da-4a60-ab01-64a896fbfb05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3527076107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3527076107
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3209595062
Short name T74
Test name
Test status
Simulation time 102546027 ps
CPU time 1.18 seconds
Started Jul 29 05:09:23 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 236316 kb
Host smart-09d76309-6d74-4905-86b5-d55f8479c3a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209595062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3209595062
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.319741621
Short name T550
Test name
Test status
Simulation time 43895952 ps
CPU time 0.97 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:36 PM PDT 24
Peak memory 207236 kb
Host smart-1d07860f-680f-4dec-99b0-bb32f354b1ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319741621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.319741621
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1535635597
Short name T778
Test name
Test status
Simulation time 5810706111 ps
CPU time 12.98 seconds
Started Jul 29 05:09:31 PM PDT 24
Finished Jul 29 05:09:44 PM PDT 24
Peak memory 220632 kb
Host smart-e3b521f5-3288-4d5c-8f78-c612730dacef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535635597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1535635597
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.845659305
Short name T452
Test name
Test status
Simulation time 32784776286 ps
CPU time 11.36 seconds
Started Jul 29 05:09:19 PM PDT 24
Finished Jul 29 05:09:31 PM PDT 24
Peak memory 216676 kb
Host smart-4ecde1c0-92d9-42ab-973d-2c62f7ecf8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845659305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.845659305
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3487582154
Short name T485
Test name
Test status
Simulation time 234059536 ps
CPU time 2.12 seconds
Started Jul 29 05:09:17 PM PDT 24
Finished Jul 29 05:09:19 PM PDT 24
Peak memory 216560 kb
Host smart-70b75fb5-955c-437b-bd06-5afee3daf8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487582154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3487582154
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1771515398
Short name T343
Test name
Test status
Simulation time 117325938 ps
CPU time 0.78 seconds
Started Jul 29 05:09:20 PM PDT 24
Finished Jul 29 05:09:21 PM PDT 24
Peak memory 206268 kb
Host smart-08c3f856-398b-4fd0-bad4-4d1439775523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771515398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1771515398
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4094432554
Short name T692
Test name
Test status
Simulation time 170856952 ps
CPU time 2.81 seconds
Started Jul 29 05:09:23 PM PDT 24
Finished Jul 29 05:09:26 PM PDT 24
Peak memory 233032 kb
Host smart-2f8045f0-e9a3-4594-913c-4f6e3dbf8d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094432554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4094432554
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2831155987
Short name T66
Test name
Test status
Simulation time 15954905 ps
CPU time 0.72 seconds
Started Jul 29 05:12:26 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 205764 kb
Host smart-d83010cd-3e75-4684-9f93-ba5c377b83c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831155987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2831155987
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3883191756
Short name T241
Test name
Test status
Simulation time 31645850 ps
CPU time 2.18 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 224796 kb
Host smart-12a4cfb8-c792-453d-ad37-68552bfedfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883191756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3883191756
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2453436650
Short name T565
Test name
Test status
Simulation time 24147605 ps
CPU time 0.75 seconds
Started Jul 29 05:12:23 PM PDT 24
Finished Jul 29 05:12:24 PM PDT 24
Peak memory 205816 kb
Host smart-ef0a7e6a-22af-4dfd-a876-bac2bc7892fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453436650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2453436650
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1400111607
Short name T637
Test name
Test status
Simulation time 16293446497 ps
CPU time 129.22 seconds
Started Jul 29 05:12:27 PM PDT 24
Finished Jul 29 05:14:36 PM PDT 24
Peak memory 252320 kb
Host smart-aa7e1ec3-0f1a-4044-899f-3f74bf29edcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400111607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1400111607
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2853523768
Short name T188
Test name
Test status
Simulation time 35507013249 ps
CPU time 182.21 seconds
Started Jul 29 05:12:25 PM PDT 24
Finished Jul 29 05:15:28 PM PDT 24
Peak memory 241392 kb
Host smart-ee0c1def-cac3-425b-a931-f5e59760313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853523768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2853523768
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.378138642
Short name T665
Test name
Test status
Simulation time 245495033157 ps
CPU time 174.48 seconds
Started Jul 29 05:12:27 PM PDT 24
Finished Jul 29 05:15:21 PM PDT 24
Peak memory 249508 kb
Host smart-3d750adf-59ab-49ae-ac86-9a021e9614b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378138642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.378138642
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2423708840
Short name T153
Test name
Test status
Simulation time 433134703 ps
CPU time 10.53 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:35 PM PDT 24
Peak memory 224736 kb
Host smart-0cc6a95d-03ad-448a-b58e-e3b178dca504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423708840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2423708840
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3938369748
Short name T950
Test name
Test status
Simulation time 79812106099 ps
CPU time 150.93 seconds
Started Jul 29 05:12:26 PM PDT 24
Finished Jul 29 05:14:57 PM PDT 24
Peak memory 249604 kb
Host smart-20397398-37be-4322-a4de-51ad65efaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938369748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3938369748
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3559555660
Short name T212
Test name
Test status
Simulation time 3473309358 ps
CPU time 9.37 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:34 PM PDT 24
Peak memory 224908 kb
Host smart-f1b58b1a-dfb3-441f-9a35-d6dffaef5516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559555660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3559555660
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2176150744
Short name T557
Test name
Test status
Simulation time 5922983591 ps
CPU time 55.93 seconds
Started Jul 29 05:12:25 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 257252 kb
Host smart-a28772ea-395f-44d1-a63b-492682e5fc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176150744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2176150744
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4292579688
Short name T98
Test name
Test status
Simulation time 565426791 ps
CPU time 8.96 seconds
Started Jul 29 05:12:23 PM PDT 24
Finished Jul 29 05:12:33 PM PDT 24
Peak memory 241248 kb
Host smart-3ac1abf3-95d2-48e9-92c3-02a1a619d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292579688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4292579688
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3854378219
Short name T667
Test name
Test status
Simulation time 59868641 ps
CPU time 2.78 seconds
Started Jul 29 05:12:25 PM PDT 24
Finished Jul 29 05:12:28 PM PDT 24
Peak memory 233008 kb
Host smart-ae8ef921-968d-4651-8679-b4f915d95613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854378219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3854378219
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3279917501
Short name T599
Test name
Test status
Simulation time 185755638 ps
CPU time 4.93 seconds
Started Jul 29 05:12:28 PM PDT 24
Finished Jul 29 05:12:33 PM PDT 24
Peak memory 223460 kb
Host smart-f7d3d159-14f4-4558-93b0-148aed59c74e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3279917501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3279917501
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4126934775
Short name T359
Test name
Test status
Simulation time 821042067 ps
CPU time 8.59 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:33 PM PDT 24
Peak memory 216612 kb
Host smart-006cd848-3a3c-48f2-8f04-eb0c98a2286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126934775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4126934775
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.103122163
Short name T331
Test name
Test status
Simulation time 511873628 ps
CPU time 3.42 seconds
Started Jul 29 05:12:26 PM PDT 24
Finished Jul 29 05:12:30 PM PDT 24
Peak memory 216444 kb
Host smart-06367a14-dd14-4432-9580-00d920fe0676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103122163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.103122163
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1621346601
Short name T487
Test name
Test status
Simulation time 235684531 ps
CPU time 1.56 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:26 PM PDT 24
Peak memory 216588 kb
Host smart-6c99cfe0-dded-4976-bff1-54a8c22a1463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621346601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1621346601
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1479009556
Short name T928
Test name
Test status
Simulation time 57343980 ps
CPU time 0.83 seconds
Started Jul 29 05:12:30 PM PDT 24
Finished Jul 29 05:12:31 PM PDT 24
Peak memory 207272 kb
Host smart-4fa0dd97-d080-4df1-b018-ee68c2f75914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479009556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1479009556
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.758172457
Short name T937
Test name
Test status
Simulation time 11965813144 ps
CPU time 7.7 seconds
Started Jul 29 05:12:24 PM PDT 24
Finished Jul 29 05:12:32 PM PDT 24
Peak memory 224832 kb
Host smart-0eec4ea2-3b94-4d8d-af97-35d0d1608727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758172457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.758172457
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2387897617
Short name T393
Test name
Test status
Simulation time 10926385 ps
CPU time 0.71 seconds
Started Jul 29 05:12:40 PM PDT 24
Finished Jul 29 05:12:41 PM PDT 24
Peak memory 205100 kb
Host smart-a43681c4-f98b-4f3d-9e69-f218347a130a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387897617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2387897617
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3897051798
Short name T244
Test name
Test status
Simulation time 132299416 ps
CPU time 2.92 seconds
Started Jul 29 05:12:32 PM PDT 24
Finished Jul 29 05:12:35 PM PDT 24
Peak memory 233060 kb
Host smart-a409d365-318d-42e6-8121-b07e3f8ae973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897051798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3897051798
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3921127995
Short name T569
Test name
Test status
Simulation time 51313486 ps
CPU time 0.76 seconds
Started Jul 29 05:12:26 PM PDT 24
Finished Jul 29 05:12:27 PM PDT 24
Peak memory 207240 kb
Host smart-1fff16b4-05b1-4d3f-b99d-ae734b8d16ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921127995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3921127995
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2391239030
Short name T197
Test name
Test status
Simulation time 3043626520 ps
CPU time 34.08 seconds
Started Jul 29 05:12:43 PM PDT 24
Finished Jul 29 05:13:18 PM PDT 24
Peak memory 250408 kb
Host smart-32857e50-e865-4668-a038-18dcdee843d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391239030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2391239030
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4053740938
Short name T957
Test name
Test status
Simulation time 22139152829 ps
CPU time 229.24 seconds
Started Jul 29 05:12:41 PM PDT 24
Finished Jul 29 05:16:31 PM PDT 24
Peak memory 249564 kb
Host smart-ad6ab838-b863-482b-b1e4-c545bf349648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053740938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4053740938
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1462002009
Short name T515
Test name
Test status
Simulation time 17472192127 ps
CPU time 200.86 seconds
Started Jul 29 05:12:40 PM PDT 24
Finished Jul 29 05:16:01 PM PDT 24
Peak memory 256160 kb
Host smart-834329ae-f870-4260-a0a1-4fde36c0dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462002009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1462002009
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.274885262
Short name T748
Test name
Test status
Simulation time 177163832 ps
CPU time 2.73 seconds
Started Jul 29 05:12:33 PM PDT 24
Finished Jul 29 05:12:36 PM PDT 24
Peak memory 233012 kb
Host smart-93b20be0-632b-4fea-8142-f2790451f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274885262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.274885262
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3057737096
Short name T805
Test name
Test status
Simulation time 165334777027 ps
CPU time 123.05 seconds
Started Jul 29 05:12:36 PM PDT 24
Finished Jul 29 05:14:40 PM PDT 24
Peak memory 265084 kb
Host smart-9414c322-8263-4a45-9a3f-6b56d360ebec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057737096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3057737096
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4123673905
Short name T533
Test name
Test status
Simulation time 18879022705 ps
CPU time 19.94 seconds
Started Jul 29 05:12:32 PM PDT 24
Finished Jul 29 05:12:52 PM PDT 24
Peak memory 233200 kb
Host smart-27bd2548-42f2-4b79-9d7a-752eb6e5653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123673905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4123673905
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.228575378
Short name T985
Test name
Test status
Simulation time 2464342460 ps
CPU time 8.64 seconds
Started Jul 29 05:12:34 PM PDT 24
Finished Jul 29 05:12:43 PM PDT 24
Peak memory 233048 kb
Host smart-abfb563e-32e4-4638-876c-e57429b38f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228575378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.228575378
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2905771513
Short name T254
Test name
Test status
Simulation time 1148387174 ps
CPU time 3.21 seconds
Started Jul 29 05:12:33 PM PDT 24
Finished Jul 29 05:12:36 PM PDT 24
Peak memory 233104 kb
Host smart-0e7d42f5-0173-4146-a6da-d22c25998501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905771513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2905771513
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1607106010
Short name T953
Test name
Test status
Simulation time 870910706 ps
CPU time 8.09 seconds
Started Jul 29 05:12:31 PM PDT 24
Finished Jul 29 05:12:39 PM PDT 24
Peak memory 224812 kb
Host smart-c8157c74-6a3b-468f-816a-3451c02f7628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607106010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1607106010
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2477979961
Short name T629
Test name
Test status
Simulation time 547160076 ps
CPU time 5.71 seconds
Started Jul 29 05:12:39 PM PDT 24
Finished Jul 29 05:12:45 PM PDT 24
Peak memory 222888 kb
Host smart-7cbae131-fcea-4311-9c4d-9edf314013db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477979961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2477979961
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3592611448
Short name T215
Test name
Test status
Simulation time 66530698423 ps
CPU time 252.04 seconds
Started Jul 29 05:12:37 PM PDT 24
Finished Jul 29 05:16:49 PM PDT 24
Peak memory 267064 kb
Host smart-4aa5ad34-0922-419f-ab46-698d067f2fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592611448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3592611448
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1770526436
Short name T831
Test name
Test status
Simulation time 71722523589 ps
CPU time 25.08 seconds
Started Jul 29 05:12:32 PM PDT 24
Finished Jul 29 05:12:57 PM PDT 24
Peak memory 216872 kb
Host smart-06418ed5-fa30-4b77-9acd-13bdc2d56ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770526436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1770526436
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1032873735
Short name T793
Test name
Test status
Simulation time 4370359348 ps
CPU time 17.52 seconds
Started Jul 29 05:12:35 PM PDT 24
Finished Jul 29 05:12:53 PM PDT 24
Peak memory 216700 kb
Host smart-159ce249-8f1a-408c-b301-877352e3ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032873735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1032873735
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.173470000
Short name T555
Test name
Test status
Simulation time 200098771 ps
CPU time 1.47 seconds
Started Jul 29 05:12:33 PM PDT 24
Finished Jul 29 05:12:35 PM PDT 24
Peak memory 216560 kb
Host smart-06b7c1d9-388b-4f7c-99bb-706f97f258f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173470000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.173470000
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2723968184
Short name T832
Test name
Test status
Simulation time 107813686 ps
CPU time 0.79 seconds
Started Jul 29 05:12:35 PM PDT 24
Finished Jul 29 05:12:36 PM PDT 24
Peak memory 206296 kb
Host smart-0ed3ae11-2df8-495c-9bdf-8dd954752600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723968184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2723968184
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1966414413
Short name T829
Test name
Test status
Simulation time 2010009267 ps
CPU time 5.27 seconds
Started Jul 29 05:12:33 PM PDT 24
Finished Jul 29 05:12:39 PM PDT 24
Peak memory 224824 kb
Host smart-a2148051-3fd0-44ce-b16b-4583f0e72437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966414413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1966414413
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1071390945
Short name T342
Test name
Test status
Simulation time 23328348 ps
CPU time 0.73 seconds
Started Jul 29 05:12:39 PM PDT 24
Finished Jul 29 05:12:40 PM PDT 24
Peak memory 206044 kb
Host smart-5daaf399-4bc6-4dfe-943d-52fd98f3e2e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071390945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1071390945
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.251427322
Short name T165
Test name
Test status
Simulation time 8536943532 ps
CPU time 20.4 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:12:58 PM PDT 24
Peak memory 233160 kb
Host smart-f81fde4a-5a90-4dc6-bfdb-1ebe7280e41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251427322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.251427322
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3025567502
Short name T724
Test name
Test status
Simulation time 54610414 ps
CPU time 0.75 seconds
Started Jul 29 05:12:39 PM PDT 24
Finished Jul 29 05:12:40 PM PDT 24
Peak memory 205788 kb
Host smart-e89bac6c-cc8b-40cf-ace2-e9396169e758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025567502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3025567502
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.800542463
Short name T914
Test name
Test status
Simulation time 120379080637 ps
CPU time 206.72 seconds
Started Jul 29 05:12:36 PM PDT 24
Finished Jul 29 05:16:03 PM PDT 24
Peak memory 249540 kb
Host smart-fe5d3e4c-2226-466a-8ec8-0dcdf75a2e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800542463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.800542463
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.993818362
Short name T716
Test name
Test status
Simulation time 2318268507 ps
CPU time 26.97 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:13:05 PM PDT 24
Peak memory 217832 kb
Host smart-a6f10985-7976-40fc-887a-85723b19fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993818362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.993818362
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2504985519
Short name T802
Test name
Test status
Simulation time 1846031705 ps
CPU time 31.23 seconds
Started Jul 29 05:12:37 PM PDT 24
Finished Jul 29 05:13:09 PM PDT 24
Peak memory 240736 kb
Host smart-fa671142-9c57-4ea0-9e1f-d7e946105170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504985519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2504985519
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.673720835
Short name T901
Test name
Test status
Simulation time 633923576 ps
CPU time 7.36 seconds
Started Jul 29 05:12:37 PM PDT 24
Finished Jul 29 05:12:45 PM PDT 24
Peak memory 224904 kb
Host smart-47f3281b-f7ea-4766-ab13-e0995e7de09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673720835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.673720835
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3255723335
Short name T834
Test name
Test status
Simulation time 1081408345 ps
CPU time 5.22 seconds
Started Jul 29 05:12:36 PM PDT 24
Finished Jul 29 05:12:41 PM PDT 24
Peak memory 233092 kb
Host smart-dcdda084-4e8b-44bf-9cc5-7b6628a0af9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255723335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3255723335
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.273118924
Short name T657
Test name
Test status
Simulation time 1594904551 ps
CPU time 13.91 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:12:52 PM PDT 24
Peak memory 224940 kb
Host smart-e7a18c19-0c5e-417e-a816-10560105de4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273118924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.273118924
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2814828544
Short name T252
Test name
Test status
Simulation time 1648957889 ps
CPU time 4.29 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:12:42 PM PDT 24
Peak memory 233012 kb
Host smart-33e25364-5019-4d01-b54f-d46fb0a02714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814828544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2814828544
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1819124031
Short name T207
Test name
Test status
Simulation time 5598892140 ps
CPU time 6.92 seconds
Started Jul 29 05:12:39 PM PDT 24
Finished Jul 29 05:12:46 PM PDT 24
Peak memory 233208 kb
Host smart-5d44f208-6b1a-497a-aa87-1e46e8cc42a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819124031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1819124031
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2640756370
Short name T733
Test name
Test status
Simulation time 156512397 ps
CPU time 4.35 seconds
Started Jul 29 05:12:39 PM PDT 24
Finished Jul 29 05:12:43 PM PDT 24
Peak memory 223460 kb
Host smart-c2072e86-aa50-4e56-bbff-8c69a102a1df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2640756370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2640756370
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3845220233
Short name T708
Test name
Test status
Simulation time 5367679552 ps
CPU time 15.42 seconds
Started Jul 29 05:12:41 PM PDT 24
Finished Jul 29 05:12:57 PM PDT 24
Peak memory 216688 kb
Host smart-79e63a57-7c5d-4565-86a9-7e4609760f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845220233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3845220233
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3736098867
Short name T948
Test name
Test status
Simulation time 8559653954 ps
CPU time 6.45 seconds
Started Jul 29 05:12:39 PM PDT 24
Finished Jul 29 05:12:45 PM PDT 24
Peak memory 216620 kb
Host smart-2243bbf6-58ef-49fb-8e2b-c75382d0af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736098867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3736098867
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1308108118
Short name T482
Test name
Test status
Simulation time 254181065 ps
CPU time 1.12 seconds
Started Jul 29 05:12:35 PM PDT 24
Finished Jul 29 05:12:37 PM PDT 24
Peak memory 216596 kb
Host smart-51377104-eb58-473f-858a-3a2bae856311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308108118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1308108118
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3050975939
Short name T313
Test name
Test status
Simulation time 38612363 ps
CPU time 0.75 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:12:39 PM PDT 24
Peak memory 206232 kb
Host smart-80a7e262-49cd-45fb-a365-5c85658a26a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050975939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3050975939
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3135397974
Short name T443
Test name
Test status
Simulation time 59783738 ps
CPU time 2.19 seconds
Started Jul 29 05:12:42 PM PDT 24
Finished Jul 29 05:12:44 PM PDT 24
Peak memory 224416 kb
Host smart-97fe9dbc-a199-403f-8dc9-6061fe140ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135397974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3135397974
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1815996309
Short name T55
Test name
Test status
Simulation time 169826732 ps
CPU time 0.77 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:12:47 PM PDT 24
Peak memory 205812 kb
Host smart-2d1da12d-3800-44dc-aef7-2c9373af666f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815996309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1815996309
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3373556647
Short name T91
Test name
Test status
Simulation time 4278030629 ps
CPU time 12.72 seconds
Started Jul 29 05:12:49 PM PDT 24
Finished Jul 29 05:13:02 PM PDT 24
Peak memory 233112 kb
Host smart-044d6aae-760a-407a-9686-1c1fd3400741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373556647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3373556647
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1740488148
Short name T491
Test name
Test status
Simulation time 16989802 ps
CPU time 0.8 seconds
Started Jul 29 05:12:37 PM PDT 24
Finished Jul 29 05:12:38 PM PDT 24
Peak memory 206940 kb
Host smart-8803983f-1c91-4fbf-8a56-536975a4d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740488148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1740488148
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4183501407
Short name T295
Test name
Test status
Simulation time 352141802057 ps
CPU time 390.08 seconds
Started Jul 29 05:12:47 PM PDT 24
Finished Jul 29 05:19:17 PM PDT 24
Peak memory 253624 kb
Host smart-e1e587c0-f6f2-4cd3-96bd-ad8fb4432a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183501407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4183501407
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.537681149
Short name T753
Test name
Test status
Simulation time 331716776551 ps
CPU time 200.8 seconds
Started Jul 29 05:12:47 PM PDT 24
Finished Jul 29 05:16:08 PM PDT 24
Peak memory 265048 kb
Host smart-8f0caf92-00e6-4e8b-9302-07d6ba67d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537681149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.537681149
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4048873378
Short name T329
Test name
Test status
Simulation time 4343113780 ps
CPU time 18.54 seconds
Started Jul 29 05:12:48 PM PDT 24
Finished Jul 29 05:13:07 PM PDT 24
Peak memory 233136 kb
Host smart-06932a54-4da8-4906-99cc-14b42a6e71a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048873378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4048873378
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1968723626
Short name T79
Test name
Test status
Simulation time 9111688321 ps
CPU time 42.39 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:13:28 PM PDT 24
Peak memory 249528 kb
Host smart-19e42d5a-ceab-45f3-912a-c928e8e53a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968723626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1968723626
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3769729162
Short name T587
Test name
Test status
Simulation time 15253747157 ps
CPU time 31.2 seconds
Started Jul 29 05:12:47 PM PDT 24
Finished Jul 29 05:13:19 PM PDT 24
Peak memory 233192 kb
Host smart-3d72f99b-59ad-4f13-b491-a49509103ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769729162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3769729162
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2696889932
Short name T381
Test name
Test status
Simulation time 2448033779 ps
CPU time 7.19 seconds
Started Jul 29 05:12:47 PM PDT 24
Finished Jul 29 05:12:55 PM PDT 24
Peak memory 225016 kb
Host smart-9730683c-b451-47e2-858a-2145e074a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696889932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2696889932
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2952592739
Short name T632
Test name
Test status
Simulation time 543288225 ps
CPU time 5.7 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:12:52 PM PDT 24
Peak memory 232996 kb
Host smart-cf91c90f-8d2d-4f9c-b04e-ffeacadced5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952592739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2952592739
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3316345791
Short name T840
Test name
Test status
Simulation time 437780175 ps
CPU time 3.68 seconds
Started Jul 29 05:12:48 PM PDT 24
Finished Jul 29 05:12:52 PM PDT 24
Peak memory 224704 kb
Host smart-20017bf7-24eb-436f-841a-ef9b5114a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316345791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3316345791
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.44415609
Short name T895
Test name
Test status
Simulation time 2436990382 ps
CPU time 5.14 seconds
Started Jul 29 05:12:49 PM PDT 24
Finished Jul 29 05:12:54 PM PDT 24
Peak memory 220816 kb
Host smart-0ca70a68-903b-4035-aca1-cbfadd649eb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=44415609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direc
t.44415609
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3558252777
Short name T538
Test name
Test status
Simulation time 71540331014 ps
CPU time 67 seconds
Started Jul 29 05:12:48 PM PDT 24
Finished Jul 29 05:13:55 PM PDT 24
Peak memory 241416 kb
Host smart-d01f189f-fdbe-4757-a3b0-078df607dc02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558252777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3558252777
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.551414322
Short name T628
Test name
Test status
Simulation time 2421261618 ps
CPU time 20.73 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:12:59 PM PDT 24
Peak memory 216612 kb
Host smart-31ab261e-8035-4404-8d4e-899c7e8a7a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551414322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.551414322
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4167582898
Short name T576
Test name
Test status
Simulation time 303609250 ps
CPU time 1.75 seconds
Started Jul 29 05:12:38 PM PDT 24
Finished Jul 29 05:12:40 PM PDT 24
Peak memory 216388 kb
Host smart-905966a4-5a85-4440-a48e-618335f08cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167582898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4167582898
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2464710135
Short name T617
Test name
Test status
Simulation time 13788607 ps
CPU time 0.84 seconds
Started Jul 29 05:12:47 PM PDT 24
Finished Jul 29 05:12:48 PM PDT 24
Peak memory 207064 kb
Host smart-d449a273-18c2-4469-a00b-60693ed99ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464710135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2464710135
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1643294496
Short name T823
Test name
Test status
Simulation time 42745859 ps
CPU time 0.71 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:12:47 PM PDT 24
Peak memory 206236 kb
Host smart-88db8f61-5adc-40f4-a08a-5e34394a406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643294496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1643294496
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1319361188
Short name T993
Test name
Test status
Simulation time 4318939163 ps
CPU time 15.94 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:13:02 PM PDT 24
Peak memory 224900 kb
Host smart-30741f57-a338-43fc-83cb-40632b304e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319361188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1319361188
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1644375835
Short name T532
Test name
Test status
Simulation time 39793125 ps
CPU time 0.73 seconds
Started Jul 29 05:12:52 PM PDT 24
Finished Jul 29 05:12:53 PM PDT 24
Peak memory 205752 kb
Host smart-7f603b1e-0f08-4f42-b10f-557e76b940ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644375835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1644375835
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.414080214
Short name T561
Test name
Test status
Simulation time 5804341697 ps
CPU time 7.22 seconds
Started Jul 29 05:12:54 PM PDT 24
Finished Jul 29 05:13:01 PM PDT 24
Peak memory 224924 kb
Host smart-2b8f861a-9de7-4839-9bdc-3c544bed86de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414080214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.414080214
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.157816261
Short name T684
Test name
Test status
Simulation time 21325913 ps
CPU time 0.78 seconds
Started Jul 29 05:12:48 PM PDT 24
Finished Jul 29 05:12:49 PM PDT 24
Peak memory 206868 kb
Host smart-f240f5cd-cca1-4de9-a195-930b4e97a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157816261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.157816261
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2484848020
Short name T833
Test name
Test status
Simulation time 21753962095 ps
CPU time 172.62 seconds
Started Jul 29 05:12:50 PM PDT 24
Finished Jul 29 05:15:42 PM PDT 24
Peak memory 254192 kb
Host smart-d6ff3831-93e2-4acc-970e-cdfbba0c5e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484848020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2484848020
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3026336807
Short name T709
Test name
Test status
Simulation time 49767205363 ps
CPU time 46.86 seconds
Started Jul 29 05:12:53 PM PDT 24
Finished Jul 29 05:13:40 PM PDT 24
Peak memory 249568 kb
Host smart-5cf9f37a-c1f2-4430-b3ec-6ec4ad6a79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026336807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3026336807
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3147406825
Short name T43
Test name
Test status
Simulation time 26735737662 ps
CPU time 233.73 seconds
Started Jul 29 05:12:52 PM PDT 24
Finished Jul 29 05:16:46 PM PDT 24
Peak memory 255324 kb
Host smart-f4b33921-86ea-4537-9077-7c6f9461067b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147406825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3147406825
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1455546926
Short name T298
Test name
Test status
Simulation time 5949688687 ps
CPU time 45.87 seconds
Started Jul 29 05:12:50 PM PDT 24
Finished Jul 29 05:13:36 PM PDT 24
Peak memory 233112 kb
Host smart-2156e640-e44a-44ba-afee-547db676026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455546926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1455546926
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3180430182
Short name T664
Test name
Test status
Simulation time 30096785829 ps
CPU time 135.63 seconds
Started Jul 29 05:12:51 PM PDT 24
Finished Jul 29 05:15:07 PM PDT 24
Peak memory 253396 kb
Host smart-3e155268-fb2e-4ad8-86ad-5bff7d319098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180430182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3180430182
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4087036576
Short name T90
Test name
Test status
Simulation time 2588107553 ps
CPU time 8.19 seconds
Started Jul 29 05:12:51 PM PDT 24
Finished Jul 29 05:13:00 PM PDT 24
Peak memory 224804 kb
Host smart-b1065771-013f-41b3-82a8-5ca9d5b25c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087036576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4087036576
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3754850482
Short name T518
Test name
Test status
Simulation time 16403941169 ps
CPU time 95.94 seconds
Started Jul 29 05:12:55 PM PDT 24
Finished Jul 29 05:14:31 PM PDT 24
Peak memory 241232 kb
Host smart-c31bc006-0976-4799-bc29-21933998f286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754850482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3754850482
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2455492672
Short name T484
Test name
Test status
Simulation time 21170262786 ps
CPU time 18.64 seconds
Started Jul 29 05:12:50 PM PDT 24
Finished Jul 29 05:13:08 PM PDT 24
Peak memory 241252 kb
Host smart-376cba03-b60d-473f-8837-0ea1dffecf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455492672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2455492672
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1540184422
Short name T136
Test name
Test status
Simulation time 915198936 ps
CPU time 7.5 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:12:54 PM PDT 24
Peak memory 224820 kb
Host smart-92871765-7d5d-4321-98f4-1d17a486af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540184422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1540184422
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2342000479
Short name T378
Test name
Test status
Simulation time 1858133793 ps
CPU time 6.73 seconds
Started Jul 29 05:12:50 PM PDT 24
Finished Jul 29 05:12:57 PM PDT 24
Peak memory 219380 kb
Host smart-d5af6d2c-5f77-473f-9d20-5eb6526abac9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342000479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2342000479
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.401704000
Short name T545
Test name
Test status
Simulation time 4782927117 ps
CPU time 51.84 seconds
Started Jul 29 05:12:51 PM PDT 24
Finished Jul 29 05:13:43 PM PDT 24
Peak memory 252680 kb
Host smart-ac6e16a5-6073-48e3-a65b-9e12918a4ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401704000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.401704000
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3584566976
Short name T648
Test name
Test status
Simulation time 7211289011 ps
CPU time 32.04 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:13:18 PM PDT 24
Peak memory 221792 kb
Host smart-a2f80fc2-dfb3-4155-805e-8090840f6126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584566976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3584566976
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.231204040
Short name T595
Test name
Test status
Simulation time 2400388120 ps
CPU time 2.81 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:12:49 PM PDT 24
Peak memory 216456 kb
Host smart-d9280783-ab86-443c-8ea0-af4162c7dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231204040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.231204040
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2314137960
Short name T564
Test name
Test status
Simulation time 26131072 ps
CPU time 1.37 seconds
Started Jul 29 05:12:48 PM PDT 24
Finished Jul 29 05:12:49 PM PDT 24
Peak memory 216664 kb
Host smart-9326cd48-6e97-4ada-ad7f-3a499d38ea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314137960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2314137960
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2916771887
Short name T320
Test name
Test status
Simulation time 70780300 ps
CPU time 0.77 seconds
Started Jul 29 05:12:46 PM PDT 24
Finished Jul 29 05:12:47 PM PDT 24
Peak memory 206220 kb
Host smart-1b4df95c-c58b-4262-b08d-db548802e1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916771887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2916771887
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.843918069
Short name T673
Test name
Test status
Simulation time 3004481903 ps
CPU time 7.31 seconds
Started Jul 29 05:12:54 PM PDT 24
Finished Jul 29 05:13:01 PM PDT 24
Peak memory 233116 kb
Host smart-05d6c87c-2e0f-4812-98e8-0bc895a5a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843918069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.843918069
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3752717994
Short name T520
Test name
Test status
Simulation time 29552259 ps
CPU time 0.72 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:12:58 PM PDT 24
Peak memory 205796 kb
Host smart-22ef0b02-83cc-4d22-9e1d-96b1c5f57d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752717994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3752717994
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3456779019
Short name T797
Test name
Test status
Simulation time 3142078055 ps
CPU time 10.11 seconds
Started Jul 29 05:13:00 PM PDT 24
Finished Jul 29 05:13:10 PM PDT 24
Peak memory 224824 kb
Host smart-d773d235-53b0-4da7-95d1-2c3a09c697a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456779019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3456779019
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1936504961
Short name T568
Test name
Test status
Simulation time 18861098 ps
CPU time 0.82 seconds
Started Jul 29 05:12:54 PM PDT 24
Finished Jul 29 05:12:55 PM PDT 24
Peak memory 206976 kb
Host smart-ee9cd8c9-73fc-4a32-81bf-68faf9d1b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936504961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1936504961
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2206756347
Short name T204
Test name
Test status
Simulation time 25188825518 ps
CPU time 192.9 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:16:10 PM PDT 24
Peak memory 265204 kb
Host smart-1a3263a5-ab76-4ece-96ba-5cd1bd23a723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206756347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2206756347
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3984906132
Short name T41
Test name
Test status
Simulation time 87529748174 ps
CPU time 427.66 seconds
Started Jul 29 05:13:03 PM PDT 24
Finished Jul 29 05:20:11 PM PDT 24
Peak memory 267104 kb
Host smart-a30312d8-daf7-4ba4-9f04-d8ff83d9d372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984906132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3984906132
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.338054895
Short name T551
Test name
Test status
Simulation time 738329633 ps
CPU time 10.56 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:09 PM PDT 24
Peak memory 224804 kb
Host smart-de7abee4-5a8d-4e7a-9eca-effc0e500e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338054895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.338054895
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1158078518
Short name T293
Test name
Test status
Simulation time 898572013 ps
CPU time 19.36 seconds
Started Jul 29 05:12:56 PM PDT 24
Finished Jul 29 05:13:15 PM PDT 24
Peak memory 254148 kb
Host smart-a8f8b03d-8526-447a-b129-5f046dea1314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158078518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1158078518
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1604716418
Short name T575
Test name
Test status
Simulation time 262936517 ps
CPU time 3.56 seconds
Started Jul 29 05:12:52 PM PDT 24
Finished Jul 29 05:12:56 PM PDT 24
Peak memory 224860 kb
Host smart-cc6b1d0d-13be-441f-9ad7-2364ada36b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604716418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1604716418
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.625192753
Short name T941
Test name
Test status
Simulation time 638074866 ps
CPU time 4.11 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:02 PM PDT 24
Peak memory 224836 kb
Host smart-13f69729-4f79-4f08-95a6-dce0051df3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625192753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.625192753
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.160808153
Short name T817
Test name
Test status
Simulation time 2237194821 ps
CPU time 3.31 seconds
Started Jul 29 05:12:50 PM PDT 24
Finished Jul 29 05:12:53 PM PDT 24
Peak memory 224880 kb
Host smart-4511a43b-c260-441f-8c6d-12e8874a7e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160808153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.160808153
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1321350537
Short name T404
Test name
Test status
Simulation time 32029181 ps
CPU time 2.62 seconds
Started Jul 29 05:12:50 PM PDT 24
Finished Jul 29 05:12:53 PM PDT 24
Peak memory 233312 kb
Host smart-3cc6d9be-05c4-49ad-8232-5e883ba72cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321350537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1321350537
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1708770068
Short name T455
Test name
Test status
Simulation time 1128555104 ps
CPU time 14.65 seconds
Started Jul 29 05:12:59 PM PDT 24
Finished Jul 29 05:13:14 PM PDT 24
Peak memory 219144 kb
Host smart-f05df551-fdf6-4e70-baf3-b54a464b7ec3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1708770068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1708770068
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2949286283
Short name T198
Test name
Test status
Simulation time 18564499226 ps
CPU time 137.46 seconds
Started Jul 29 05:13:03 PM PDT 24
Finished Jul 29 05:15:20 PM PDT 24
Peak memory 267968 kb
Host smart-b9bf7cd0-8b4d-4d49-ac90-d149ff9d377b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949286283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2949286283
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1466019854
Short name T782
Test name
Test status
Simulation time 3957400472 ps
CPU time 23.31 seconds
Started Jul 29 05:12:51 PM PDT 24
Finished Jul 29 05:13:14 PM PDT 24
Peak memory 216776 kb
Host smart-2bc23ec9-fd0e-4546-96fb-9eaf6c167ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466019854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1466019854
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1074302400
Short name T436
Test name
Test status
Simulation time 2213361762 ps
CPU time 4.7 seconds
Started Jul 29 05:12:53 PM PDT 24
Finished Jul 29 05:12:58 PM PDT 24
Peak memory 216540 kb
Host smart-1bdb3983-f770-4c4e-8233-256fab158d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074302400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1074302400
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1763068765
Short name T722
Test name
Test status
Simulation time 47476229 ps
CPU time 1.44 seconds
Started Jul 29 05:12:54 PM PDT 24
Finished Jul 29 05:12:55 PM PDT 24
Peak memory 217880 kb
Host smart-f348611e-69e4-434a-90f3-2f749af59b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763068765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1763068765
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2230752989
Short name T348
Test name
Test status
Simulation time 152310529 ps
CPU time 0.84 seconds
Started Jul 29 05:12:51 PM PDT 24
Finished Jul 29 05:12:51 PM PDT 24
Peak memory 206224 kb
Host smart-3f198390-9628-4bfb-91d9-510cb63187a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230752989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2230752989
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2780468271
Short name T969
Test name
Test status
Simulation time 6804964402 ps
CPU time 10.46 seconds
Started Jul 29 05:13:00 PM PDT 24
Finished Jul 29 05:13:11 PM PDT 24
Peak memory 235104 kb
Host smart-7b46f58d-c1b4-4634-8be2-5752225bd305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780468271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2780468271
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.377110564
Short name T760
Test name
Test status
Simulation time 14419816 ps
CPU time 0.7 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:12:57 PM PDT 24
Peak memory 205724 kb
Host smart-b0e41ec5-4b7d-4067-b78f-f97b17befcac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377110564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.377110564
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2784074189
Short name T965
Test name
Test status
Simulation time 84043357 ps
CPU time 2.55 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:13:00 PM PDT 24
Peak memory 224828 kb
Host smart-22cf7420-ee29-4baa-983a-10da5a56bb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784074189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2784074189
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2054220132
Short name T647
Test name
Test status
Simulation time 35852082 ps
CPU time 0.83 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:12:58 PM PDT 24
Peak memory 206924 kb
Host smart-6ccae262-524d-4678-b61a-575c5630e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054220132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2054220132
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3592345954
Short name T810
Test name
Test status
Simulation time 6403630661 ps
CPU time 46.23 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:13:44 PM PDT 24
Peak memory 235492 kb
Host smart-0c31363e-586b-463b-a113-afa442286994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592345954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3592345954
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4159519696
Short name T813
Test name
Test status
Simulation time 33358187807 ps
CPU time 102.16 seconds
Started Jul 29 05:13:01 PM PDT 24
Finished Jul 29 05:14:43 PM PDT 24
Peak memory 241468 kb
Host smart-07284378-641d-4270-8f6e-edd9f0bf94b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159519696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4159519696
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3277432720
Short name T461
Test name
Test status
Simulation time 1521609899 ps
CPU time 10.5 seconds
Started Jul 29 05:12:59 PM PDT 24
Finished Jul 29 05:13:10 PM PDT 24
Peak memory 224812 kb
Host smart-7c32ba9a-2cea-45c4-a8fa-0fc5361d108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277432720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3277432720
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4263642495
Short name T193
Test name
Test status
Simulation time 8871168059 ps
CPU time 27.05 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:25 PM PDT 24
Peak memory 233140 kb
Host smart-343b313c-3513-4376-a095-0dad5d23c1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263642495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4263642495
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2956676736
Short name T663
Test name
Test status
Simulation time 4279234322 ps
CPU time 31.86 seconds
Started Jul 29 05:12:57 PM PDT 24
Finished Jul 29 05:13:29 PM PDT 24
Peak memory 233356 kb
Host smart-dc895a3a-033f-455a-a866-6bda1f0019e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956676736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2956676736
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2651225672
Short name T415
Test name
Test status
Simulation time 4657666036 ps
CPU time 9.35 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:07 PM PDT 24
Peak memory 224852 kb
Host smart-ab94e58f-777d-4a8a-944b-10038cf536bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651225672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2651225672
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2141387831
Short name T460
Test name
Test status
Simulation time 435364996 ps
CPU time 4.62 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:03 PM PDT 24
Peak memory 224800 kb
Host smart-3cb9d793-384d-4195-bea6-f7a524a7e349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141387831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2141387831
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.291785325
Short name T653
Test name
Test status
Simulation time 208113902 ps
CPU time 5.29 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:03 PM PDT 24
Peak memory 223052 kb
Host smart-54184396-8f17-48eb-9ab3-937b7428379a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=291785325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.291785325
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4155820462
Short name T470
Test name
Test status
Simulation time 2435842117 ps
CPU time 30.26 seconds
Started Jul 29 05:13:02 PM PDT 24
Finished Jul 29 05:13:32 PM PDT 24
Peak memory 220332 kb
Host smart-fde1e23d-7df5-43e7-ba3f-21d84485ba74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155820462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4155820462
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3322970279
Short name T61
Test name
Test status
Simulation time 3856089420 ps
CPU time 24.63 seconds
Started Jul 29 05:12:58 PM PDT 24
Finished Jul 29 05:13:22 PM PDT 24
Peak memory 216716 kb
Host smart-493ac737-d793-4f32-8103-91433b815c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322970279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3322970279
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1089036540
Short name T377
Test name
Test status
Simulation time 180434343 ps
CPU time 1.51 seconds
Started Jul 29 05:12:59 PM PDT 24
Finished Jul 29 05:13:00 PM PDT 24
Peak memory 208132 kb
Host smart-11511897-0b71-4fdf-ac61-22a3c7de54c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089036540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1089036540
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1982539102
Short name T775
Test name
Test status
Simulation time 64600139 ps
CPU time 0.69 seconds
Started Jul 29 05:12:56 PM PDT 24
Finished Jul 29 05:12:57 PM PDT 24
Peak memory 205944 kb
Host smart-b71af00f-1942-4815-bf89-05c0ffc00c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982539102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1982539102
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.564937426
Short name T431
Test name
Test status
Simulation time 22018970 ps
CPU time 0.78 seconds
Started Jul 29 05:12:56 PM PDT 24
Finished Jul 29 05:12:57 PM PDT 24
Peak memory 206256 kb
Host smart-ff474ce5-eabe-4fd2-9e48-4a2f4777c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564937426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.564937426
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1058037153
Short name T620
Test name
Test status
Simulation time 197165458 ps
CPU time 2.27 seconds
Started Jul 29 05:13:03 PM PDT 24
Finished Jul 29 05:13:05 PM PDT 24
Peak memory 232724 kb
Host smart-3f240fb1-5dea-4a5e-85f2-3891b4510e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058037153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1058037153
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2589859289
Short name T65
Test name
Test status
Simulation time 39815399 ps
CPU time 0.74 seconds
Started Jul 29 05:13:05 PM PDT 24
Finished Jul 29 05:13:05 PM PDT 24
Peak memory 206044 kb
Host smart-e3bebb20-5abb-47a5-80bf-0e5ac19ce439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589859289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2589859289
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3124381544
Short name T527
Test name
Test status
Simulation time 437029357 ps
CPU time 3.55 seconds
Started Jul 29 05:13:08 PM PDT 24
Finished Jul 29 05:13:11 PM PDT 24
Peak memory 232988 kb
Host smart-346a8a82-959b-4f2c-b1a6-589e6d7dfe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124381544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3124381544
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.753795414
Short name T401
Test name
Test status
Simulation time 34123887 ps
CPU time 0.81 seconds
Started Jul 29 05:13:07 PM PDT 24
Finished Jul 29 05:13:07 PM PDT 24
Peak memory 206928 kb
Host smart-c6fa3b7d-7d0c-41d8-8cd9-ec0a9f375edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753795414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.753795414
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.941307425
Short name T548
Test name
Test status
Simulation time 59178206888 ps
CPU time 216.69 seconds
Started Jul 29 05:13:08 PM PDT 24
Finished Jul 29 05:16:45 PM PDT 24
Peak memory 250784 kb
Host smart-ede99d72-40bc-4f68-b0a7-eac56a3f0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941307425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.941307425
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.735551362
Short name T265
Test name
Test status
Simulation time 112832657902 ps
CPU time 254.19 seconds
Started Jul 29 05:13:04 PM PDT 24
Finished Jul 29 05:17:19 PM PDT 24
Peak memory 241320 kb
Host smart-13b52a3a-b4d9-4ca6-96f8-d062e22df6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735551362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.735551362
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1287391634
Short name T536
Test name
Test status
Simulation time 4019557488 ps
CPU time 112.72 seconds
Started Jul 29 05:13:03 PM PDT 24
Finished Jul 29 05:14:56 PM PDT 24
Peak memory 255100 kb
Host smart-389a7d0b-7900-4a9a-a132-3e61ed2858ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287391634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1287391634
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2699101057
Short name T582
Test name
Test status
Simulation time 1490008012 ps
CPU time 14.18 seconds
Started Jul 29 05:13:05 PM PDT 24
Finished Jul 29 05:13:20 PM PDT 24
Peak memory 243808 kb
Host smart-3e9ec62f-9dd5-4ab9-af5e-6542af8f6021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699101057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2699101057
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4224470101
Short name T795
Test name
Test status
Simulation time 79092531 ps
CPU time 2.09 seconds
Started Jul 29 05:13:04 PM PDT 24
Finished Jul 29 05:13:06 PM PDT 24
Peak memory 224824 kb
Host smart-c7149442-54b8-43db-9d8e-50c8096992d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224470101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4224470101
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1883262343
Short name T590
Test name
Test status
Simulation time 208643363 ps
CPU time 4.29 seconds
Started Jul 29 05:13:07 PM PDT 24
Finished Jul 29 05:13:11 PM PDT 24
Peak memory 224816 kb
Host smart-3831afd0-26d3-4cc8-a0c2-040739c56d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883262343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1883262343
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1717626461
Short name T783
Test name
Test status
Simulation time 16691012421 ps
CPU time 16.29 seconds
Started Jul 29 05:13:08 PM PDT 24
Finished Jul 29 05:13:24 PM PDT 24
Peak memory 233080 kb
Host smart-aa25d717-ed17-4f9e-8659-813602ca9847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717626461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1717626461
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.368966223
Short name T513
Test name
Test status
Simulation time 330319541 ps
CPU time 4.04 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:13 PM PDT 24
Peak memory 233088 kb
Host smart-9d4cbbe0-5210-4015-abfc-10aa5667c62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368966223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.368966223
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4085629151
Short name T383
Test name
Test status
Simulation time 148693356 ps
CPU time 3.75 seconds
Started Jul 29 05:13:07 PM PDT 24
Finished Jul 29 05:13:11 PM PDT 24
Peak memory 223524 kb
Host smart-542128e5-b2a3-4f05-8e95-8666483a6dfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4085629151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4085629151
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.555425257
Short name T867
Test name
Test status
Simulation time 34005425367 ps
CPU time 185.65 seconds
Started Jul 29 05:13:04 PM PDT 24
Finished Jul 29 05:16:10 PM PDT 24
Peak memory 274124 kb
Host smart-aff891c1-c43b-4876-a028-c290f0f8e9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555425257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.555425257
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2176188496
Short name T317
Test name
Test status
Simulation time 613409342 ps
CPU time 5.94 seconds
Started Jul 29 05:13:07 PM PDT 24
Finished Jul 29 05:13:13 PM PDT 24
Peak memory 216684 kb
Host smart-bd604ef5-e042-4ed8-a4a4-d5fbc6607db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176188496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2176188496
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3165195046
Short name T341
Test name
Test status
Simulation time 3112653635 ps
CPU time 10.63 seconds
Started Jul 29 05:13:07 PM PDT 24
Finished Jul 29 05:13:18 PM PDT 24
Peak memory 216632 kb
Host smart-33441a2d-73b6-4d98-8dc8-c68beac41c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165195046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3165195046
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.466911423
Short name T615
Test name
Test status
Simulation time 13047807 ps
CPU time 0.74 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:07 PM PDT 24
Peak memory 206304 kb
Host smart-8b043439-c14e-4241-aff5-c0cee6094527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466911423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.466911423
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3520069819
Short name T903
Test name
Test status
Simulation time 147072636 ps
CPU time 0.82 seconds
Started Jul 29 05:13:07 PM PDT 24
Finished Jul 29 05:13:08 PM PDT 24
Peak memory 206200 kb
Host smart-21114d8d-7ca0-46c4-97bc-427deaafc9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520069819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3520069819
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.136270583
Short name T933
Test name
Test status
Simulation time 66681951819 ps
CPU time 24.72 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:31 PM PDT 24
Peak memory 233028 kb
Host smart-4d8cf84e-ab4a-41a7-aec4-6d65e74e5337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136270583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.136270583
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3755305539
Short name T606
Test name
Test status
Simulation time 24799444 ps
CPU time 0.73 seconds
Started Jul 29 05:13:10 PM PDT 24
Finished Jul 29 05:13:11 PM PDT 24
Peak memory 205788 kb
Host smart-b50b0716-3886-4b21-a3ab-56f4945ff9fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755305539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3755305539
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1347985167
Short name T897
Test name
Test status
Simulation time 555457327 ps
CPU time 6.39 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:12 PM PDT 24
Peak memory 224796 kb
Host smart-c436a73c-e2a7-46ea-89e7-fc39daac94f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347985167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1347985167
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3998705030
Short name T714
Test name
Test status
Simulation time 106989105 ps
CPU time 0.78 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:10 PM PDT 24
Peak memory 206948 kb
Host smart-a91d5de7-16e0-4981-86be-4085b49ee78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998705030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3998705030
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1371143838
Short name T504
Test name
Test status
Simulation time 1898998842 ps
CPU time 8.54 seconds
Started Jul 29 05:13:15 PM PDT 24
Finished Jul 29 05:13:24 PM PDT 24
Peak memory 235464 kb
Host smart-6ff62f31-d0b0-4c77-8fe1-dd02b4db0866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371143838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1371143838
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3987873424
Short name T225
Test name
Test status
Simulation time 115207157634 ps
CPU time 218.33 seconds
Started Jul 29 05:13:10 PM PDT 24
Finished Jul 29 05:16:48 PM PDT 24
Peak memory 257620 kb
Host smart-ecade9f5-e851-4382-a8e4-f7e74ff49516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987873424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3987873424
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1084984958
Short name T987
Test name
Test status
Simulation time 5698878949 ps
CPU time 81.95 seconds
Started Jul 29 05:13:08 PM PDT 24
Finished Jul 29 05:14:30 PM PDT 24
Peak memory 251568 kb
Host smart-9b5c6a58-6df0-45b0-bb22-404e16e83285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084984958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1084984958
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.774274132
Short name T596
Test name
Test status
Simulation time 65645442 ps
CPU time 2.3 seconds
Started Jul 29 05:13:11 PM PDT 24
Finished Jul 29 05:13:13 PM PDT 24
Peak memory 224828 kb
Host smart-e2456ca8-14dd-4766-9031-7f43e16db619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774274132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.774274132
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1605897112
Short name T209
Test name
Test status
Simulation time 9661756898 ps
CPU time 87.8 seconds
Started Jul 29 05:13:12 PM PDT 24
Finished Jul 29 05:14:39 PM PDT 24
Peak memory 265764 kb
Host smart-f7d63ae0-3d1d-45be-825e-db89819b7e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605897112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1605897112
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2870018854
Short name T226
Test name
Test status
Simulation time 9555659928 ps
CPU time 18.66 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:25 PM PDT 24
Peak memory 224816 kb
Host smart-feda36d7-d4d8-4c4e-809e-97593e437ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870018854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2870018854
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1544447157
Short name T694
Test name
Test status
Simulation time 136991269 ps
CPU time 2.2 seconds
Started Jul 29 05:13:08 PM PDT 24
Finished Jul 29 05:13:11 PM PDT 24
Peak memory 223440 kb
Host smart-f3664be8-f9d3-4d72-9962-686beb33af9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544447157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1544447157
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2360788206
Short name T45
Test name
Test status
Simulation time 2992319507 ps
CPU time 6.47 seconds
Started Jul 29 05:13:08 PM PDT 24
Finished Jul 29 05:13:14 PM PDT 24
Peak memory 224828 kb
Host smart-7d46b40f-454b-4e25-9ff5-f7bb8d83ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360788206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2360788206
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2558772526
Short name T327
Test name
Test status
Simulation time 32056231 ps
CPU time 2.38 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:09 PM PDT 24
Peak memory 232784 kb
Host smart-7444c719-542f-4ad1-806f-1f2689a67e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558772526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2558772526
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1772687040
Short name T412
Test name
Test status
Simulation time 7252683905 ps
CPU time 24.88 seconds
Started Jul 29 05:13:10 PM PDT 24
Finished Jul 29 05:13:35 PM PDT 24
Peak memory 219460 kb
Host smart-529bec6a-0d6e-4e83-a52f-e86649c15b40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1772687040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1772687040
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3679662324
Short name T270
Test name
Test status
Simulation time 9158088332 ps
CPU time 171.78 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:16:01 PM PDT 24
Peak memory 265904 kb
Host smart-b37efe2e-e291-464b-a4f7-2f369045c6be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679662324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3679662324
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1443207448
Short name T306
Test name
Test status
Simulation time 15077205972 ps
CPU time 35.78 seconds
Started Jul 29 05:13:05 PM PDT 24
Finished Jul 29 05:13:41 PM PDT 24
Peak memory 216844 kb
Host smart-4f0980be-d731-4322-a1e8-aab4a38c3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443207448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1443207448
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1810228285
Short name T417
Test name
Test status
Simulation time 3312785031 ps
CPU time 6.88 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:12 PM PDT 24
Peak memory 216716 kb
Host smart-d30c15b8-cd20-4485-86b0-c16a8fb354aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810228285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1810228285
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3224609324
Short name T422
Test name
Test status
Simulation time 152985146 ps
CPU time 2.58 seconds
Started Jul 29 05:13:06 PM PDT 24
Finished Jul 29 05:13:08 PM PDT 24
Peak memory 216588 kb
Host smart-4b6cd6ea-0622-4771-a7f9-7c041f43ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224609324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3224609324
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.313687094
Short name T956
Test name
Test status
Simulation time 34893654 ps
CPU time 0.71 seconds
Started Jul 29 05:13:05 PM PDT 24
Finished Jul 29 05:13:06 PM PDT 24
Peak memory 205868 kb
Host smart-f7305181-595f-4ac0-b0ac-99c40ab573a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313687094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.313687094
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2504049530
Short name T166
Test name
Test status
Simulation time 20530872678 ps
CPU time 20.47 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:29 PM PDT 24
Peak memory 233164 kb
Host smart-18239566-0ef5-4867-bcb1-c1869b556fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504049530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2504049530
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.764392311
Short name T814
Test name
Test status
Simulation time 10971168 ps
CPU time 0.7 seconds
Started Jul 29 05:13:20 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 206164 kb
Host smart-61d03772-8f0b-43cb-8d35-7550d2f55824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764392311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.764392311
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1185924025
Short name T858
Test name
Test status
Simulation time 59344895 ps
CPU time 2.55 seconds
Started Jul 29 05:13:10 PM PDT 24
Finished Jul 29 05:13:12 PM PDT 24
Peak memory 233012 kb
Host smart-88214979-9f5f-449c-82df-5d22e14e6e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185924025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1185924025
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1198525997
Short name T454
Test name
Test status
Simulation time 15886873 ps
CPU time 0.76 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:10 PM PDT 24
Peak memory 207236 kb
Host smart-a68cba36-09a0-4815-bd41-a1f85d0b2548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198525997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1198525997
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4024186969
Short name T421
Test name
Test status
Simulation time 43178947 ps
CPU time 0.77 seconds
Started Jul 29 05:13:13 PM PDT 24
Finished Jul 29 05:13:14 PM PDT 24
Peak memory 216048 kb
Host smart-1d39d555-ebdc-4980-a9fd-1900da877e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024186969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4024186969
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2846485325
Short name T257
Test name
Test status
Simulation time 2107659152 ps
CPU time 33.52 seconds
Started Jul 29 05:13:12 PM PDT 24
Finished Jul 29 05:13:46 PM PDT 24
Peak memory 224716 kb
Host smart-7bb26269-4b1b-46d0-bf64-ea3a6ceb5a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846485325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2846485325
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.976060033
Short name T157
Test name
Test status
Simulation time 13005665991 ps
CPU time 45.3 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:55 PM PDT 24
Peak memory 239416 kb
Host smart-03941a44-f5da-4225-a1e6-1564270fc03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976060033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.976060033
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2552531035
Short name T544
Test name
Test status
Simulation time 12394626173 ps
CPU time 126.68 seconds
Started Jul 29 05:13:10 PM PDT 24
Finished Jul 29 05:15:17 PM PDT 24
Peak memory 257468 kb
Host smart-8a5180d9-5586-46f2-91ba-2a7aed03e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552531035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2552531035
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.932223383
Short name T522
Test name
Test status
Simulation time 128696034 ps
CPU time 3.18 seconds
Started Jul 29 05:13:11 PM PDT 24
Finished Jul 29 05:13:14 PM PDT 24
Peak memory 224788 kb
Host smart-ddb122e8-be19-41c6-abbd-22183b61930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932223383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.932223383
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2626215644
Short name T451
Test name
Test status
Simulation time 2185567713 ps
CPU time 15.4 seconds
Started Jul 29 05:13:11 PM PDT 24
Finished Jul 29 05:13:26 PM PDT 24
Peak memory 233144 kb
Host smart-c733bce0-66ea-4b43-9852-40966cda9579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626215644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2626215644
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2425610796
Short name T287
Test name
Test status
Simulation time 1026582697 ps
CPU time 7.75 seconds
Started Jul 29 05:13:13 PM PDT 24
Finished Jul 29 05:13:21 PM PDT 24
Peak memory 233084 kb
Host smart-6a48beff-f3c4-40e1-b627-66a95899c95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425610796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2425610796
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3183940951
Short name T944
Test name
Test status
Simulation time 247607502 ps
CPU time 3.43 seconds
Started Jul 29 05:13:12 PM PDT 24
Finished Jul 29 05:13:15 PM PDT 24
Peak memory 224720 kb
Host smart-c2f6da9e-bb08-4be7-a185-9d7e6d4cddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183940951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3183940951
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2686945046
Short name T720
Test name
Test status
Simulation time 20333118026 ps
CPU time 27.16 seconds
Started Jul 29 05:13:11 PM PDT 24
Finished Jul 29 05:13:38 PM PDT 24
Peak memory 220192 kb
Host smart-12e13943-d5d8-46e7-af09-2c0ac6b9b721
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686945046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2686945046
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3041269929
Short name T440
Test name
Test status
Simulation time 50093921 ps
CPU time 0.98 seconds
Started Jul 29 05:13:25 PM PDT 24
Finished Jul 29 05:13:26 PM PDT 24
Peak memory 207848 kb
Host smart-7b16d885-49da-418c-bb76-ef0f56f39df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041269929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3041269929
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1501899394
Short name T400
Test name
Test status
Simulation time 1971051515 ps
CPU time 12.49 seconds
Started Jul 29 05:13:11 PM PDT 24
Finished Jul 29 05:13:23 PM PDT 24
Peak memory 219912 kb
Host smart-86fd91b3-9075-4e5d-a824-5998e6af396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501899394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1501899394
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3384222282
Short name T861
Test name
Test status
Simulation time 1209699638 ps
CPU time 6.95 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:16 PM PDT 24
Peak memory 216688 kb
Host smart-765e94ad-3372-4143-b1bb-9ba183948850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384222282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3384222282
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4212021495
Short name T493
Test name
Test status
Simulation time 55590635 ps
CPU time 3.18 seconds
Started Jul 29 05:13:13 PM PDT 24
Finished Jul 29 05:13:16 PM PDT 24
Peak memory 216632 kb
Host smart-ee8b1a4a-7a64-43d8-946f-a05439e2d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212021495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4212021495
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.876257872
Short name T610
Test name
Test status
Simulation time 64736192 ps
CPU time 0.75 seconds
Started Jul 29 05:13:13 PM PDT 24
Finished Jul 29 05:13:14 PM PDT 24
Peak memory 206292 kb
Host smart-a5d40dea-1d52-499d-ae19-7c476fde5cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876257872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.876257872
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1461330379
Short name T123
Test name
Test status
Simulation time 164109701 ps
CPU time 2.78 seconds
Started Jul 29 05:13:09 PM PDT 24
Finished Jul 29 05:13:12 PM PDT 24
Peak memory 224852 kb
Host smart-7d069687-18d3-4040-a82f-8e10eafa3603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461330379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1461330379
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1176944892
Short name T786
Test name
Test status
Simulation time 14027050 ps
CPU time 0.75 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:36 PM PDT 24
Peak memory 206080 kb
Host smart-8931481b-d695-4df6-81a4-f410ba6a2cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176944892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
176944892
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4206015784
Short name T889
Test name
Test status
Simulation time 408153297 ps
CPU time 3.87 seconds
Started Jul 29 05:09:21 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 233016 kb
Host smart-9543b970-b8dd-4521-83a1-ef0e97136b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206015784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4206015784
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.588820657
Short name T507
Test name
Test status
Simulation time 53856938 ps
CPU time 0.79 seconds
Started Jul 29 05:09:45 PM PDT 24
Finished Jul 29 05:09:46 PM PDT 24
Peak memory 207184 kb
Host smart-d238ffb3-c799-4175-a4ec-6c50e22e0526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588820657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.588820657
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.126587349
Short name T955
Test name
Test status
Simulation time 8817949309 ps
CPU time 74.73 seconds
Started Jul 29 05:09:30 PM PDT 24
Finished Jul 29 05:10:45 PM PDT 24
Peak memory 240176 kb
Host smart-b677447f-a26b-4e28-b48a-300ec1f355ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126587349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.126587349
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.164297745
Short name T302
Test name
Test status
Simulation time 14853404128 ps
CPU time 15.7 seconds
Started Jul 29 05:09:28 PM PDT 24
Finished Jul 29 05:09:44 PM PDT 24
Peak memory 218156 kb
Host smart-fcec5c78-0083-483f-81a3-59e879c6e1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164297745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.164297745
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2036635414
Short name T959
Test name
Test status
Simulation time 3771487948 ps
CPU time 92.11 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:11:10 PM PDT 24
Peak memory 265464 kb
Host smart-73cdc106-77da-49fe-b0ed-b3d77ffe2108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036635414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2036635414
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1304553550
Short name T437
Test name
Test status
Simulation time 358830448 ps
CPU time 4.62 seconds
Started Jul 29 05:09:22 PM PDT 24
Finished Jul 29 05:09:27 PM PDT 24
Peak memory 224808 kb
Host smart-dc6a6670-751d-4c0c-a231-1bc141bb38da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304553550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1304553550
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1713752586
Short name T23
Test name
Test status
Simulation time 7337293511 ps
CPU time 22.25 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 249548 kb
Host smart-c030850f-880e-4c71-930d-91b507231603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713752586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1713752586
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2359471777
Short name T560
Test name
Test status
Simulation time 2227329165 ps
CPU time 22.74 seconds
Started Jul 29 05:09:46 PM PDT 24
Finished Jul 29 05:10:09 PM PDT 24
Peak memory 233176 kb
Host smart-74bd1752-dcec-4fc8-94da-485601960a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359471777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2359471777
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2870055919
Short name T397
Test name
Test status
Simulation time 5700883221 ps
CPU time 20.92 seconds
Started Jul 29 05:09:28 PM PDT 24
Finished Jul 29 05:09:49 PM PDT 24
Peak memory 224860 kb
Host smart-94d2e0fe-6d1b-427c-9781-0ed8bf00e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870055919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2870055919
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1988483864
Short name T552
Test name
Test status
Simulation time 1989954014 ps
CPU time 9.41 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:44 PM PDT 24
Peak memory 237680 kb
Host smart-d9787678-3ac3-4cb7-9a07-c2e2251d8df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988483864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1988483864
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2563469469
Short name T227
Test name
Test status
Simulation time 217903092 ps
CPU time 3.97 seconds
Started Jul 29 05:09:28 PM PDT 24
Finished Jul 29 05:09:32 PM PDT 24
Peak memory 224896 kb
Host smart-620ee679-890d-4170-86f8-2543e93f90b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563469469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2563469469
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.300951445
Short name T463
Test name
Test status
Simulation time 291491850 ps
CPU time 3.56 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:39 PM PDT 24
Peak memory 223524 kb
Host smart-81733096-2dc2-432c-8bea-eb599c1953aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300951445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.300951445
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.889108256
Short name T747
Test name
Test status
Simulation time 180883588 ps
CPU time 1.03 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:09:35 PM PDT 24
Peak memory 215708 kb
Host smart-bbcae9ba-b115-40f2-acdc-aa0bfe054cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889108256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.889108256
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.122192656
Short name T655
Test name
Test status
Simulation time 3019765806 ps
CPU time 9.33 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:09:42 PM PDT 24
Peak memory 216528 kb
Host smart-92a5fb91-00a0-4b16-a631-eb20868cde04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122192656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.122192656
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.400673838
Short name T689
Test name
Test status
Simulation time 4476871473 ps
CPU time 7.43 seconds
Started Jul 29 05:09:37 PM PDT 24
Finished Jul 29 05:09:44 PM PDT 24
Peak memory 216612 kb
Host smart-d252ed9d-5504-42de-8a00-668d4f9b8ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400673838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.400673838
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1770259029
Short name T47
Test name
Test status
Simulation time 28830507 ps
CPU time 1.16 seconds
Started Jul 29 05:09:26 PM PDT 24
Finished Jul 29 05:09:27 PM PDT 24
Peak memory 216544 kb
Host smart-d6aa676f-aeb1-4564-b837-5e33aaf2d51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770259029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1770259029
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1391794390
Short name T806
Test name
Test status
Simulation time 290840434 ps
CPU time 0.96 seconds
Started Jul 29 05:09:21 PM PDT 24
Finished Jul 29 05:09:22 PM PDT 24
Peak memory 206560 kb
Host smart-3b1020e8-7e3c-4b9f-932e-650f2acf14ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391794390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1391794390
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.804379527
Short name T770
Test name
Test status
Simulation time 9505136709 ps
CPU time 11.86 seconds
Started Jul 29 05:09:22 PM PDT 24
Finished Jul 29 05:09:34 PM PDT 24
Peak memory 241148 kb
Host smart-14e475c0-5a39-47bb-a99d-348ee77806bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804379527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.804379527
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3781409597
Short name T1005
Test name
Test status
Simulation time 64140911 ps
CPU time 0.68 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:09:35 PM PDT 24
Peak memory 205736 kb
Host smart-9113d4bf-46ec-47f1-9168-4559de8e89dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781409597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
781409597
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2378083533
Short name T645
Test name
Test status
Simulation time 369956050 ps
CPU time 2.19 seconds
Started Jul 29 05:09:48 PM PDT 24
Finished Jul 29 05:09:50 PM PDT 24
Peak memory 224568 kb
Host smart-bdeefa6c-3614-45b1-865a-9389c500526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378083533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2378083533
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.835574198
Short name T811
Test name
Test status
Simulation time 13227371 ps
CPU time 0.75 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:36 PM PDT 24
Peak memory 207272 kb
Host smart-9a89303a-f038-41f8-9e4a-fede0dd386be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835574198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.835574198
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.258216893
Short name T426
Test name
Test status
Simulation time 9665362077 ps
CPU time 106.68 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:11:38 PM PDT 24
Peak memory 249600 kb
Host smart-4f4e6041-f1a2-443a-aef3-a688411675a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258216893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.258216893
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.966480792
Short name T247
Test name
Test status
Simulation time 14395562062 ps
CPU time 40.37 seconds
Started Jul 29 05:09:47 PM PDT 24
Finished Jul 29 05:10:27 PM PDT 24
Peak memory 241352 kb
Host smart-23d1f069-5f6e-4c45-83d8-3b829b9df375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966480792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.966480792
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2332840465
Short name T301
Test name
Test status
Simulation time 333370416 ps
CPU time 8.43 seconds
Started Jul 29 05:09:47 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 233000 kb
Host smart-84580224-96e4-4103-aae4-bf9a3f2c925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332840465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2332840465
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2611636930
Short name T846
Test name
Test status
Simulation time 144576560771 ps
CPU time 294.61 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:14:30 PM PDT 24
Peak memory 250732 kb
Host smart-ac5187c0-e86f-42fe-b2d4-eeb39f589ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611636930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2611636930
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4228165581
Short name T471
Test name
Test status
Simulation time 210861895 ps
CPU time 3.67 seconds
Started Jul 29 05:09:37 PM PDT 24
Finished Jul 29 05:09:41 PM PDT 24
Peak memory 224868 kb
Host smart-59eaf148-ec78-4cdd-944f-e17157683ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228165581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4228165581
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3260171248
Short name T766
Test name
Test status
Simulation time 1556703831 ps
CPU time 9.11 seconds
Started Jul 29 05:09:32 PM PDT 24
Finished Jul 29 05:09:41 PM PDT 24
Peak memory 224804 kb
Host smart-20944939-3a09-4adf-abcc-59fd50b4ae98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260171248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3260171248
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1212738100
Short name T885
Test name
Test status
Simulation time 6605867346 ps
CPU time 20.42 seconds
Started Jul 29 05:09:32 PM PDT 24
Finished Jul 29 05:09:53 PM PDT 24
Peak memory 224892 kb
Host smart-ff4ec492-e958-43c2-a481-d2363615affd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212738100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1212738100
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3394692295
Short name T888
Test name
Test status
Simulation time 3820058201 ps
CPU time 12.45 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:09:46 PM PDT 24
Peak memory 224924 kb
Host smart-c322fdaf-0177-4644-87c1-833d1ceedcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394692295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3394692295
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3515738240
Short name T695
Test name
Test status
Simulation time 2279870335 ps
CPU time 7.74 seconds
Started Jul 29 05:09:37 PM PDT 24
Finished Jul 29 05:09:45 PM PDT 24
Peak memory 219280 kb
Host smart-13809307-0c9d-4686-95a8-0dec9d037618
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3515738240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3515738240
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3610708616
Short name T146
Test name
Test status
Simulation time 24903234897 ps
CPU time 140.2 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:11:54 PM PDT 24
Peak memory 252732 kb
Host smart-c675597d-971c-4fc3-9366-28a56be0fc8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610708616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3610708616
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2875851909
Short name T964
Test name
Test status
Simulation time 5333676899 ps
CPU time 23.26 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 220356 kb
Host smart-cb149f58-abe8-4d34-9f3c-2f6aad84fb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875851909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2875851909
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.897478396
Short name T735
Test name
Test status
Simulation time 943713993 ps
CPU time 7.09 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:09:45 PM PDT 24
Peak memory 216540 kb
Host smart-385f47aa-c290-4316-8bf5-7e0c8ab7d07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897478396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.897478396
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3647483813
Short name T622
Test name
Test status
Simulation time 30193261 ps
CPU time 1.76 seconds
Started Jul 29 05:09:27 PM PDT 24
Finished Jul 29 05:09:29 PM PDT 24
Peak memory 216628 kb
Host smart-75aab99b-27ff-45f1-9400-a60ebd08d290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647483813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3647483813
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.928651988
Short name T367
Test name
Test status
Simulation time 207635020 ps
CPU time 0.9 seconds
Started Jul 29 05:09:38 PM PDT 24
Finished Jul 29 05:09:39 PM PDT 24
Peak memory 206288 kb
Host smart-ae8ea91d-c302-4a62-9028-9a734f05eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928651988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.928651988
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.940800634
Short name T998
Test name
Test status
Simulation time 5585270377 ps
CPU time 15.22 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:09:50 PM PDT 24
Peak memory 233100 kb
Host smart-5743da21-a60e-438e-8804-a68edb891ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940800634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.940800634
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1500646376
Short name T492
Test name
Test status
Simulation time 12104408 ps
CPU time 0.72 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:09:42 PM PDT 24
Peak memory 205224 kb
Host smart-e7843840-9e07-4a78-9ae5-fa5f8239d908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500646376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
500646376
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4110331494
Short name T371
Test name
Test status
Simulation time 83796030 ps
CPU time 3.32 seconds
Started Jul 29 05:09:49 PM PDT 24
Finished Jul 29 05:09:52 PM PDT 24
Peak memory 233044 kb
Host smart-80ca2930-9fce-46fd-9b40-615423bbcc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110331494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4110331494
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4023061320
Short name T52
Test name
Test status
Simulation time 14389648 ps
CPU time 0.77 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:09:35 PM PDT 24
Peak memory 206960 kb
Host smart-0025c58f-c60c-48d6-af40-f5681892b6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023061320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4023061320
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2878700085
Short name T741
Test name
Test status
Simulation time 28327065484 ps
CPU time 82.88 seconds
Started Jul 29 05:09:43 PM PDT 24
Finished Jul 29 05:11:06 PM PDT 24
Peak memory 257164 kb
Host smart-690994b7-d4fd-4452-8929-3f4162b095cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878700085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2878700085
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1172063641
Short name T938
Test name
Test status
Simulation time 41765217647 ps
CPU time 115.58 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:11:37 PM PDT 24
Peak memory 266764 kb
Host smart-e55e0899-2dd3-4ac1-bea1-8c36e8b6b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172063641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1172063641
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1582170765
Short name T740
Test name
Test status
Simulation time 67621925740 ps
CPU time 35.04 seconds
Started Jul 29 05:09:35 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 224812 kb
Host smart-50639723-93c6-4d37-8b49-c28b68f32e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582170765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1582170765
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2074596348
Short name T584
Test name
Test status
Simulation time 413445964 ps
CPU time 5.33 seconds
Started Jul 29 05:09:36 PM PDT 24
Finished Jul 29 05:09:41 PM PDT 24
Peak memory 224936 kb
Host smart-e445f015-7dc0-4b5d-8c94-ccb9a5daf150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074596348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2074596348
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.513691306
Short name T260
Test name
Test status
Simulation time 637165598 ps
CPU time 9.48 seconds
Started Jul 29 05:09:36 PM PDT 24
Finished Jul 29 05:09:45 PM PDT 24
Peak memory 224760 kb
Host smart-6753b175-d877-451e-ab45-536d442581aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513691306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.513691306
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.619369175
Short name T725
Test name
Test status
Simulation time 30487834 ps
CPU time 2.2 seconds
Started Jul 29 05:09:36 PM PDT 24
Finished Jul 29 05:09:39 PM PDT 24
Peak memory 224452 kb
Host smart-2171257d-0bb3-4b00-a944-089bf38038aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619369175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
619369175
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4177094751
Short name T963
Test name
Test status
Simulation time 5128965473 ps
CPU time 11.04 seconds
Started Jul 29 05:09:40 PM PDT 24
Finished Jul 29 05:09:51 PM PDT 24
Peak memory 233132 kb
Host smart-9ab7e716-cd02-4fbc-ac3f-027e1c4c2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177094751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4177094751
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2706048774
Short name T602
Test name
Test status
Simulation time 1260338738 ps
CPU time 9.22 seconds
Started Jul 29 05:09:34 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 221316 kb
Host smart-42828de9-35be-4ff5-8aea-959080374e87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2706048774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2706048774
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2147729462
Short name T323
Test name
Test status
Simulation time 14683628 ps
CPU time 0.77 seconds
Started Jul 29 05:09:36 PM PDT 24
Finished Jul 29 05:09:37 PM PDT 24
Peak memory 206016 kb
Host smart-c1d69b51-15a9-4d4e-aee0-0f424f03132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147729462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2147729462
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1325212312
Short name T315
Test name
Test status
Simulation time 198006367 ps
CPU time 2.04 seconds
Started Jul 29 05:09:36 PM PDT 24
Finished Jul 29 05:09:38 PM PDT 24
Peak memory 216620 kb
Host smart-a1c18fc2-9e05-441f-9499-b890f86d4689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325212312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1325212312
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2371241357
Short name T577
Test name
Test status
Simulation time 20899713 ps
CPU time 1.27 seconds
Started Jul 29 05:09:33 PM PDT 24
Finished Jul 29 05:09:35 PM PDT 24
Peak memory 216604 kb
Host smart-27f16545-65a7-4289-96ed-ea1b9098519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371241357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2371241357
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.972264816
Short name T372
Test name
Test status
Simulation time 87102470 ps
CPU time 0.85 seconds
Started Jul 29 05:09:45 PM PDT 24
Finished Jul 29 05:09:46 PM PDT 24
Peak memory 206344 kb
Host smart-91e42214-dde5-4d78-b26a-a43c325f93f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972264816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.972264816
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1476199498
Short name T167
Test name
Test status
Simulation time 35239692946 ps
CPU time 27.56 seconds
Started Jul 29 05:09:36 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 249588 kb
Host smart-d1a6bc63-abcd-4b75-957d-6661ed492079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476199498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1476199498
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3474640036
Short name T511
Test name
Test status
Simulation time 25968759 ps
CPU time 0.74 seconds
Started Jul 29 05:09:46 PM PDT 24
Finished Jul 29 05:09:47 PM PDT 24
Peak memory 205204 kb
Host smart-9411f8c6-a4a6-449d-b6c1-8a71fc7a5f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474640036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
474640036
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.975499858
Short name T930
Test name
Test status
Simulation time 780242211 ps
CPU time 8.59 seconds
Started Jul 29 05:09:43 PM PDT 24
Finished Jul 29 05:09:51 PM PDT 24
Peak memory 233116 kb
Host smart-5c8d7a7d-a4da-485a-b655-dba4b579eeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975499858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.975499858
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1018181845
Short name T75
Test name
Test status
Simulation time 17140555 ps
CPU time 0.83 seconds
Started Jul 29 05:09:44 PM PDT 24
Finished Jul 29 05:09:45 PM PDT 24
Peak memory 206976 kb
Host smart-08470afc-e277-402e-aec0-921e0369ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018181845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1018181845
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3756408131
Short name T292
Test name
Test status
Simulation time 52038782610 ps
CPU time 173.76 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:12:35 PM PDT 24
Peak memory 257492 kb
Host smart-73c2b8dd-9228-4e8b-b6dd-fc8fd35e158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756408131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3756408131
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.662387265
Short name T147
Test name
Test status
Simulation time 3655800295 ps
CPU time 81.96 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:11:04 PM PDT 24
Peak memory 256672 kb
Host smart-07636919-9f3d-4d9a-818d-4b1db7b8e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662387265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.662387265
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3604530670
Short name T469
Test name
Test status
Simulation time 27074614 ps
CPU time 0.82 seconds
Started Jul 29 05:09:45 PM PDT 24
Finished Jul 29 05:09:45 PM PDT 24
Peak memory 217564 kb
Host smart-86e09377-0979-408d-9ce6-e997206a5580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604530670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3604530670
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2560426420
Short name T921
Test name
Test status
Simulation time 901335885 ps
CPU time 6.68 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:09:49 PM PDT 24
Peak memory 235688 kb
Host smart-8f04dff7-c833-4a99-a4f0-6058b9b876ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560426420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2560426420
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2993556239
Short name T562
Test name
Test status
Simulation time 2599094884 ps
CPU time 22.55 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:10:05 PM PDT 24
Peak memory 233184 kb
Host smart-c4b84b51-fd64-43f2-84e7-156c624ef12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993556239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2993556239
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2968114022
Short name T845
Test name
Test status
Simulation time 1937033976 ps
CPU time 22.39 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:10:05 PM PDT 24
Peak memory 224832 kb
Host smart-7411000d-9011-4246-9730-caca8b11e56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968114022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2968114022
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2205515357
Short name T363
Test name
Test status
Simulation time 7373666157 ps
CPU time 14.36 seconds
Started Jul 29 05:09:46 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 233096 kb
Host smart-508b0fc6-55a4-4875-bcc6-14b5de428fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205515357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2205515357
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.472993867
Short name T976
Test name
Test status
Simulation time 6484701825 ps
CPU time 21.06 seconds
Started Jul 29 05:09:44 PM PDT 24
Finished Jul 29 05:10:05 PM PDT 24
Peak memory 233188 kb
Host smart-30302f87-4321-4183-b037-c119972d9447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472993867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
472993867
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2225551712
Short name T480
Test name
Test status
Simulation time 1128987626 ps
CPU time 10.62 seconds
Started Jul 29 05:09:43 PM PDT 24
Finished Jul 29 05:09:53 PM PDT 24
Peak memory 249008 kb
Host smart-469afa0f-75f1-4de2-9d2b-b22c98079a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225551712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2225551712
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2572357151
Short name T365
Test name
Test status
Simulation time 2450387780 ps
CPU time 16.3 seconds
Started Jul 29 05:09:43 PM PDT 24
Finished Jul 29 05:09:59 PM PDT 24
Peak memory 222460 kb
Host smart-91002a81-9e90-4372-bf30-1f13e5219d8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2572357151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2572357151
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2026650420
Short name T18
Test name
Test status
Simulation time 224311763 ps
CPU time 0.95 seconds
Started Jul 29 05:09:48 PM PDT 24
Finished Jul 29 05:09:49 PM PDT 24
Peak memory 206424 kb
Host smart-21ae5562-400a-40fc-93a6-626bed450738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026650420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2026650420
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3313470428
Short name T589
Test name
Test status
Simulation time 1174700113 ps
CPU time 4.88 seconds
Started Jul 29 05:09:47 PM PDT 24
Finished Jul 29 05:09:52 PM PDT 24
Peak memory 216532 kb
Host smart-da5d0fff-2987-436f-9b29-8e9db3d4feee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313470428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3313470428
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4182233942
Short name T328
Test name
Test status
Simulation time 16713357 ps
CPU time 0.73 seconds
Started Jul 29 05:09:46 PM PDT 24
Finished Jul 29 05:09:47 PM PDT 24
Peak memory 205964 kb
Host smart-5b74869a-ca21-4997-b8dc-3d9b615612dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182233942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4182233942
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2253334057
Short name T350
Test name
Test status
Simulation time 213816050 ps
CPU time 2.58 seconds
Started Jul 29 05:09:45 PM PDT 24
Finished Jul 29 05:09:47 PM PDT 24
Peak memory 216628 kb
Host smart-987a9e05-0c31-4388-a3cb-906277eb2e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253334057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2253334057
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2623079761
Short name T508
Test name
Test status
Simulation time 141940542 ps
CPU time 1.11 seconds
Started Jul 29 05:09:41 PM PDT 24
Finished Jul 29 05:09:42 PM PDT 24
Peak memory 206724 kb
Host smart-ce18f21b-0611-4ecb-b1b7-258a6334d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623079761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2623079761
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4186292745
Short name T314
Test name
Test status
Simulation time 92329845 ps
CPU time 2.38 seconds
Started Jul 29 05:09:47 PM PDT 24
Finished Jul 29 05:09:49 PM PDT 24
Peak memory 224336 kb
Host smart-716a1414-0f96-4ad8-8aad-e1a9ed2b6849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186292745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4186292745
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3138192806
Short name T376
Test name
Test status
Simulation time 37486096 ps
CPU time 0.74 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:09:52 PM PDT 24
Peak memory 205776 kb
Host smart-9511f141-d99c-4226-aac3-d004e6652488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138192806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
138192806
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3309768954
Short name T971
Test name
Test status
Simulation time 1676419444 ps
CPU time 10.78 seconds
Started Jul 29 05:09:52 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 224832 kb
Host smart-8d021736-9c06-4863-8969-d268076603ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309768954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3309768954
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.577644029
Short name T332
Test name
Test status
Simulation time 30730597 ps
CPU time 0.79 seconds
Started Jul 29 05:09:42 PM PDT 24
Finished Jul 29 05:09:43 PM PDT 24
Peak memory 206960 kb
Host smart-fb195a64-6e45-4890-80ea-caf7943aec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577644029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.577644029
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.271851921
Short name T289
Test name
Test status
Simulation time 110295606605 ps
CPU time 523.88 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 249564 kb
Host smart-5bd88c8a-1db9-44c8-9a87-a301842dca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271851921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.271851921
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.973904410
Short name T36
Test name
Test status
Simulation time 58777226887 ps
CPU time 150.65 seconds
Started Jul 29 05:09:57 PM PDT 24
Finished Jul 29 05:12:28 PM PDT 24
Peak memory 256484 kb
Host smart-a22fd008-ed4d-4a01-9bde-64f9ff7fb33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973904410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.973904410
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.162302165
Short name T909
Test name
Test status
Simulation time 6500150156 ps
CPU time 39.54 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:10:35 PM PDT 24
Peak memory 241360 kb
Host smart-7cea99fb-55bd-4c33-b4e5-6cf2e074b9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162302165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
162302165
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4186057213
Short name T638
Test name
Test status
Simulation time 293114724 ps
CPU time 4.21 seconds
Started Jul 29 05:09:54 PM PDT 24
Finished Jul 29 05:09:58 PM PDT 24
Peak memory 233144 kb
Host smart-24051024-ba62-460c-91c9-03bb181d6dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186057213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4186057213
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1338645529
Short name T185
Test name
Test status
Simulation time 5901573144 ps
CPU time 75.57 seconds
Started Jul 29 05:09:53 PM PDT 24
Finished Jul 29 05:11:09 PM PDT 24
Peak memory 253124 kb
Host smart-727d05bd-27ac-4d96-bab3-9da8707c40f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338645529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1338645529
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2516201191
Short name T975
Test name
Test status
Simulation time 851417893 ps
CPU time 4.8 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 227768 kb
Host smart-837f7da7-3bfe-4bbb-91f6-cb3a376273bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516201191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2516201191
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2509032906
Short name T932
Test name
Test status
Simulation time 2093846711 ps
CPU time 16.56 seconds
Started Jul 29 05:09:53 PM PDT 24
Finished Jul 29 05:10:10 PM PDT 24
Peak memory 232944 kb
Host smart-5c41e7ce-87bb-4cf3-84dc-c6b5cd7453eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509032906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2509032906
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.324745314
Short name T539
Test name
Test status
Simulation time 4419396395 ps
CPU time 12.24 seconds
Started Jul 29 05:09:55 PM PDT 24
Finished Jul 29 05:10:08 PM PDT 24
Peak memory 233072 kb
Host smart-f05f6fcd-fa17-443f-9885-925739c433ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324745314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
324745314
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1584283512
Short name T819
Test name
Test status
Simulation time 2810977546 ps
CPU time 8.49 seconds
Started Jul 29 05:09:52 PM PDT 24
Finished Jul 29 05:10:01 PM PDT 24
Peak memory 224892 kb
Host smart-aedccbf0-6b98-48d7-8811-5a7c8bd2a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584283512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1584283512
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2621329024
Short name T918
Test name
Test status
Simulation time 328966209 ps
CPU time 5.47 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:09:57 PM PDT 24
Peak memory 223448 kb
Host smart-ca66e8a9-3624-4bdf-b04c-90f6ec8dc9ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2621329024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2621329024
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2996895290
Short name T288
Test name
Test status
Simulation time 24162710120 ps
CPU time 56.75 seconds
Started Jul 29 05:09:52 PM PDT 24
Finished Jul 29 05:10:49 PM PDT 24
Peak memory 233104 kb
Host smart-d646fe21-e2fb-4600-8d3a-396c04784839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996895290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2996895290
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3675875158
Short name T605
Test name
Test status
Simulation time 988661679 ps
CPU time 16.27 seconds
Started Jul 29 05:09:51 PM PDT 24
Finished Jul 29 05:10:07 PM PDT 24
Peak memory 220364 kb
Host smart-8b40d890-ab59-4d3d-a2ec-97ff03589025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675875158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3675875158
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.962348309
Short name T952
Test name
Test status
Simulation time 2293576594 ps
CPU time 9.87 seconds
Started Jul 29 05:09:52 PM PDT 24
Finished Jul 29 05:10:02 PM PDT 24
Peak memory 216596 kb
Host smart-30679b32-5b38-46fd-b7c5-92ef25bc9dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962348309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.962348309
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4150013512
Short name T611
Test name
Test status
Simulation time 105727218 ps
CPU time 6.03 seconds
Started Jul 29 05:09:54 PM PDT 24
Finished Jul 29 05:10:00 PM PDT 24
Peak memory 216464 kb
Host smart-c6fccac8-da59-4470-bb26-6af21a6c887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150013512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4150013512
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.14004372
Short name T686
Test name
Test status
Simulation time 149752125 ps
CPU time 0.85 seconds
Started Jul 29 05:09:53 PM PDT 24
Finished Jul 29 05:09:54 PM PDT 24
Peak memory 207228 kb
Host smart-429dac48-7276-4949-9975-af885fe68a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14004372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.14004372
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.72766358
Short name T505
Test name
Test status
Simulation time 218542076 ps
CPU time 2.34 seconds
Started Jul 29 05:09:53 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 224596 kb
Host smart-53f714f5-8544-4598-a929-24410a0eda4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72766358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.72766358
Directory /workspace/9.spi_device_upload/latest
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