Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2650311	1			T1	1		T2	1		T4	1
all_values[1]	2650311	1			T1	1		T2	1		T4	1
all_values[2]	2650311	1			T1	1		T2	1		T4	1
all_values[3]	2650311	1			T1	1		T2	1		T4	1
all_values[4]	2650311	1			T1	1		T2	1		T4	1
all_values[5]	2650311	1			T1	1		T2	1		T4	1
all_values[6]	2650311	1			T1	1		T2	1		T4	1
all_values[7]	2650311	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20459373

1

T1

8

T2

8

T4

8

auto[1]

743115

1

T15

1037

T16

76

T17

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21177149

1

T1

8

T2

8

T4

8

auto[1]

25339

1

T7

65

T10

20

T11

75

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2555080	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	12227	1			T7	23		T10	10		T11	75
all_values[0]	auto[1]	auto[0]	82761	1			T15	2		T16	7		T17	10
all_values[0]	auto[1]	auto[1]	243	1			T15	2		T16	5		T17	1
all_values[1]	auto[0]	auto[0]	2642077	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	7730	1			T7	23		T10	10		T30	83
all_values[1]	auto[1]	auto[0]	310	1			T15	1		T16	9		T17	2
all_values[1]	auto[1]	auto[1]	194	1			T15	3		T16	1		T17	2
all_values[2]	auto[0]	auto[0]	2514419	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	2697	1			T7	19		T14	76		T25	27
all_values[2]	auto[1]	auto[0]	132955	1			T15	1		T16	6		T17	1
all_values[2]	auto[1]	auto[1]	240	1			T15	2		T16	4		T18	6
all_values[3]	auto[0]	auto[0]	2515897	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	202	1			T15	2		T17	1		T18	3
all_values[3]	auto[1]	auto[0]	134021	1			T15	2		T16	8		T17	1
all_values[3]	auto[1]	auto[1]	191	1			T15	1		T16	1		T17	1
all_values[4]	auto[0]	auto[0]	2520705	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	229	1			T15	3		T16	1		T17	3
all_values[4]	auto[1]	auto[0]	129168	1			T15	3		T16	6		T17	3
all_values[4]	auto[1]	auto[1]	209	1			T15	1		T16	2		T17	2
all_values[5]	auto[0]	auto[0]	2600156	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	187	1			T17	2		T18	5		T19	1
all_values[5]	auto[1]	auto[0]	49780	1			T15	505		T16	7		T17	5
all_values[5]	auto[1]	auto[1]	188	1			T15	4		T16	4		T17	3
all_values[6]	auto[0]	auto[0]	2564223	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	192	1			T15	2		T16	1		T17	2
all_values[6]	auto[1]	auto[0]	85686	1			T15	506		T16	3		T17	3
all_values[6]	auto[1]	auto[1]	210	1			T16	1		T17	4		T18	10
all_values[7]	auto[0]	auto[0]	2523158	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	194	1			T15	4		T17	5		T18	6
all_values[7]	auto[1]	auto[0]	126753	1			T15	2		T16	8		T18	1
all_values[7]	auto[1]	auto[1]	206	1			T15	2		T16	4		T17	1