Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33696	1			T4	6		T7	203		T9	158
auto[SpiFlashAddrCfg]	7874	1			T2	12		T7	38		T9	42
auto[SpiFlashAddr3b]	9197	1			T7	64		T9	40		T10	68
auto[SpiFlashAddr4b]	7911	1			T2	8		T4	4		T5	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34608

1

T4

10

T5

1

T7

241

auto[1]

24070

1

T2

20

T7

88

T9

151

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31311

1

T2

12

T5

1

T7

180

auto[1]

27367

1

T2

8

T4

10

T7

149

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38527	1			T2	2		T4	6		T7	234
values[1]	1070	1			T7	9		T9	9		T10	12
values[2]	1446	1			T7	5		T9	6		T10	17
values[3]	1539	1			T2	4		T7	8		T9	6
values[4]	1525	1			T2	2		T4	4		T7	6
values[5]	1457	1			T7	3		T9	7		T10	9
values[6]	1389	1			T2	2		T7	10		T9	15
values[7]	1588	1			T2	2		T7	6		T9	12
values[8]	10137	1			T2	8		T5	1		T7	48

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31971

1

T2

20

T4

10

T7

329

auto[1]

26707

1

T5

1

T11

112

T12

426

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55403

1

T2

18

T4

10

T5

1

write

3275

1

T2

2

T7

20

T9

22

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19764

1

T2

16

T4

4

T5

1

valids[0x1]

38914

1

T2

4

T4

6

T7

245

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1556	1			T7	4		T9	4		T10	8
internal_process_ops[0x5a]	1556	1			T7	7		T9	7		T10	6
internal_process_ops[0x05]	19746	1			T7	156		T9	96		T10	205
internal_process_ops[0x35]	1630	1			T4	6		T7	4		T9	5
internal_process_ops[0x15]	1605	1			T7	4		T9	7		T10	12
internal_process_ops[0x03]	1060	1			T7	5		T9	8		T10	8
internal_process_ops[0x0b]	1134	1			T7	8		T9	6		T10	15
internal_process_ops[0x3b]	1089	1			T7	5		T9	8		T10	9
internal_process_ops[0x6b]	1092	1			T7	7		T9	5		T10	5
internal_process_ops[0xbb]	1099	1			T2	4		T4	4		T5	1
internal_process_ops[0xeb]	1044	1			T7	3		T9	10		T10	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57033

1

T2

18

T4

10

T5

1

auto[1]

1645

1

T2

2

T7

7

T9

13

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56295

1

T2

20

T4

10

T5

1

auto[1]

2383

1

T7

12

T9

8

T10

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10992

1

T4

6

T7

178

T9

74

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6271

1

T7

21

T9

77

T10

144

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2123

1

T7

16

T9

15

T10

24

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2014

1

T2

10

T7

19

T9

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2631

1

T7

29

T9

22

T10

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2147

1

T7

26

T9

17

T10

41

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2247

1

T4

4

T7

11

T9

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1937

1

T2

8

T7

9

T9

19

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T7

1

T10

1

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

89

1

T10

2

T14

1

T39

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T10

1

T22

1

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T7

3

T9

7

T10

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

136

1

T7

2

T9

2

T10

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

91

1

T7

1

T9

1

T22

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T9

1

T30

3

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

109

1

T2

2

T10

2

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

108

1

T7

3

T10

1

T22

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

109

1

T10

1

T22

1

T39

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

83

1

T7

3

T9

1

T10

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T7

3

T10

3

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

131

1

T9

1

T10

1

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T9

3

T16

1

T149

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

106

1

T7

4

T9

4

T10

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T9

2

T30

1

T22

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10193

1

T11

42

T12

211

T13

47

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5489

1

T11

11

T12

97

T13

86

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1462

1

T11

11

T12

10

T13

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1401

1

T11

15

T12

9

T13

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1821

1

T11

13

T12

15

T13

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1753

1

T11

10

T12

17

T13

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1451

1

T5

1

T11

4

T12

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1471

1

T11

5

T12

18

T13

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

72

1

T11

1

T12

1

T13

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

88

1

T13

1

T27

3

T150

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T12

6

T14

2

T102

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

114

1

T13

1

T27

5

T102

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T13

1

T14

2

T25

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

136

1

T12

5

T25

1

T150

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T13

1

T31

5

T151

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T102

1

T152

1

T61

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

114

1

T12

6

T14

2

T25

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

91

1

T12

4

T27

3

T61

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

123

1

T12

3

T14

3

T25

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

107

1

T12

2

T13

3

T14

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T12

1

T14

6

T25

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

119

1

T14

4

T25

1

T27

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T13

2

T25

2

T17

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T12

1

T14

5

T25

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4106	1			T7	33		T9	32		T10	63
auto[0]	values[0]	valids[0x1]	16175	1			T2	2		T4	6		T7	201
auto[0]	values[1]	valids[0x1]	558	1			T7	9		T9	9		T10	12
auto[0]	values[2]	valids[0x0]	525	1			T7	4		T9	3		T10	12
auto[0]	values[2]	valids[0x1]	303	1			T7	1		T9	3		T10	5
auto[0]	values[3]	valids[0x0]	554	1			T2	4		T7	6		T9	1
auto[0]	values[3]	valids[0x1]	336	1			T7	2		T9	5		T10	3
auto[0]	values[4]	valids[0x0]	591	1			T2	2		T4	4		T7	5
auto[0]	values[4]	valids[0x1]	325	1			T7	1		T9	7		T10	5
auto[0]	values[5]	valids[0x0]	548	1			T9	6		T10	8		T30	2
auto[0]	values[5]	valids[0x1]	296	1			T7	3		T9	1		T10	1
auto[0]	values[6]	valids[0x0]	567	1			T2	2		T7	7		T9	11
auto[0]	values[6]	valids[0x1]	265	1			T7	3		T9	4		T10	2
auto[0]	values[7]	valids[0x0]	619	1			T7	2		T9	5		T10	10
auto[0]	values[7]	valids[0x1]	302	1			T2	2		T7	4		T9	7
auto[0]	values[8]	valids[0x0]	3655	1			T2	8		T7	27		T9	29
auto[0]	values[8]	valids[0x1]	2246	1			T7	21		T9	10		T10	30
auto[1]	values[0]	valids[0x0]	3787	1			T11	32		T12	35		T13	35
auto[1]	values[0]	valids[0x1]	14459	1			T11	36		T12	303		T13	115
auto[1]	values[1]	valids[0x1]	512	1			T11	6		T12	3		T13	8
auto[1]	values[2]	valids[0x0]	362	1			T11	3		T12	4		T13	3
auto[1]	values[2]	valids[0x1]	256	1			T12	6		T13	2		T14	3
auto[1]	values[3]	valids[0x0]	427	1			T11	1		T12	1		T13	5
auto[1]	values[3]	valids[0x1]	222	1			T12	4		T14	3		T25	1
auto[1]	values[4]	valids[0x0]	348	1			T11	3		T12	5		T13	1
auto[1]	values[4]	valids[0x1]	261	1			T12	3		T13	2		T14	3
auto[1]	values[5]	valids[0x0]	395	1			T12	6		T13	1		T14	4
auto[1]	values[5]	valids[0x1]	218	1			T12	6		T13	2		T14	4
auto[1]	values[6]	valids[0x0]	340	1			T11	1		T12	5		T13	3
auto[1]	values[6]	valids[0x1]	217	1			T11	1		T12	1		T13	3
auto[1]	values[7]	valids[0x0]	421	1			T11	3		T12	3		T13	1
auto[1]	values[7]	valids[0x1]	246	1			T13	1		T14	2		T25	7
auto[1]	values[8]	valids[0x0]	2519	1			T5	1		T11	16		T12	21
auto[1]	values[8]	valids[0x1]	1717	1			T11	10		T12	20		T13	22