Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3537337

1

T2

1

T4

863

T5

175

auto[1]

30596

1

T7

149

T9

88

T10

198

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037438

1

T2

1

T4

719

T5

175

auto[1]

2530495

1

T4

144

T7

11150

T9

14734

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	734683	1			T2	1		T4	51		T5	171
auto[524288:1048575]	407886	1			T4	155		T7	3		T9	2881
auto[1048576:1572863]	438300	1			T4	4		T5	4		T7	5441
auto[1572864:2097151]	419981	1			T4	18		T7	626		T9	1858
auto[2097152:2621439]	401609	1			T4	135		T7	1030		T9	5398
auto[2621440:3145727]	378342	1			T4	383		T7	3464		T9	515
auto[3145728:3670015]	411942	1			T4	117		T7	515		T9	31
auto[3670016:4194303]	375190	1			T7	132		T9	528		T10	34

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2565399

1

T2

1

T4

173

T5

5

auto[1]

1002534

1

T4

690

T5

170

T7

4

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3065607

1

T2

1

T4

863

T5

175

auto[1]

502326

1

T7

2643

T9

2982

T10

1019

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	234518	1			T2	1		T4	29		T5	171
auto[0]	auto[0]	auto[0:524287]	auto[1]	422485	1			T4	22		T10	4073		T11	256
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	117209	1			T4	150		T10	7		T11	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	231056	1			T4	5		T9	2881		T10	513
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	130035	1			T4	3		T5	4		T7	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	251844	1			T4	1		T7	3334		T9	1119
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	95913	1			T4	18		T7	11		T9	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	238379	1			T7	517		T9	1846		T10	5162
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	103931	1			T4	135		T7	5		T9	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	221411	1			T7	1024		T9	4824		T10	4935
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	105558	1			T4	267		T7	13		T9	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	227156	1			T4	116		T7	3410		T9	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	129136	1			T4	117		T9	2		T10	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	205327	1			T9	5		T10	532		T12	3225
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	102993	1			T7	3		T9	4		T10	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	224972	1			T7	128		T9	513		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	3310	1			T9	2		T11	5		T12	12
auto[0]	auto[1]	auto[0:524287]	auto[1]	69298	1			T9	2441		T10	128		T11	100
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1447	1			T7	3		T10	8		T12	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	54229	1			T10	1		T12	256		T13	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	561	1			T7	3		T10	1		T13	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51502	1			T7	2087		T10	512		T13	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3087	1			T10	10		T13	1		T30	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	79425	1			T10	130		T13	76		T14	4712
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3148	1			T7	1		T9	1		T10	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	69509	1			T9	512		T10	1		T14	1300
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	655	1			T7	2		T10	3		T11	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	42057	1			T7	1		T10	128		T11	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1103	1			T7	3		T9	3		T11	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	73756	1			T7	512		T9	1		T11	514
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	526	1			T7	1		T9	2		T11	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	41801	1			T13	256		T22	3		T27	390
auto[1]	auto[0]	auto[0:524287]	auto[0]	527	1			T10	2		T30	6		T14	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3634	1			T10	46		T30	9		T25	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	484	1			T10	1		T11	1		T12	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2605	1			T11	1		T12	8		T27	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	418	1			T7	1		T10	1		T25	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2635	1			T7	9		T10	4		T25	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	388	1			T7	5		T9	1		T10	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2226	1			T7	93		T9	6		T10	22
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	444	1			T9	5		T13	1		T27	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2660	1			T9	47		T13	31		T27	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	386	1			T7	4		T12	3		T14	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2252	1			T7	7		T12	29		T14	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	387	1			T30	2		T14	3		T102	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1912	1			T30	8		T14	3		T16	8
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	442	1			T9	1		T10	1		T11	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2284	1			T9	8		T10	24		T12	2
auto[1]	auto[1]	auto[0:524287]	auto[0]	114	1			T11	3		T12	5		T151	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	797	1			T11	1		T12	60		T151	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	125	1			T10	1		T13	1		T76	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	731	1			T10	35		T13	30		T150	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	111	1			T7	1		T16	1		T186	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1194	1			T7	2		T16	10		T186	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	110	1			T10	2		T14	3		T22	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	453	1			T10	14		T14	6		T22	79
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	103	1			T10	1		T14	2		T16	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	403	1			T10	43		T14	8		T16	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	90	1			T7	1		T11	1		T14	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	188	1			T7	26		T11	1		T14	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	81	1			T9	1		T11	2		T12	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	240	1			T9	19		T12	65		T149	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	98	1			T22	3		T27	2		T102	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	2074	1			T22	136		T27	1		T61	215

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2049096	1			T2	1		T4	173		T5	5
auto[0]	auto[0]	auto[1]	992827	1			T4	690		T5	170		T7	3
auto[0]	auto[1]	auto[0]	486456	1			T7	2613		T9	2962		T10	922
auto[0]	auto[1]	auto[1]	8958	1			T10	1		T12	6		T13	1
auto[1]	auto[0]	auto[0]	23088	1			T7	118		T9	64		T10	102
auto[1]	auto[0]	auto[1]	596	1			T7	1		T9	4		T12	8
auto[1]	auto[1]	auto[0]	6759	1			T7	30		T9	19		T10	95
auto[1]	auto[1]	auto[1]	153	1			T9	1		T10	1		T12	7