Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2650311	1			T1	1		T2	1		T4	1
all_pins[1]	2650311	1			T1	1		T2	1		T4	1
all_pins[2]	2650311	1			T1	1		T2	1		T4	1
all_pins[3]	2650311	1			T1	1		T2	1		T4	1
all_pins[4]	2650311	1			T1	1		T2	1		T4	1
all_pins[5]	2650311	1			T1	1		T2	1		T4	1
all_pins[6]	2650311	1			T1	1		T2	1		T4	1
all_pins[7]	2650311	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21115390	1			T1	8		T2	8		T4	8
values[0x1]	87098	1			T15	15		T16	22		T17	14
transitions[0x0=>0x1]	86460	1			T15	14		T16	20		T17	10
transitions[0x1=>0x0]	86476	1			T15	14		T16	20		T17	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2650047	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	264	1			T15	2		T16	5		T17	1
all_pins[0]	transitions[0x0=>0x1]	220	1			T15	1		T16	5		T17	1
all_pins[0]	transitions[0x1=>0x0]	150	1			T15	2		T16	1		T17	2
all_pins[1]	values[0x0]	2650117	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	194	1			T15	3		T16	1		T17	2
all_pins[1]	transitions[0x0=>0x1]	133	1			T15	3		T16	1		T17	2
all_pins[1]	transitions[0x1=>0x0]	194	1			T15	2		T16	4		T18	3
all_pins[2]	values[0x0]	2650056	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	255	1			T15	2		T16	4		T18	6
all_pins[2]	transitions[0x0=>0x1]	196	1			T15	2		T16	3		T18	6
all_pins[2]	transitions[0x1=>0x0]	132	1			T15	1		T17	1		T18	4
all_pins[3]	values[0x0]	2650120	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	191	1			T15	1		T16	1		T17	1
all_pins[3]	transitions[0x0=>0x1]	145	1			T15	1		T16	1		T18	4
all_pins[3]	transitions[0x1=>0x0]	163	1			T15	1		T16	2		T17	1
all_pins[4]	values[0x0]	2650102	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	209	1			T15	1		T16	2		T17	2
all_pins[4]	transitions[0x0=>0x1]	172	1			T15	1		T16	1		T17	2
all_pins[4]	transitions[0x1=>0x0]	761	1			T15	4		T16	3		T17	3
all_pins[5]	values[0x0]	2649513	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	798	1			T15	4		T16	4		T17	3
all_pins[5]	transitions[0x0=>0x1]	511	1			T15	4		T16	4		T17	1
all_pins[5]	transitions[0x1=>0x0]	84694	1			T16	1		T17	2		T18	9
all_pins[6]	values[0x0]	2565330	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	84981	1			T16	1		T17	4		T18	10
all_pins[6]	transitions[0x0=>0x1]	84932	1			T16	1		T17	4		T18	7
all_pins[6]	transitions[0x1=>0x0]	157	1			T15	2		T16	4		T17	1
all_pins[7]	values[0x0]	2650105	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	206	1			T15	2		T16	4		T17	1
all_pins[7]	transitions[0x0=>0x1]	151	1			T15	2		T16	4		T18	5
all_pins[7]	transitions[0x1=>0x0]	225	1			T15	2		T16	5		T18	3