Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18844

1

T4

10

T7

241

T9

137

auto[1]

13127

1

T2

20

T7

88

T9

151

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3357	1			T9	20		T10	64		T30	26
values[1]	3687	1			T7	40		T9	77		T10	25
values[2]	4194	1			T2	20		T4	10		T7	40
values[3]	4609	1			T7	111		T9	20		T10	71
values[4]	4453	1			T9	20		T10	20		T14	45
values[5]	3911	1			T10	149		T215	4		T39	20
values[6]	4159	1			T7	23		T9	27		T30	50
values[7]	3601	1			T7	115		T9	20		T10	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4289	1			T7	46		T9	121		T10	71
values[1]	3971	1			T7	20		T9	60		T30	30
values[2]	3795	1			T4	10		T7	105		T9	20
values[3]	4107	1			T2	20		T7	85		T10	69
values[4]	3457	1			T9	40		T10	88		T47	14
values[5]	3613	1			T14	20		T22	29		T15	32
values[6]	4147	1			T7	73		T9	47		T10	64
values[7]	4592	1			T10	121		T30	20		T14	30

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	211	1			T30	7		T186	12		T21	21
auto[0]	values[0]	values[1]	254	1			T172	11		T36	13		T182	9
auto[0]	values[0]	values[2]	98	1			T200	16		T179	8		T216	11
auto[0]	values[0]	values[3]	379	1			T103	6		T64	20		T166	40
auto[0]	values[0]	values[4]	141	1			T9	15		T18	14		T203	14
auto[0]	values[0]	values[5]	202	1			T16	14		T210	10		T191	18
auto[0]	values[0]	values[6]	183	1			T10	9		T166	17		T217	19
auto[0]	values[0]	values[7]	387	1			T65	32		T168	8		T79	10
auto[0]	values[1]	values[0]	238	1			T7	13		T9	14		T26	14
auto[0]	values[1]	values[1]	376	1			T9	31		T186	15		T151	15
auto[0]	values[1]	values[2]	206	1			T9	13		T10	10		T15	6
auto[0]	values[1]	values[3]	159	1			T39	14		T218	4		T127	18
auto[0]	values[1]	values[4]	269	1			T22	8		T18	24		T76	10
auto[0]	values[1]	values[5]	226	1			T22	11		T120	18		T219	6
auto[0]	values[1]	values[6]	115	1			T7	5		T16	21		T76	11
auto[0]	values[1]	values[7]	307	1			T39	25		T124	4		T186	14
auto[0]	values[2]	values[0]	329	1			T9	10		T10	13		T30	11
auto[0]	values[2]	values[1]	257	1			T7	12		T9	14		T220	10
auto[0]	values[2]	values[2]	380	1			T4	10		T7	12		T10	13
auto[0]	values[2]	values[3]	371	1			T10	6		T39	14		T15	102
auto[0]	values[2]	values[4]	312	1			T10	58		T171	6		T76	11
auto[0]	values[2]	values[5]	311	1			T16	66		T21	11		T126	13
auto[0]	values[2]	values[6]	381	1			T221	18		T79	12		T166	22
auto[0]	values[2]	values[7]	230	1			T149	9		T172	8		T163	15
auto[0]	values[3]	values[0]	346	1			T7	16		T10	10		T149	9
auto[0]	values[3]	values[1]	222	1			T222	4		T151	14		T172	15
auto[0]	values[3]	values[2]	505	1			T7	78		T10	10		T30	15
auto[0]	values[3]	values[3]	270	1			T30	15		T186	8		T79	13
auto[0]	values[3]	values[4]	333	1			T9	5		T47	14		T223	4
auto[0]	values[3]	values[5]	240	1			T15	15		T211	18		T186	12
auto[0]	values[3]	values[6]	478	1			T15	92		T79	12		T224	94
auto[0]	values[3]	values[7]	337	1			T10	7		T82	8		T16	10
auto[0]	values[4]	values[0]	375	1			T9	7		T10	19		T15	15
auto[0]	values[4]	values[1]	218	1			T22	10		T33	16		T79	13
auto[0]	values[4]	values[2]	295	1			T28	2		T18	11		T204	20
auto[0]	values[4]	values[3]	191	1			T149	12		T225	2		T76	14
auto[0]	values[4]	values[4]	216	1			T203	7		T68	14		T226	16
auto[0]	values[4]	values[5]	219	1			T14	15		T165	10		T186	9
auto[0]	values[4]	values[6]	609	1			T14	12		T22	184		T24	6
auto[0]	values[4]	values[7]	610	1			T186	10		T65	10		T163	11
auto[0]	values[5]	values[0]	355	1			T227	12		T172	14		T166	15
auto[0]	values[5]	values[1]	212	1			T39	9		T149	14		T208	7
auto[0]	values[5]	values[2]	141	1			T215	4		T228	8		T126	12
auto[0]	values[5]	values[3]	364	1			T10	38		T15	102		T229	8
auto[0]	values[5]	values[4]	566	1			T191	28		T166	6		T217	10
auto[0]	values[5]	values[5]	457	1			T18	12		T77	22		T191	131
auto[0]	values[5]	values[6]	174	1			T18	11		T230	2		T200	7
auto[0]	values[5]	values[7]	304	1			T10	29		T15	13		T231	8
auto[0]	values[6]	values[0]	313	1			T22	43		T119	10		T232	47
auto[0]	values[6]	values[1]	324	1			T30	13		T22	62		T76	17
auto[0]	values[6]	values[2]	306	1			T18	7		T21	20		T203	12
auto[0]	values[6]	values[3]	218	1			T22	13		T16	26		T165	25
auto[0]	values[6]	values[4]	154	1			T233	2		T203	11		T217	31
auto[0]	values[6]	values[5]	253	1			T16	6		T217	8		T68	49
auto[0]	values[6]	values[6]	541	1			T7	20		T9	19		T22	27
auto[0]	values[6]	values[7]	225	1			T30	11		T39	15		T186	11
auto[0]	values[7]	values[0]	204	1			T39	12		T149	10		T126	12
auto[0]	values[7]	values[1]	389	1			T18	8		T207	35		T234	15
auto[0]	values[7]	values[2]	204	1			T18	11		T151	6		T203	13
auto[0]	values[7]	values[3]	392	1			T7	73		T16	8		T126	15
auto[0]	values[7]	values[4]	129	1			T10	12		T14	16		T151	12
auto[0]	values[7]	values[5]	222	1			T162	16		T201	17		T42	43
auto[0]	values[7]	values[6]	183	1			T7	12		T9	9		T14	10
auto[0]	values[7]	values[7]	428	1			T14	13		T101	8		T18	15
auto[1]	values[0]	values[0]	149	1			T30	19		T186	8		T21	6
auto[1]	values[0]	values[1]	276	1			T172	9		T36	37		T182	11
auto[1]	values[0]	values[2]	85	1			T200	6		T179	24		T216	9
auto[1]	values[0]	values[3]	175	1			T166	8		T217	14		T68	9
auto[1]	values[0]	values[4]	115	1			T9	5		T18	6		T203	6
auto[1]	values[0]	values[5]	155	1			T16	17		T191	12		T203	12
auto[1]	values[0]	values[6]	230	1			T10	55		T235	4		T166	7
auto[1]	values[0]	values[7]	317	1			T65	9		T168	12		T79	10
auto[1]	values[1]	values[0]	443	1			T7	7		T9	6		T18	10
auto[1]	values[1]	values[1]	146	1			T9	6		T186	5		T151	5
auto[1]	values[1]	values[2]	212	1			T9	7		T10	15		T15	14
auto[1]	values[1]	values[3]	132	1			T39	6		T127	6		T236	10
auto[1]	values[1]	values[4]	195	1			T22	12		T18	22		T76	10
auto[1]	values[1]	values[5]	249	1			T22	18		T76	8		T217	30
auto[1]	values[1]	values[6]	130	1			T7	15		T16	10		T76	9
auto[1]	values[1]	values[7]	284	1			T39	15		T186	7		T126	14
auto[1]	values[2]	values[0]	279	1			T9	71		T10	7		T30	16
auto[1]	values[2]	values[1]	178	1			T7	8		T9	9		T84	22
auto[1]	values[2]	values[2]	297	1			T7	8		T10	7		T165	7
auto[1]	values[2]	values[3]	199	1			T2	20		T10	15		T39	6
auto[1]	values[2]	values[4]	196	1			T10	10		T76	9		T198	4
auto[1]	values[2]	values[5]	148	1			T16	39		T21	11		T126	7
auto[1]	values[2]	values[6]	156	1			T79	8		T166	5		T127	7
auto[1]	values[2]	values[7]	170	1			T149	11		T172	12		T163	5
auto[1]	values[3]	values[0]	333	1			T7	10		T10	21		T149	11
auto[1]	values[3]	values[1]	196	1			T151	12		T172	5		T201	13
auto[1]	values[3]	values[2]	180	1			T7	7		T10	10		T30	9
auto[1]	values[3]	values[3]	340	1			T30	5		T186	22		T79	7
auto[1]	values[3]	values[4]	268	1			T9	15		T203	7		T217	9
auto[1]	values[3]	values[5]	271	1			T15	17		T186	15		T126	9
auto[1]	values[3]	values[6]	122	1			T15	14		T79	8		T201	7
auto[1]	values[3]	values[7]	168	1			T10	13		T16	10		T76	7
auto[1]	values[4]	values[0]	179	1			T9	13		T10	1		T15	5
auto[1]	values[4]	values[1]	199	1			T22	10		T79	7		T166	25
auto[1]	values[4]	values[2]	313	1			T18	9		T237	26		T79	5
auto[1]	values[4]	values[3]	243	1			T149	15		T76	6		T151	6
auto[1]	values[4]	values[4]	127	1			T203	13		T68	6		T238	8
auto[1]	values[4]	values[5]	120	1			T14	5		T165	10		T186	11
auto[1]	values[4]	values[6]	239	1			T14	13		T22	6		T15	7
auto[1]	values[4]	values[7]	300	1			T186	17		T65	10		T163	9
auto[1]	values[5]	values[0]	176	1			T172	6		T166	8		T239	20
auto[1]	values[5]	values[1]	106	1			T39	11		T149	11		T208	13
auto[1]	values[5]	values[2]	150	1			T126	8		T166	5		T163	13
auto[1]	values[5]	values[3]	215	1			T10	10		T15	12		T127	8
auto[1]	values[5]	values[4]	177	1			T191	17		T166	37		T217	40
auto[1]	values[5]	values[5]	202	1			T18	12		T191	5		T240	6
auto[1]	values[5]	values[6]	130	1			T18	15		T200	13		T127	8
auto[1]	values[5]	values[7]	182	1			T10	72		T15	7		T21	8
auto[1]	values[6]	values[0]	216	1			T22	7		T187	16		T173	83
auto[1]	values[6]	values[1]	399	1			T30	17		T22	9		T83	18
auto[1]	values[6]	values[2]	244	1			T18	13		T21	7		T203	8
auto[1]	values[6]	values[3]	220	1			T22	7		T16	25		T165	6
auto[1]	values[6]	values[4]	138	1			T203	9		T217	3		T68	10
auto[1]	values[6]	values[5]	162	1			T16	14		T217	12		T68	58
auto[1]	values[6]	values[6]	299	1			T7	3		T9	8		T22	13
auto[1]	values[6]	values[7]	147	1			T30	9		T39	5		T186	12
auto[1]	values[7]	values[0]	143	1			T39	8		T149	14		T126	8
auto[1]	values[7]	values[1]	219	1			T18	12		T207	10		T234	5
auto[1]	values[7]	values[2]	179	1			T18	11		T151	14		T203	7
auto[1]	values[7]	values[3]	239	1			T7	12		T16	27		T126	9
auto[1]	values[7]	values[4]	121	1			T10	8		T14	8		T151	11
auto[1]	values[7]	values[5]	176	1			T201	15		T42	5		T181	13
auto[1]	values[7]	values[6]	177	1			T7	18		T9	11		T14	11
auto[1]	values[7]	values[7]	196	1			T14	17		T18	5		T21	6