Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	439	1			T4	4		T7	4		T9	4
auto[ReadAddrCrossIntoMailbox]	269	1			T7	2		T9	3		T10	5
auto[ReadAddrCrossOutOfMailbox]	333	1			T7	2		T9	2		T10	9
auto[ReadAddrCrossAllMailbox]	263	1			T7	1		T9	5		T30	1
auto[ReadAddrOutsideMailbox]	3689	1			T2	4		T7	26		T9	32

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2490

1

T2

2

T4

2

T7

17

auto[1]

2503

1

T2

2

T4

2

T7

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	812	1			T7	5		T9	8		T10	8
read_ops[0x0b]	889	1			T7	8		T9	6		T10	15
read_ops[0x3b]	843	1			T7	5		T9	8		T10	9
read_ops[0x6b]	832	1			T7	7		T9	5		T10	5
read_ops[0xbb]	836	1			T2	4		T4	4		T7	7
read_ops[0xeb]	781	1			T7	3		T9	10		T10	10

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T30	1		T22	2		T149	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T16	1		T168	1		T166	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T9	1		T186	1		T228	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T7	2		T228	1		T79	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T9	1		T10	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T186	1		T62	2		T210	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T149	2		T165	1		T18	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T186	2		T62	2		T221	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T7	1		T9	3		T10	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T7	2		T9	3		T10	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T47	1		T22	1		T219	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T7	1		T47	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T14	1		T186	1		T219	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T22	1		T18	1		T219	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T7	1		T149	2		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T15	1		T76	1		T126	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T9	1		T149	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	32	1			T9	2		T165	1		T18	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T7	1		T10	11		T30	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	348	1			T7	5		T9	3		T10	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T10	1		T30	1		T47	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T9	1		T47	2		T14	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T10	4		T18	1		T172	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T9	1		T151	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T9	1		T10	1		T16	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T39	1		T16	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T18	1		T219	1		T68	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T219	1		T191	1		T208	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T7	5		T9	4		T10	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T9	1		T10	2		T30	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T47	1		T126	1		T151	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T47	1		T22	1		T16	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T18	1		T65	1		T151	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T16	1		T76	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T22	1		T228	1		T126	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T7	1		T30	1		T15	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T30	1		T18	1		T79	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T7	1		T16	1		T163	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T7	2		T9	5		T10	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T7	3		T10	2		T14	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T4	2		T7	1		T9	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T4	2		T7	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T9	1		T22	1		T15	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T149	1		T241	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T10	3		T22	1		T168	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T10	1		T22	1		T16	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T9	1		T39	1		T16	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T16	1		T228	1		T62	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T2	2		T7	4		T9	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T2	2		T7	1		T9	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T24	1		T221	1		T126	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T7	1		T9	1		T24	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T10	1		T16	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T22	1		T15	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T10	3		T16	1		T76	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T14	1		T39	1		T228	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T221	1		T217	1		T163	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T9	1		T76	1		T21	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T7	2		T9	4		T10	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T9	4		T10	1		T30	2