Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3624	1			T9	37		T10	108		T14	30
values[1]	4326	1			T7	20		T47	14		T14	41
values[2]	3739	1			T7	43		T9	43		T10	70
values[3]	4473	1			T9	60		T10	84		T30	24
values[4]	3861	1			T4	10		T7	26		T10	48
values[5]	4917	1			T2	20		T7	240		T9	27
values[6]	3961	1			T9	121		T10	61		T30	56
values[7]	3070	1			T10	56		T30	47		T82	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4126	1			T9	27		T10	20		T30	20
values[1]	4461	1			T7	23		T9	81		T10	71
values[2]	3697	1			T2	20		T4	10		T7	30
values[3]	3902	1			T10	45		T30	27		T14	69
values[4]	3827	1			T9	20		T10	68		T22	20
values[5]	4575	1			T7	105		T9	20		T10	20
values[6]	3480	1			T7	40		T9	20		T10	85
values[7]	3903	1			T7	131		T9	37		T10	76

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31176

1

T2

18

T4

10

T7

322

auto[1]

795

1

T2

2

T7

7

T9

13

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	451	1			T10	20		T187	23		T242	2
auto[0]	values[0]	values[1]	416	1			T62	20		T151	20		T203	16
auto[0]	values[0]	values[2]	393	1			T101	8		T76	17		T217	20
auto[0]	values[0]	values[3]	415	1			T21	27		T163	23		T239	19
auto[0]	values[0]	values[4]	493	1			T10	66		T22	20		T33	16
auto[0]	values[0]	values[5]	521	1			T14	28		T186	23		T76	19
auto[0]	values[0]	values[6]	435	1			T15	31		T190	19		T21	20
auto[0]	values[0]	values[7]	389	1			T9	36		T10	17		T39	15
auto[0]	values[1]	values[0]	401	1			T14	20		T126	19		T79	20
auto[0]	values[1]	values[1]	504	1			T47	14		T39	16		T126	19
auto[0]	values[1]	values[2]	253	1			T186	20		T18	21		T172	20
auto[0]	values[1]	values[3]	627	1			T14	19		T16	35		T165	19
auto[0]	values[1]	values[4]	697	1			T16	27		T151	20		T172	19
auto[0]	values[1]	values[5]	884	1			T7	19		T171	6		T84	22
auto[0]	values[1]	values[6]	247	1			T76	20		T77	22		T172	18
auto[0]	values[1]	values[7]	603	1			T21	20		T151	22		T243	4
auto[0]	values[2]	values[0]	343	1			T126	20		T151	22		T178	20
auto[0]	values[2]	values[1]	628	1			T7	22		T15	37		T186	26
auto[0]	values[2]	values[2]	407	1			T9	21		T10	25		T126	24
auto[0]	values[2]	values[3]	432	1			T10	44		T208	20		T244	16
auto[0]	values[2]	values[4]	441	1			T16	30		T235	4		T168	20
auto[0]	values[2]	values[5]	574	1			T9	20		T16	20		T165	30
auto[0]	values[2]	values[6]	331	1			T7	20		T58	18		T230	2
auto[0]	values[2]	values[7]	482	1			T124	4		T231	8		T172	15
auto[0]	values[3]	values[0]	695	1			T193	4		T220	10		T223	4
auto[0]	values[3]	values[1]	565	1			T237	22		T151	20		T203	19
auto[0]	values[3]	values[2]	544	1			T9	38		T10	20		T15	20
auto[0]	values[3]	values[3]	587	1			T14	24		T16	30		T163	20
auto[0]	values[3]	values[4]	374	1			T39	20		T15	36		T186	20
auto[0]	values[3]	values[5]	748	1			T22	91		T21	21		T126	21
auto[0]	values[3]	values[6]	406	1			T9	18		T10	63		T24	6
auto[0]	values[3]	values[7]	447	1			T30	21		T39	20		T15	20
auto[0]	values[4]	values[0]	759	1			T22	235		T16	30		T186	27
auto[0]	values[4]	values[1]	375	1			T26	14		T16	24		T219	6
auto[0]	values[4]	values[2]	401	1			T4	10		T10	46		T83	18
auto[0]	values[4]	values[3]	387	1			T151	23		T172	20		T189	100
auto[0]	values[4]	values[4]	584	1			T15	112		T16	20		T18	20
auto[0]	values[4]	values[5]	326	1			T22	50		T167	6		T245	14
auto[0]	values[4]	values[6]	547	1			T79	18		T68	31		T208	20
auto[0]	values[4]	values[7]	397	1			T7	26		T203	45		T217	18
auto[0]	values[5]	values[0]	396	1			T9	24		T15	67		T169	34
auto[0]	values[5]	values[1]	921	1			T10	51		T30	20		T15	108
auto[0]	values[5]	values[2]	680	1			T2	18		T7	30		T103	6
auto[0]	values[5]	values[3]	590	1			T14	25		T16	20		T18	17
auto[0]	values[5]	values[4]	427	1			T39	16		T120	18		T191	72
auto[0]	values[5]	values[5]	548	1			T7	83		T15	20		T16	34
auto[0]	values[5]	values[6]	618	1			T7	19		T22	20		T149	20
auto[0]	values[5]	values[7]	625	1			T7	103		T21	19		T79	20
auto[0]	values[6]	values[0]	521	1			T39	20		T191	74		T166	24
auto[0]	values[6]	values[1]	518	1			T9	78		T10	20		T30	28
auto[0]	values[6]	values[2]	657	1			T9	20		T30	26		T186	22
auto[0]	values[6]	values[3]	335	1			T22	19		T18	18		T210	10
auto[0]	values[6]	values[4]	301	1			T9	20		T149	25		T65	40
auto[0]	values[6]	values[5]	519	1			T10	20		T28	2		T39	20
auto[0]	values[6]	values[6]	456	1			T10	20		T16	20		T246	6
auto[0]	values[6]	values[7]	566	1			T16	50		T211	18		T186	21
auto[0]	values[7]	values[0]	475	1			T30	20		T215	4		T186	30
auto[0]	values[7]	values[1]	422	1			T18	20		T76	20		T203	24
auto[0]	values[7]	values[2]	267	1			T18	24		T79	20		T166	20
auto[0]	values[7]	values[3]	421	1			T30	26		T149	41		T172	20
auto[0]	values[7]	values[4]	425	1			T168	20		T166	22		T68	43
auto[0]	values[7]	values[5]	360	1			T126	20		T172	18		T217	18
auto[0]	values[7]	values[6]	342	1			T225	2		T207	22		T201	66
auto[0]	values[7]	values[7]	277	1			T10	56		T82	8		T227	12
auto[1]	values[0]	values[0]	12	1			T187	2		T236	1		T247	1
auto[1]	values[0]	values[1]	15	1			T151	4		T203	4		T42	1
auto[1]	values[0]	values[2]	16	1			T76	3		T187	3		T248	4
auto[1]	values[0]	values[3]	8	1			T239	1		T181	2		T174	1
auto[1]	values[0]	values[4]	18	1			T10	2		T76	2		T79	2
auto[1]	values[0]	values[5]	11	1			T14	2		T76	1		T79	1
auto[1]	values[0]	values[6]	15	1			T15	1		T190	1		T21	3
auto[1]	values[0]	values[7]	16	1			T9	1		T10	3		T39	5
auto[1]	values[1]	values[0]	10	1			T14	1		T126	1		T147	1
auto[1]	values[1]	values[1]	17	1			T39	4		T126	2		T68	1
auto[1]	values[1]	values[2]	6	1			T18	2		T200	1		T44	1
auto[1]	values[1]	values[3]	15	1			T14	1		T165	1		T207	1
auto[1]	values[1]	values[4]	18	1			T172	1		T173	1		T189	2
auto[1]	values[1]	values[5]	16	1			T7	1		T203	1		T217	2
auto[1]	values[1]	values[6]	8	1			T172	2		T163	1		T249	2
auto[1]	values[1]	values[7]	20	1			T173	3		T201	1		T250	1
auto[1]	values[2]	values[0]	3	1			T151	1		T251	1		T252	1
auto[1]	values[2]	values[1]	13	1			T7	1		T186	1		T163	1
auto[1]	values[2]	values[2]	12	1			T9	2		T253	2		T147	2
auto[1]	values[2]	values[3]	20	1			T10	1		T244	4		T209	4
auto[1]	values[2]	values[4]	12	1			T16	1		T207	1		T209	2
auto[1]	values[2]	values[5]	23	1			T165	1		T186	2		T151	5
auto[1]	values[2]	values[6]	4	1			T217	2		T254	1		T255	1
auto[1]	values[2]	values[7]	14	1			T172	5		T166	1		T42	2
auto[1]	values[3]	values[0]	11	1			T191	2		T250	1		T256	3
auto[1]	values[3]	values[1]	19	1			T237	4		T203	1		T173	2
auto[1]	values[3]	values[2]	13	1			T9	2		T173	2		T239	1
auto[1]	values[3]	values[3]	10	1			T16	1		T207	1		T216	2
auto[1]	values[3]	values[4]	13	1			T15	2		T127	2		T181	3
auto[1]	values[3]	values[5]	10	1			T21	1		T191	1		T68	1
auto[1]	values[3]	values[6]	15	1			T9	2		T10	1		T76	2
auto[1]	values[3]	values[7]	16	1			T30	3		T201	2		T257	2
auto[1]	values[4]	values[0]	20	1			T22	4		T16	1		T191	1
auto[1]	values[4]	values[1]	17	1			T16	3		T76	4		T238	4
auto[1]	values[4]	values[2]	8	1			T10	2		T191	1		T127	3
auto[1]	values[4]	values[3]	9	1			T147	1		T258	3		T129	1
auto[1]	values[4]	values[4]	4	1			T15	2		T259	1		T260	1
auto[1]	values[4]	values[5]	5	1			T201	2		T175	2		T249	1
auto[1]	values[4]	values[6]	13	1			T79	2		T68	2		T164	2
auto[1]	values[4]	values[7]	9	1			T203	1		T217	2		T261	1
auto[1]	values[5]	values[0]	14	1			T9	3		T15	2		T68	7
auto[1]	values[5]	values[1]	6	1			T15	1		T186	1		T252	1
auto[1]	values[5]	values[2]	20	1			T2	2		T149	1		T18	4
auto[1]	values[5]	values[3]	16	1			T18	5		T79	2		T198	1
auto[1]	values[5]	values[4]	10	1			T39	4		T68	4		T46	2
auto[1]	values[5]	values[5]	14	1			T7	2		T166	2		T181	1
auto[1]	values[5]	values[6]	18	1			T7	1		T18	1		T191	1
auto[1]	values[5]	values[7]	14	1			T7	2		T21	1		T214	3
auto[1]	values[6]	values[0]	4	1			T166	1		T182	1		T175	1
auto[1]	values[6]	values[1]	12	1			T9	3		T30	2		T166	3
auto[1]	values[6]	values[2]	18	1			T186	3		T170	3		T164	2
auto[1]	values[6]	values[3]	12	1			T22	1		T18	2		T170	2
auto[1]	values[6]	values[4]	2	1			T65	1		T209	1		-	-
auto[1]	values[6]	values[5]	8	1			T173	1		T239	2		T209	2
auto[1]	values[6]	values[6]	18	1			T10	1		T217	3		T173	4
auto[1]	values[6]	values[7]	14	1			T16	1		T186	2		T198	7
auto[1]	values[7]	values[0]	11	1			T164	2		T262	1		T263	1
auto[1]	values[7]	values[1]	13	1			T181	1		T216	1		T182	1
auto[1]	values[7]	values[2]	2	1			T216	1		T43	1		-	-
auto[1]	values[7]	values[3]	18	1			T30	1		T149	3		T200	2
auto[1]	values[7]	values[4]	8	1			T168	1		T166	1		T264	1
auto[1]	values[7]	values[5]	8	1			T172	2		T217	2		T265	1
auto[1]	values[7]	values[6]	7	1			T42	2		T266	2		T256	1
auto[1]	values[7]	values[7]	14	1			T79	2		T151	3		T267	3