Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1928

1

T1

9

T6

3

T7

4

auto[1]

1750

1

T1

11

T6

2

T7

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2034

1

T7

9

T10

2

T11

9

auto[1]

1644

1

T1

20

T6

5

T10

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2887

1

T1

20

T6

5

T7

5

auto[1]

791

1

T7

4

T11

3

T13

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	732	1			T1	4		T6	1		T7	2
valid[1]	752	1			T1	3		T11	3		T13	1
valid[2]	762	1			T1	5		T6	2		T7	2
valid[3]	696	1			T1	4		T6	1		T7	4
valid[4]	736	1			T1	4		T6	1		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	124	1			T29	2		T14	4		T186	1
auto[0]	auto[0]	valid[0]	auto[1]	180	1			T1	2		T75	1		T121	2
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T11	1		T13	1		T29	1
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T1	1		T11	1		T75	3
auto[0]	auto[0]	valid[2]	auto[0]	147	1			T7	1		T10	1		T13	1
auto[0]	auto[0]	valid[2]	auto[1]	167	1			T1	1		T6	1		T11	1
auto[0]	auto[0]	valid[3]	auto[0]	114	1			T7	1		T30	1		T14	1
auto[0]	auto[0]	valid[3]	auto[1]	166	1			T1	2		T6	1		T75	2
auto[0]	auto[0]	valid[4]	auto[0]	140	1			T10	1		T11	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	169	1			T1	3		T6	1		T13	1
auto[0]	auto[1]	valid[0]	auto[0]	110	1			T7	1		T11	2		T13	1
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T1	2		T6	1		T11	1
auto[0]	auto[1]	valid[1]	auto[0]	121	1			T14	1		T16	1		T18	3
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T1	2		T11	1		T22	1
auto[0]	auto[1]	valid[2]	auto[0]	116	1			T14	2		T25	2		T16	1
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T1	4		T6	1		T11	1
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T7	1		T30	1		T14	2
auto[0]	auto[1]	valid[3]	auto[1]	132	1			T1	2		T10	1		T11	1
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T7	1		T11	2		T13	1
auto[0]	auto[1]	valid[4]	auto[1]	143	1			T1	1		T11	1		T75	1
auto[1]	auto[0]	valid[0]	auto[0]	87	1			T7	1		T11	1		T29	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T14	2		T25	1		T66	1
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T7	1		T11	1		T14	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T13	1		T30	1		T14	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T13	1		T29	1		T30	1
auto[1]	auto[1]	valid[0]	auto[0]	63	1			T25	1		T186	1		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	62	1			T14	2		T25	1		T63	1
auto[1]	auto[1]	valid[2]	auto[0]	86	1			T11	1		T25	1		T18	2
auto[1]	auto[1]	valid[3]	auto[0]	81	1			T7	2		T14	1		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	92	1			T14	1		T27	1		T186	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal