Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51446

1

T7

161

T10

55

T11

381

auto[1]

17871

1

T1

272

T6

5

T10

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50495

1

T1

272

T6

5

T7

102

auto[1]

18822

1

T7

59

T10

17

T11

180

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35418	1			T1	133		T6	5		T7	71
others[1]	5958	1			T1	28		T7	24		T10	3
others[2]	5920	1			T1	21		T7	13		T10	2
others[3]	6711	1			T1	25		T7	16		T10	9
interest[1]	3754	1			T1	14		T7	8		T10	3
interest[4]	23183	1			T1	85		T6	5		T7	44
interest[64]	11556	1			T1	51		T7	29		T10	12

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16576	1			T7	47		T10	20		T11	98
auto[0]	auto[0]	others[1]	2821	1			T7	16		T10	2		T11	17
auto[0]	auto[0]	others[2]	2782	1			T7	9		T10	1		T11	23
auto[0]	auto[0]	others[3]	3199	1			T7	8		T10	5		T11	21
auto[0]	auto[0]	interest[1]	1817	1			T7	5		T10	2		T11	4
auto[0]	auto[0]	interest[4]	10757	1			T7	28		T10	17		T11	61
auto[0]	auto[0]	interest[64]	5429	1			T7	17		T10	8		T11	38
auto[0]	auto[1]	others[0]	9237	1			T1	133		T6	5		T10	2
auto[0]	auto[1]	others[1]	1454	1			T1	28		T11	7		T13	2
auto[0]	auto[1]	others[2]	1520	1			T1	21		T10	1		T11	10
auto[0]	auto[1]	others[3]	1699	1			T1	25		T11	4		T13	6
auto[0]	auto[1]	interest[1]	966	1			T1	14		T10	1		T11	6
auto[0]	auto[1]	interest[4]	6119	1			T1	85		T6	5		T10	2
auto[0]	auto[1]	interest[64]	2995	1			T1	51		T11	17		T13	3
auto[1]	auto[0]	others[0]	9605	1			T7	24		T10	8		T11	101
auto[1]	auto[0]	others[1]	1683	1			T7	8		T10	1		T11	17
auto[1]	auto[0]	others[2]	1618	1			T7	4		T11	24		T13	5
auto[1]	auto[0]	others[3]	1813	1			T7	8		T10	4		T11	14
auto[1]	auto[0]	interest[1]	971	1			T7	3		T11	6		T13	2
auto[1]	auto[0]	interest[4]	6307	1			T7	16		T10	2		T11	59
auto[1]	auto[0]	interest[64]	3132	1			T7	12		T10	4		T11	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal