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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T89 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1422099272 Jul 30 05:26:24 PM PDT 24 Jul 30 05:26:29 PM PDT 24 877163209 ps
T1025 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3484948575 Jul 30 05:26:15 PM PDT 24 Jul 30 05:26:23 PM PDT 24 432615944 ps
T1026 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3268963195 Jul 30 05:26:25 PM PDT 24 Jul 30 05:26:26 PM PDT 24 14987234 ps
T1027 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.192703016 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:33 PM PDT 24 91776816 ps
T1028 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2389614631 Jul 30 05:26:06 PM PDT 24 Jul 30 05:26:06 PM PDT 24 45154948 ps
T156 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.706869697 Jul 30 05:26:20 PM PDT 24 Jul 30 05:26:33 PM PDT 24 2564832077 ps
T1029 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4206024131 Jul 30 05:26:30 PM PDT 24 Jul 30 05:26:31 PM PDT 24 17503472 ps
T72 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.86581923 Jul 30 05:26:15 PM PDT 24 Jul 30 05:26:16 PM PDT 24 135760165 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.986557595 Jul 30 05:26:16 PM PDT 24 Jul 30 05:26:44 PM PDT 24 1851309892 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2704371270 Jul 30 05:26:16 PM PDT 24 Jul 30 05:26:18 PM PDT 24 54014949 ps
T155 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3994652534 Jul 30 05:26:27 PM PDT 24 Jul 30 05:26:42 PM PDT 24 1090129976 ps
T1030 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2953055357 Jul 30 05:26:17 PM PDT 24 Jul 30 05:26:21 PM PDT 24 99469915 ps
T1031 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2747608292 Jul 30 05:26:47 PM PDT 24 Jul 30 05:26:48 PM PDT 24 19016572 ps
T73 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.671156027 Jul 30 05:26:11 PM PDT 24 Jul 30 05:26:13 PM PDT 24 21884631 ps
T1032 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2715997378 Jul 30 05:26:29 PM PDT 24 Jul 30 05:26:30 PM PDT 24 13924599 ps
T1033 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.247668404 Jul 30 05:26:51 PM PDT 24 Jul 30 05:26:52 PM PDT 24 35748449 ps
T110 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2211187011 Jul 30 05:26:14 PM PDT 24 Jul 30 05:26:17 PM PDT 24 51041324 ps
T1034 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.48999930 Jul 30 05:26:18 PM PDT 24 Jul 30 05:26:19 PM PDT 24 29407908 ps
T1035 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2247082486 Jul 30 05:26:40 PM PDT 24 Jul 30 05:26:40 PM PDT 24 40854372 ps
T88 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2196390347 Jul 30 05:26:25 PM PDT 24 Jul 30 05:26:30 PM PDT 24 425525100 ps
T1036 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2826434331 Jul 30 05:26:43 PM PDT 24 Jul 30 05:26:43 PM PDT 24 46482901 ps
T111 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2597893375 Jul 30 05:26:15 PM PDT 24 Jul 30 05:26:22 PM PDT 24 1270929793 ps
T1037 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.558450595 Jul 30 05:26:43 PM PDT 24 Jul 30 05:26:44 PM PDT 24 43421102 ps
T1038 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3615724269 Jul 30 05:26:38 PM PDT 24 Jul 30 05:26:42 PM PDT 24 204013641 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2315046154 Jul 30 05:26:12 PM PDT 24 Jul 30 05:26:13 PM PDT 24 14335991 ps
T92 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3796359061 Jul 30 05:26:20 PM PDT 24 Jul 30 05:26:24 PM PDT 24 120631623 ps
T1040 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2986215300 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:33 PM PDT 24 19198351 ps
T1041 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3880327665 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:47 PM PDT 24 13052568 ps
T153 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2808731557 Jul 30 05:26:22 PM PDT 24 Jul 30 05:26:40 PM PDT 24 726188452 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2936686188 Jul 30 05:26:37 PM PDT 24 Jul 30 05:26:39 PM PDT 24 137360051 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1967887840 Jul 30 05:26:19 PM PDT 24 Jul 30 05:26:26 PM PDT 24 478636989 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2371089224 Jul 30 05:26:24 PM PDT 24 Jul 30 05:26:28 PM PDT 24 128434809 ps
T1045 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3156314840 Jul 30 05:26:44 PM PDT 24 Jul 30 05:26:45 PM PDT 24 66250542 ps
T1046 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.603549470 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:47 PM PDT 24 72408769 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1425806846 Jul 30 05:26:44 PM PDT 24 Jul 30 05:26:45 PM PDT 24 13321213 ps
T1048 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2782087517 Jul 30 05:26:13 PM PDT 24 Jul 30 05:26:22 PM PDT 24 397507354 ps
T1049 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.32444928 Jul 30 05:26:28 PM PDT 24 Jul 30 05:26:30 PM PDT 24 55102312 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2159981670 Jul 30 05:26:34 PM PDT 24 Jul 30 05:26:37 PM PDT 24 544565618 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.413223341 Jul 30 05:26:14 PM PDT 24 Jul 30 05:26:17 PM PDT 24 92512422 ps
T95 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.672945181 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:34 PM PDT 24 133778809 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1980613483 Jul 30 05:26:15 PM PDT 24 Jul 30 05:26:16 PM PDT 24 42797396 ps
T90 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2458440093 Jul 30 05:26:12 PM PDT 24 Jul 30 05:26:17 PM PDT 24 87198689 ps
T94 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2234460715 Jul 30 05:26:06 PM PDT 24 Jul 30 05:26:10 PM PDT 24 65254997 ps
T1052 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3667688802 Jul 30 05:26:45 PM PDT 24 Jul 30 05:26:46 PM PDT 24 48867140 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1184082555 Jul 30 05:26:20 PM PDT 24 Jul 30 05:26:23 PM PDT 24 108193341 ps
T115 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3087999798 Jul 30 05:26:18 PM PDT 24 Jul 30 05:26:19 PM PDT 24 129436436 ps
T1054 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1707129369 Jul 30 05:26:30 PM PDT 24 Jul 30 05:26:33 PM PDT 24 52825190 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1830872314 Jul 30 05:26:14 PM PDT 24 Jul 30 05:26:25 PM PDT 24 191659619 ps
T1056 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3065098276 Jul 30 05:26:54 PM PDT 24 Jul 30 05:27:16 PM PDT 24 2223431473 ps
T1057 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3294244964 Jul 30 05:26:31 PM PDT 24 Jul 30 05:26:34 PM PDT 24 85573626 ps
T1058 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4048481958 Jul 30 05:26:26 PM PDT 24 Jul 30 05:26:29 PM PDT 24 203359397 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3006960338 Jul 30 05:26:17 PM PDT 24 Jul 30 05:26:18 PM PDT 24 46037336 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.296715739 Jul 30 05:26:12 PM PDT 24 Jul 30 05:26:14 PM PDT 24 29306689 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3026541693 Jul 30 05:26:22 PM PDT 24 Jul 30 05:26:31 PM PDT 24 444773630 ps
T1062 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2744620151 Jul 30 05:26:28 PM PDT 24 Jul 30 05:26:29 PM PDT 24 56918390 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3112652907 Jul 30 05:26:13 PM PDT 24 Jul 30 05:26:15 PM PDT 24 46109794 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3254210084 Jul 30 05:26:11 PM PDT 24 Jul 30 05:26:13 PM PDT 24 125026822 ps
T1063 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1650132241 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:32 PM PDT 24 14639585 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.732128595 Jul 30 05:26:16 PM PDT 24 Jul 30 05:26:18 PM PDT 24 221528162 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2509272006 Jul 30 05:26:11 PM PDT 24 Jul 30 05:26:27 PM PDT 24 604812875 ps
T1066 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.342481802 Jul 30 05:26:43 PM PDT 24 Jul 30 05:26:44 PM PDT 24 20447882 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2972433361 Jul 30 05:26:13 PM PDT 24 Jul 30 05:26:17 PM PDT 24 383677069 ps
T1068 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2424842224 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:47 PM PDT 24 35194436 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3964673878 Jul 30 05:26:26 PM PDT 24 Jul 30 05:26:29 PM PDT 24 834198791 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3199147397 Jul 30 05:26:21 PM PDT 24 Jul 30 05:26:26 PM PDT 24 261147179 ps
T1071 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.598766356 Jul 30 05:26:23 PM PDT 24 Jul 30 05:26:25 PM PDT 24 326289080 ps
T1072 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4293369740 Jul 30 05:26:44 PM PDT 24 Jul 30 05:26:45 PM PDT 24 23635605 ps
T1073 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.955081047 Jul 30 05:26:19 PM PDT 24 Jul 30 05:26:19 PM PDT 24 15116709 ps
T1074 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2391300303 Jul 30 05:26:37 PM PDT 24 Jul 30 05:26:41 PM PDT 24 227135265 ps
T1075 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.281079979 Jul 30 05:26:58 PM PDT 24 Jul 30 05:26:59 PM PDT 24 52583818 ps
T1076 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.22159084 Jul 30 05:26:44 PM PDT 24 Jul 30 05:26:44 PM PDT 24 16313051 ps
T113 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.990161894 Jul 30 05:26:34 PM PDT 24 Jul 30 05:26:36 PM PDT 24 38953061 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.819122927 Jul 30 05:26:15 PM PDT 24 Jul 30 05:26:33 PM PDT 24 710545693 ps
T114 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2984490671 Jul 30 05:26:20 PM PDT 24 Jul 30 05:26:22 PM PDT 24 147428432 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4022959828 Jul 30 05:26:22 PM PDT 24 Jul 30 05:26:23 PM PDT 24 143113754 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1079797662 Jul 30 05:26:20 PM PDT 24 Jul 30 05:26:21 PM PDT 24 37521717 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.568648291 Jul 30 05:26:27 PM PDT 24 Jul 30 05:26:30 PM PDT 24 210506869 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2123912807 Jul 30 05:26:39 PM PDT 24 Jul 30 05:26:41 PM PDT 24 395183094 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1757906273 Jul 30 05:26:48 PM PDT 24 Jul 30 05:27:11 PM PDT 24 3831892500 ps
T1083 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1369839306 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:36 PM PDT 24 189008581 ps
T1084 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2540207802 Jul 30 05:26:37 PM PDT 24 Jul 30 05:26:41 PM PDT 24 305918699 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2122811533 Jul 30 05:26:19 PM PDT 24 Jul 30 05:26:22 PM PDT 24 53784989 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2425766188 Jul 30 05:26:31 PM PDT 24 Jul 30 05:26:34 PM PDT 24 204894648 ps
T117 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2612960553 Jul 30 05:26:17 PM PDT 24 Jul 30 05:26:18 PM PDT 24 245106010 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1879271875 Jul 30 05:26:18 PM PDT 24 Jul 30 05:26:20 PM PDT 24 180986099 ps
T1088 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3107187893 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:47 PM PDT 24 37346877 ps
T1089 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1349520384 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:49 PM PDT 24 76486999 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3217965933 Jul 30 05:26:25 PM PDT 24 Jul 30 05:26:27 PM PDT 24 78122927 ps
T1091 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2010212882 Jul 30 05:26:43 PM PDT 24 Jul 30 05:26:44 PM PDT 24 144016800 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.833999314 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:45 PM PDT 24 2487218813 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1367985942 Jul 30 05:26:33 PM PDT 24 Jul 30 05:26:34 PM PDT 24 89503535 ps
T1094 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3116879359 Jul 30 05:26:47 PM PDT 24 Jul 30 05:26:47 PM PDT 24 25147053 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2835120061 Jul 30 05:26:36 PM PDT 24 Jul 30 05:26:38 PM PDT 24 255709156 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.876986039 Jul 30 05:26:17 PM PDT 24 Jul 30 05:26:19 PM PDT 24 50414529 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3418927753 Jul 30 05:26:33 PM PDT 24 Jul 30 05:26:34 PM PDT 24 53849647 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3880357405 Jul 30 05:26:19 PM PDT 24 Jul 30 05:26:35 PM PDT 24 709597489 ps
T1099 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2969750187 Jul 30 05:26:34 PM PDT 24 Jul 30 05:26:37 PM PDT 24 85179421 ps
T1100 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1773946355 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:47 PM PDT 24 17671087 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1906578176 Jul 30 05:26:22 PM PDT 24 Jul 30 05:26:22 PM PDT 24 10761783 ps
T1102 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2319228226 Jul 30 05:26:18 PM PDT 24 Jul 30 05:26:20 PM PDT 24 92179059 ps
T1103 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.90763315 Jul 30 05:26:26 PM PDT 24 Jul 30 05:26:29 PM PDT 24 529338979 ps
T1104 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1558585708 Jul 30 05:26:46 PM PDT 24 Jul 30 05:26:46 PM PDT 24 14946693 ps
T1105 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2167293391 Jul 30 05:26:47 PM PDT 24 Jul 30 05:26:47 PM PDT 24 22754756 ps
T1106 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2701472436 Jul 30 05:26:34 PM PDT 24 Jul 30 05:26:38 PM PDT 24 762068616 ps
T1107 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3150035451 Jul 30 05:26:33 PM PDT 24 Jul 30 05:26:39 PM PDT 24 385700942 ps
T1108 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3880312615 Jul 30 05:26:19 PM PDT 24 Jul 30 05:26:22 PM PDT 24 89872945 ps
T1109 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3163644153 Jul 30 05:26:44 PM PDT 24 Jul 30 05:26:45 PM PDT 24 11419274 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1342366039 Jul 30 05:26:21 PM PDT 24 Jul 30 05:26:22 PM PDT 24 42343611 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1869448270 Jul 30 05:26:17 PM PDT 24 Jul 30 05:26:18 PM PDT 24 112934715 ps
T154 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.230762087 Jul 30 05:26:35 PM PDT 24 Jul 30 05:26:56 PM PDT 24 3129310653 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.405222495 Jul 30 05:26:16 PM PDT 24 Jul 30 05:26:30 PM PDT 24 6736326737 ps
T1113 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3974240098 Jul 30 05:26:34 PM PDT 24 Jul 30 05:26:36 PM PDT 24 26702878 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1414195911 Jul 30 05:26:14 PM PDT 24 Jul 30 05:26:37 PM PDT 24 356609290 ps
T1115 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3254837373 Jul 30 05:26:18 PM PDT 24 Jul 30 05:26:21 PM PDT 24 214791492 ps
T1116 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1598001987 Jul 30 05:26:39 PM PDT 24 Jul 30 05:26:42 PM PDT 24 50020082 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2661313865 Jul 30 05:26:28 PM PDT 24 Jul 30 05:26:31 PM PDT 24 131369193 ps
T1118 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2724637653 Jul 30 05:26:25 PM PDT 24 Jul 30 05:26:27 PM PDT 24 136596210 ps
T1119 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4241440052 Jul 30 05:26:18 PM PDT 24 Jul 30 05:26:20 PM PDT 24 76678106 ps
T1120 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2064656574 Jul 30 05:26:33 PM PDT 24 Jul 30 05:26:35 PM PDT 24 76869968 ps
T1121 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1651734666 Jul 30 05:26:21 PM PDT 24 Jul 30 05:26:23 PM PDT 24 186321569 ps
T1122 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3912911925 Jul 30 05:26:34 PM PDT 24 Jul 30 05:26:35 PM PDT 24 12983772 ps
T1123 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1299200985 Jul 30 05:26:28 PM PDT 24 Jul 30 05:26:30 PM PDT 24 188768174 ps
T1124 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3716126948 Jul 30 05:26:16 PM PDT 24 Jul 30 05:26:42 PM PDT 24 9202056098 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2051741513 Jul 30 05:26:31 PM PDT 24 Jul 30 05:26:48 PM PDT 24 2945349060 ps
T1126 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2476939853 Jul 30 05:26:25 PM PDT 24 Jul 30 05:26:28 PM PDT 24 2098072010 ps
T74 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.988464941 Jul 30 05:26:12 PM PDT 24 Jul 30 05:26:13 PM PDT 24 14593415 ps
T1127 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3617349077 Jul 30 05:26:32 PM PDT 24 Jul 30 05:26:36 PM PDT 24 339089149 ps
T1128 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1773895451 Jul 30 05:26:40 PM PDT 24 Jul 30 05:26:42 PM PDT 24 81986556 ps
T1129 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4176791635 Jul 30 05:26:06 PM PDT 24 Jul 30 05:26:22 PM PDT 24 1518018865 ps
T1130 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.592849056 Jul 30 05:26:53 PM PDT 24 Jul 30 05:26:54 PM PDT 24 55187194 ps
T1131 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3179225512 Jul 30 05:26:30 PM PDT 24 Jul 30 05:26:32 PM PDT 24 29162764 ps

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3227471480
Short name T10
Test name
Test status
Simulation time 3892015775 ps
CPU time 97.47 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:14:30 PM PDT 24
Peak memory 257868 kb
Host smart-1b0b10d7-6ec3-42d6-b3f5-1f84b410a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227471480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3227471480
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2759180139
Short name T13
Test name
Test status
Simulation time 7934378726 ps
CPU time 47.32 seconds
Started Jul 30 05:12:41 PM PDT 24
Finished Jul 30 05:13:28 PM PDT 24
Peak memory 250208 kb
Host smart-04a28afb-194e-4735-a45b-d686718ea96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759180139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2759180139
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3117178379
Short name T18
Test name
Test status
Simulation time 393362257343 ps
CPU time 990.99 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:30:54 PM PDT 24
Peak memory 284972 kb
Host smart-1f18013f-4f48-4237-af67-853785a2d8da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117178379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3117178379
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2128544634
Short name T86
Test name
Test status
Simulation time 8232447140 ps
CPU time 22.47 seconds
Started Jul 30 05:26:31 PM PDT 24
Finished Jul 30 05:26:54 PM PDT 24
Peak memory 215220 kb
Host smart-31efada1-12f8-4dfc-94fc-07eac6c64848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128544634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2128544634
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.999342303
Short name T151
Test name
Test status
Simulation time 318234397269 ps
CPU time 703.53 seconds
Started Jul 30 05:14:09 PM PDT 24
Finished Jul 30 05:25:53 PM PDT 24
Peak memory 282392 kb
Host smart-1993afbd-a782-4e72-81ed-ea64c5049508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999342303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.999342303
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3791831022
Short name T53
Test name
Test status
Simulation time 16448166 ps
CPU time 0.74 seconds
Started Jul 30 05:11:36 PM PDT 24
Finished Jul 30 05:11:37 PM PDT 24
Peak memory 216448 kb
Host smart-896ed270-687d-48f6-aaa0-d469d336e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791831022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3791831022
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.620358543
Short name T16
Test name
Test status
Simulation time 82545145067 ps
CPU time 200.54 seconds
Started Jul 30 05:13:47 PM PDT 24
Finished Jul 30 05:17:07 PM PDT 24
Peak memory 269768 kb
Host smart-7dbd603e-770e-40bd-b7f4-277313d2d843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620358543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.620358543
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3020552511
Short name T203
Test name
Test status
Simulation time 58018102233 ps
CPU time 615.56 seconds
Started Jul 30 05:13:39 PM PDT 24
Finished Jul 30 05:23:55 PM PDT 24
Peak memory 270568 kb
Host smart-22a29b43-84cb-4f5e-9589-b2bde0d6185e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020552511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3020552511
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3885591100
Short name T50
Test name
Test status
Simulation time 358827942 ps
CPU time 4.27 seconds
Started Jul 30 05:26:38 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 215284 kb
Host smart-ded33c87-58bd-4318-8c0d-bb4a811e7e21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885591100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3885591100
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4231716453
Short name T68
Test name
Test status
Simulation time 78186596946 ps
CPU time 546.2 seconds
Started Jul 30 05:14:07 PM PDT 24
Finished Jul 30 05:23:13 PM PDT 24
Peak memory 260156 kb
Host smart-c1fc90ab-71d8-4ef3-89e5-4902ac534665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231716453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4231716453
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1972008569
Short name T20
Test name
Test status
Simulation time 36333882 ps
CPU time 0.99 seconds
Started Jul 30 05:11:50 PM PDT 24
Finished Jul 30 05:11:51 PM PDT 24
Peak memory 236712 kb
Host smart-f1c5897d-b9ad-4b51-9212-5fa7c54bd44b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972008569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1972008569
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3215125111
Short name T34
Test name
Test status
Simulation time 3142320215 ps
CPU time 45.86 seconds
Started Jul 30 05:11:48 PM PDT 24
Finished Jul 30 05:12:34 PM PDT 24
Peak memory 233184 kb
Host smart-25198dbc-1c80-4bdc-8be7-2c0250915e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215125111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3215125111
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1050155010
Short name T14
Test name
Test status
Simulation time 83064517860 ps
CPU time 474.52 seconds
Started Jul 30 05:13:33 PM PDT 24
Finished Jul 30 05:21:28 PM PDT 24
Peak memory 264444 kb
Host smart-f4117d43-178c-42a0-a9bf-b46ea39b91c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050155010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1050155010
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.522926444
Short name T163
Test name
Test status
Simulation time 327736086255 ps
CPU time 694.41 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:25:15 PM PDT 24
Peak memory 266612 kb
Host smart-d61c7fb5-de03-45b1-b40c-c37fc8612517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522926444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.522926444
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3171989399
Short name T173
Test name
Test status
Simulation time 38145876192 ps
CPU time 126.76 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:13:58 PM PDT 24
Peak memory 264908 kb
Host smart-7e407cec-2f06-41d9-ab17-63d7e9a44570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171989399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3171989399
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1167236848
Short name T70
Test name
Test status
Simulation time 15011911 ps
CPU time 0.94 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:18 PM PDT 24
Peak memory 206724 kb
Host smart-c17b102e-11f0-45fa-8f13-447ddf8a0679
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167236848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1167236848
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3121066260
Short name T166
Test name
Test status
Simulation time 957890635052 ps
CPU time 499.32 seconds
Started Jul 30 05:15:05 PM PDT 24
Finished Jul 30 05:23:25 PM PDT 24
Peak memory 265984 kb
Host smart-6c030885-e77f-4691-a0a9-a7399cf81c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121066260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3121066260
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4247249124
Short name T42
Test name
Test status
Simulation time 393510149234 ps
CPU time 554.12 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:23:16 PM PDT 24
Peak memory 262672 kb
Host smart-8723dd43-bc31-4921-989f-29bdf3978a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247249124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4247249124
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3080595317
Short name T183
Test name
Test status
Simulation time 794392528875 ps
CPU time 687.93 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:23:33 PM PDT 24
Peak memory 266012 kb
Host smart-45834141-b4ac-434c-96c9-648b59f4cb88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080595317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3080595317
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2467298845
Short name T200
Test name
Test status
Simulation time 357999814519 ps
CPU time 425.44 seconds
Started Jul 30 05:15:10 PM PDT 24
Finished Jul 30 05:22:15 PM PDT 24
Peak memory 283248 kb
Host smart-bd22f027-92b3-463c-a725-b4d63d0f55cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467298845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2467298845
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.781373136
Short name T79
Test name
Test status
Simulation time 114085161728 ps
CPU time 410.36 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:18:51 PM PDT 24
Peak memory 266100 kb
Host smart-9b99ec58-fa9c-4035-82b9-47c8aab6bbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781373136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
781373136
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2598419726
Short name T257
Test name
Test status
Simulation time 23802405395 ps
CPU time 100.67 seconds
Started Jul 30 05:12:45 PM PDT 24
Finished Jul 30 05:14:25 PM PDT 24
Peak memory 257280 kb
Host smart-434bca79-def0-47b5-92d8-ae941704b33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598419726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2598419726
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4211616139
Short name T1
Test name
Test status
Simulation time 18891854401 ps
CPU time 13.07 seconds
Started Jul 30 05:14:03 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 216664 kb
Host smart-65cb5010-30f5-4834-8ad6-6510cd54301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211616139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4211616139
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3746724701
Short name T301
Test name
Test status
Simulation time 64199634 ps
CPU time 0.74 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:36 PM PDT 24
Peak memory 205848 kb
Host smart-b48aa64a-8601-4042-98cb-3eaedfd760d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746724701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3746724701
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3285579461
Short name T205
Test name
Test status
Simulation time 1430802398 ps
CPU time 37.88 seconds
Started Jul 30 05:13:17 PM PDT 24
Finished Jul 30 05:13:55 PM PDT 24
Peak memory 254696 kb
Host smart-49de6343-75c7-4612-9c30-e58bceb62de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285579461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3285579461
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.867521817
Short name T187
Test name
Test status
Simulation time 15789716537 ps
CPU time 167.12 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 257036 kb
Host smart-db08ed1c-68f2-47eb-aa5c-9354e2ff02cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867521817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.867521817
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1616100293
Short name T15
Test name
Test status
Simulation time 11874111190 ps
CPU time 74.51 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 259148 kb
Host smart-77994339-8de8-407d-a06d-3700aae709c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616100293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1616100293
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2742572980
Short name T7
Test name
Test status
Simulation time 4959843643 ps
CPU time 103.25 seconds
Started Jul 30 05:12:45 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 270004 kb
Host smart-06066ae3-9d95-48d8-96a1-f7ed32b1cd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742572980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2742572980
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2913862726
Short name T164
Test name
Test status
Simulation time 23710940123 ps
CPU time 92.31 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:15:30 PM PDT 24
Peak memory 254324 kb
Host smart-5705e835-b98a-48c3-88d7-218443e84b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913862726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2913862726
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2234460715
Short name T94
Test name
Test status
Simulation time 65254997 ps
CPU time 4.35 seconds
Started Jul 30 05:26:06 PM PDT 24
Finished Jul 30 05:26:10 PM PDT 24
Peak memory 216176 kb
Host smart-a87b7756-a795-468a-b448-69acfeca6c55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234460715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
234460715
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2808731557
Short name T153
Test name
Test status
Simulation time 726188452 ps
CPU time 17.96 seconds
Started Jul 30 05:26:22 PM PDT 24
Finished Jul 30 05:26:40 PM PDT 24
Peak memory 215176 kb
Host smart-f4090aa6-4994-4b84-8c95-d8a2ead73b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808731557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2808731557
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4094095094
Short name T270
Test name
Test status
Simulation time 1029552093 ps
CPU time 23.66 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:14:26 PM PDT 24
Peak memory 234384 kb
Host smart-916cc094-0fe5-4079-8738-7bac9cf93827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094095094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4094095094
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2893179594
Short name T9
Test name
Test status
Simulation time 72249526128 ps
CPU time 464.55 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:22:11 PM PDT 24
Peak memory 252692 kb
Host smart-c58b6816-9674-4ba4-967a-0aad077bdcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893179594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2893179594
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3916147065
Short name T25
Test name
Test status
Simulation time 75547069276 ps
CPU time 173.44 seconds
Started Jul 30 05:14:47 PM PDT 24
Finished Jul 30 05:17:41 PM PDT 24
Peak memory 252484 kb
Host smart-310ed9a1-2103-42e0-9de3-eb575dbe809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916147065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3916147065
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4209054974
Short name T182
Test name
Test status
Simulation time 235049618874 ps
CPU time 597.13 seconds
Started Jul 30 05:11:46 PM PDT 24
Finished Jul 30 05:21:43 PM PDT 24
Peak memory 257392 kb
Host smart-e498b496-7c4a-4b67-9818-4310b8c3ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209054974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4209054974
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3613370800
Short name T175
Test name
Test status
Simulation time 71880770133 ps
CPU time 195.82 seconds
Started Jul 30 05:12:36 PM PDT 24
Finished Jul 30 05:15:52 PM PDT 24
Peak memory 256268 kb
Host smart-bf68146a-7ab3-4496-87ce-abbc029cc842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613370800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3613370800
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1788285262
Short name T174
Test name
Test status
Simulation time 64571470856 ps
CPU time 161.4 seconds
Started Jul 30 05:12:31 PM PDT 24
Finished Jul 30 05:15:13 PM PDT 24
Peak memory 254800 kb
Host smart-6f4007b2-6ebe-490b-b628-c464d7fcbb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788285262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1788285262
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3055305102
Short name T172
Test name
Test status
Simulation time 58953759900 ps
CPU time 117.76 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:14:48 PM PDT 24
Peak memory 265936 kb
Host smart-7cca6883-12a0-4cb5-a79b-2303417b6717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055305102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3055305102
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.91411221
Short name T147
Test name
Test status
Simulation time 97616777884 ps
CPU time 400.25 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:21:50 PM PDT 24
Peak memory 266072 kb
Host smart-2db37dbb-4d7c-4cab-a37c-114211f53038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91411221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress
_all.91411221
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2425408559
Short name T99
Test name
Test status
Simulation time 4377111448 ps
CPU time 25.22 seconds
Started Jul 30 05:26:37 PM PDT 24
Finished Jul 30 05:27:02 PM PDT 24
Peak memory 215464 kb
Host smart-33fde5df-f0b9-4094-bac7-27d550d9f717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425408559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2425408559
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2466276681
Short name T159
Test name
Test status
Simulation time 603196473 ps
CPU time 6.03 seconds
Started Jul 30 05:12:25 PM PDT 24
Finished Jul 30 05:12:31 PM PDT 24
Peak memory 224904 kb
Host smart-74b5844b-e79c-4cf0-bf23-c808dd880870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466276681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2466276681
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2213233203
Short name T137
Test name
Test status
Simulation time 8827935752 ps
CPU time 39.35 seconds
Started Jul 30 05:12:29 PM PDT 24
Finished Jul 30 05:13:08 PM PDT 24
Peak memory 234272 kb
Host smart-9221fbf9-948c-4056-b71c-ff1e2052b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213233203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2213233203
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2862644526
Short name T952
Test name
Test status
Simulation time 100363861644 ps
CPU time 370.12 seconds
Started Jul 30 05:12:31 PM PDT 24
Finished Jul 30 05:18:41 PM PDT 24
Peak memory 252852 kb
Host smart-4a03e4e1-55c4-418f-9ddc-b116b77f39c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862644526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2862644526
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1935906521
Short name T209
Test name
Test status
Simulation time 68065058342 ps
CPU time 198.83 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:16:09 PM PDT 24
Peak memory 255840 kb
Host smart-1f15de2e-ea01-4d7b-809c-3fe01a339b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935906521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1935906521
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1592421517
Short name T288
Test name
Test status
Simulation time 58667219638 ps
CPU time 172.6 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:16:03 PM PDT 24
Peak memory 251976 kb
Host smart-770e9f60-a5e5-49ad-80a8-3722df149992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592421517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1592421517
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4197138273
Short name T217
Test name
Test status
Simulation time 294629091162 ps
CPU time 389.13 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:19:54 PM PDT 24
Peak memory 257252 kb
Host smart-c86b8cf3-dc24-4cdb-980d-7ffac4f30535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197138273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4197138273
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.346059014
Short name T43
Test name
Test status
Simulation time 368090425818 ps
CPU time 301.36 seconds
Started Jul 30 05:15:20 PM PDT 24
Finished Jul 30 05:20:22 PM PDT 24
Peak memory 271580 kb
Host smart-3b8d0341-cd2d-4e9a-bc4b-b2d7617bf6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346059014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.346059014
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1742593418
Short name T83
Test name
Test status
Simulation time 29760013664 ps
CPU time 14.1 seconds
Started Jul 30 05:14:03 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 239164 kb
Host smart-3b01986f-d28f-4432-9ae5-be7235fae81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742593418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1742593418
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3294244964
Short name T1057
Test name
Test status
Simulation time 85573626 ps
CPU time 2.69 seconds
Started Jul 30 05:26:31 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 215460 kb
Host smart-b477d6c9-c725-4f82-a928-bcc9bd7895d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294244964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3294244964
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1994624764
Short name T71
Test name
Test status
Simulation time 94654937 ps
CPU time 1 seconds
Started Jul 30 05:26:12 PM PDT 24
Finished Jul 30 05:26:13 PM PDT 24
Peak memory 206832 kb
Host smart-d902a62c-a217-47e3-9f1f-95bb357f2225
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994624764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1994624764
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1082213491
Short name T1008
Test name
Test status
Simulation time 855234616 ps
CPU time 14.76 seconds
Started Jul 30 05:26:10 PM PDT 24
Finished Jul 30 05:26:25 PM PDT 24
Peak memory 215104 kb
Host smart-c9fb4343-5174-4edd-a41d-037269527fe6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082213491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1082213491
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1414195911
Short name T1114
Test name
Test status
Simulation time 356609290 ps
CPU time 23.31 seconds
Started Jul 30 05:26:14 PM PDT 24
Finished Jul 30 05:26:37 PM PDT 24
Peak memory 206952 kb
Host smart-294d61f4-e76b-4a6d-8205-69497d784afb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414195911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1414195911
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4081832011
Short name T93
Test name
Test status
Simulation time 92635444 ps
CPU time 2.58 seconds
Started Jul 30 05:26:11 PM PDT 24
Finished Jul 30 05:26:14 PM PDT 24
Peak memory 218328 kb
Host smart-82f87b76-4a06-4a60-83f3-e8e6e67bced4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081832011 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4081832011
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3254210084
Short name T112
Test name
Test status
Simulation time 125026822 ps
CPU time 2.23 seconds
Started Jul 30 05:26:11 PM PDT 24
Finished Jul 30 05:26:13 PM PDT 24
Peak memory 215096 kb
Host smart-992520b7-053e-4676-9e76-766212529f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254210084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
254210084
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2389614631
Short name T1028
Test name
Test status
Simulation time 45154948 ps
CPU time 0.69 seconds
Started Jul 30 05:26:06 PM PDT 24
Finished Jul 30 05:26:06 PM PDT 24
Peak memory 203656 kb
Host smart-38d2658e-f481-49bc-8550-709e25c4459b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389614631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
389614631
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2657738781
Short name T105
Test name
Test status
Simulation time 107210664 ps
CPU time 1.99 seconds
Started Jul 30 05:26:04 PM PDT 24
Finished Jul 30 05:26:06 PM PDT 24
Peak memory 215112 kb
Host smart-ba18e027-18f0-4647-984f-fe0e46f7b3a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657738781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2657738781
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1274849256
Short name T1015
Test name
Test status
Simulation time 21079525 ps
CPU time 0.68 seconds
Started Jul 30 05:26:05 PM PDT 24
Finished Jul 30 05:26:05 PM PDT 24
Peak memory 203956 kb
Host smart-ea952e6b-0a7f-4cd0-9608-16e7bc24020e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274849256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1274849256
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.709168557
Short name T143
Test name
Test status
Simulation time 214840647 ps
CPU time 4.38 seconds
Started Jul 30 05:26:11 PM PDT 24
Finished Jul 30 05:26:15 PM PDT 24
Peak memory 215204 kb
Host smart-5fe9b23e-6524-4258-b14a-d639deb4014e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709168557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.709168557
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4176791635
Short name T1129
Test name
Test status
Simulation time 1518018865 ps
CPU time 16.03 seconds
Started Jul 30 05:26:06 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 215400 kb
Host smart-831b907f-dd20-46a2-af95-0a0f6297af48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176791635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4176791635
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2782087517
Short name T1048
Test name
Test status
Simulation time 397507354 ps
CPU time 8.82 seconds
Started Jul 30 05:26:13 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 215164 kb
Host smart-fabdeeaf-afa4-4d27-a6bb-58649d85d2a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782087517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2782087517
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1830872314
Short name T1055
Test name
Test status
Simulation time 191659619 ps
CPU time 11.86 seconds
Started Jul 30 05:26:14 PM PDT 24
Finished Jul 30 05:26:25 PM PDT 24
Peak memory 215228 kb
Host smart-68480f05-31a2-4c06-9870-163b04ae549a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830872314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1830872314
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.988464941
Short name T74
Test name
Test status
Simulation time 14593415 ps
CPU time 0.97 seconds
Started Jul 30 05:26:12 PM PDT 24
Finished Jul 30 05:26:13 PM PDT 24
Peak memory 206832 kb
Host smart-c2ddd335-08e9-4d43-8456-56ccca2d3b45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988464941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.988464941
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.413223341
Short name T96
Test name
Test status
Simulation time 92512422 ps
CPU time 2.84 seconds
Started Jul 30 05:26:14 PM PDT 24
Finished Jul 30 05:26:17 PM PDT 24
Peak memory 217528 kb
Host smart-a7097428-0cff-4eae-9008-1e4d7db83fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413223341 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.413223341
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2810391266
Short name T141
Test name
Test status
Simulation time 76819251 ps
CPU time 1.89 seconds
Started Jul 30 05:26:13 PM PDT 24
Finished Jul 30 05:26:15 PM PDT 24
Peak memory 215148 kb
Host smart-756db183-987d-4ac7-9646-3993d6ba9ba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810391266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
810391266
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2315046154
Short name T1039
Test name
Test status
Simulation time 14335991 ps
CPU time 0.76 seconds
Started Jul 30 05:26:12 PM PDT 24
Finished Jul 30 05:26:13 PM PDT 24
Peak memory 204000 kb
Host smart-11145ac4-3207-4061-9083-b8ad5ab90174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315046154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
315046154
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2211187011
Short name T110
Test name
Test status
Simulation time 51041324 ps
CPU time 2.07 seconds
Started Jul 30 05:26:14 PM PDT 24
Finished Jul 30 05:26:17 PM PDT 24
Peak memory 215084 kb
Host smart-b4bfdc5b-c836-41bc-bbff-9c77957ffef3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211187011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2211187011
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2553245507
Short name T1007
Test name
Test status
Simulation time 11941276 ps
CPU time 0.69 seconds
Started Jul 30 05:26:14 PM PDT 24
Finished Jul 30 05:26:14 PM PDT 24
Peak memory 203500 kb
Host smart-82d868b7-fb08-4590-86ed-62a10f56f941
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553245507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2553245507
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2972433361
Short name T1067
Test name
Test status
Simulation time 383677069 ps
CPU time 4.02 seconds
Started Jul 30 05:26:13 PM PDT 24
Finished Jul 30 05:26:17 PM PDT 24
Peak memory 215128 kb
Host smart-25ddb1b7-eee4-4a9e-b9fe-ca5e1fc72231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972433361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2972433361
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2458440093
Short name T90
Test name
Test status
Simulation time 87198689 ps
CPU time 5.63 seconds
Started Jul 30 05:26:12 PM PDT 24
Finished Jul 30 05:26:17 PM PDT 24
Peak memory 215376 kb
Host smart-a08d49d5-4744-423a-9043-b1880fbb62df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458440093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
458440093
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2509272006
Short name T1065
Test name
Test status
Simulation time 604812875 ps
CPU time 15.51 seconds
Started Jul 30 05:26:11 PM PDT 24
Finished Jul 30 05:26:27 PM PDT 24
Peak memory 215400 kb
Host smart-b498c0a6-5c68-4fc6-bed9-4fbe540c15c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509272006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2509272006
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2159981670
Short name T1050
Test name
Test status
Simulation time 544565618 ps
CPU time 3.51 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:37 PM PDT 24
Peak memory 217148 kb
Host smart-19280d77-a990-4db8-b83b-2fec120ccee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159981670 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2159981670
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2944303594
Short name T106
Test name
Test status
Simulation time 90265378 ps
CPU time 2.58 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 215160 kb
Host smart-3ec75cd7-82f5-4c20-9fe7-1ce708283502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944303594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2944303594
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2715997378
Short name T1032
Test name
Test status
Simulation time 13924599 ps
CPU time 0.72 seconds
Started Jul 30 05:26:29 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 203980 kb
Host smart-913326ce-61a4-4a15-bf31-fad6367c2e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715997378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2715997378
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.222417157
Short name T1024
Test name
Test status
Simulation time 138244851 ps
CPU time 3.04 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:35 PM PDT 24
Peak memory 215140 kb
Host smart-ea45a745-b469-488b-819e-d575689013aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222417157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.222417157
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2476939853
Short name T1126
Test name
Test status
Simulation time 2098072010 ps
CPU time 3 seconds
Started Jul 30 05:26:25 PM PDT 24
Finished Jul 30 05:26:28 PM PDT 24
Peak memory 215300 kb
Host smart-d7a80f6b-64b6-47ca-972d-408b6c98942a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476939853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2476939853
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3994652534
Short name T155
Test name
Test status
Simulation time 1090129976 ps
CPU time 14.7 seconds
Started Jul 30 05:26:27 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 215980 kb
Host smart-635c1dea-d825-4554-9d76-b4d2af72c144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994652534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3994652534
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2661313865
Short name T1117
Test name
Test status
Simulation time 131369193 ps
CPU time 2.63 seconds
Started Jul 30 05:26:28 PM PDT 24
Finished Jul 30 05:26:31 PM PDT 24
Peak memory 216664 kb
Host smart-4537627a-3bd7-4390-b77c-0c86b1c2e2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661313865 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2661313865
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.990161894
Short name T113
Test name
Test status
Simulation time 38953061 ps
CPU time 2.47 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 215188 kb
Host smart-da32a980-bcd8-4dad-9fcb-4286d9493f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990161894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.990161894
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2744620151
Short name T1062
Test name
Test status
Simulation time 56918390 ps
CPU time 0.73 seconds
Started Jul 30 05:26:28 PM PDT 24
Finished Jul 30 05:26:29 PM PDT 24
Peak memory 203960 kb
Host smart-216a3cfa-0af9-4f7b-9d5d-97f9c4d0ea8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744620151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2744620151
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.158690438
Short name T142
Test name
Test status
Simulation time 1088571790 ps
CPU time 3.23 seconds
Started Jul 30 05:26:27 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 215136 kb
Host smart-4a6e0be4-94b0-4615-976c-d77063d8c0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158690438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.158690438
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.672945181
Short name T95
Test name
Test status
Simulation time 133778809 ps
CPU time 1.9 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 215288 kb
Host smart-e62d3aeb-110c-4db1-8064-341d9dbec493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672945181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.672945181
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2051741513
Short name T1125
Test name
Test status
Simulation time 2945349060 ps
CPU time 16.67 seconds
Started Jul 30 05:26:31 PM PDT 24
Finished Jul 30 05:26:48 PM PDT 24
Peak memory 215560 kb
Host smart-b66649d3-6d49-4129-b116-7e1703de81a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051741513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2051741513
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3974240098
Short name T1113
Test name
Test status
Simulation time 26702878 ps
CPU time 1.76 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 215092 kb
Host smart-ba183511-834f-4367-b71a-d1506353df38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974240098 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3974240098
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.192703016
Short name T1027
Test name
Test status
Simulation time 91776816 ps
CPU time 1.2 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:33 PM PDT 24
Peak memory 215200 kb
Host smart-4b5d6742-51b4-46f6-bfa1-14959933dedc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192703016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.192703016
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2527403863
Short name T1014
Test name
Test status
Simulation time 41809264 ps
CPU time 0.75 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:35 PM PDT 24
Peak memory 203660 kb
Host smart-5bfee67e-b622-4796-a2e7-06c462ea9d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527403863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2527403863
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3362257406
Short name T1019
Test name
Test status
Simulation time 226457837 ps
CPU time 1.84 seconds
Started Jul 30 05:26:28 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 206956 kb
Host smart-2559c3ac-1e26-459e-8b1f-a3923d0307eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362257406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3362257406
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1707129369
Short name T1054
Test name
Test status
Simulation time 52825190 ps
CPU time 3.49 seconds
Started Jul 30 05:26:30 PM PDT 24
Finished Jul 30 05:26:33 PM PDT 24
Peak memory 215196 kb
Host smart-5d54cc01-5299-4e94-92f5-dd90dcd78151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707129369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1707129369
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.568648291
Short name T1080
Test name
Test status
Simulation time 210506869 ps
CPU time 2.77 seconds
Started Jul 30 05:26:27 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 217544 kb
Host smart-f7c5f6c3-369f-4937-b8cf-d38bdfae9e09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568648291 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.568648291
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1299200985
Short name T1123
Test name
Test status
Simulation time 188768174 ps
CPU time 1.27 seconds
Started Jul 30 05:26:28 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 215168 kb
Host smart-47558cf2-003e-4a15-b41e-55853b77281b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299200985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1299200985
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4206024131
Short name T1029
Test name
Test status
Simulation time 17503472 ps
CPU time 0.76 seconds
Started Jul 30 05:26:30 PM PDT 24
Finished Jul 30 05:26:31 PM PDT 24
Peak memory 203948 kb
Host smart-5d506de8-51e5-476c-8caf-2c940ae62c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206024131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4206024131
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2969750187
Short name T1099
Test name
Test status
Simulation time 85179421 ps
CPU time 3.04 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:37 PM PDT 24
Peak memory 215180 kb
Host smart-24a844f2-d4e4-4c16-9b79-ccb78bed2bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969750187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2969750187
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1369839306
Short name T1083
Test name
Test status
Simulation time 189008581 ps
CPU time 4.7 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 215216 kb
Host smart-65036b7e-9a11-4225-805a-3907096aa898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369839306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1369839306
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1757906273
Short name T1082
Test name
Test status
Simulation time 3831892500 ps
CPU time 23.16 seconds
Started Jul 30 05:26:48 PM PDT 24
Finished Jul 30 05:27:11 PM PDT 24
Peak memory 215444 kb
Host smart-cf5ca9f4-7dfc-48a8-9509-381e2fd9ea78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757906273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1757906273
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3179225512
Short name T1131
Test name
Test status
Simulation time 29162764 ps
CPU time 1.82 seconds
Started Jul 30 05:26:30 PM PDT 24
Finished Jul 30 05:26:32 PM PDT 24
Peak memory 216184 kb
Host smart-6ded21a1-eab2-45dc-a1af-ca302492dd46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179225512 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3179225512
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2064656574
Short name T1120
Test name
Test status
Simulation time 76869968 ps
CPU time 2.09 seconds
Started Jul 30 05:26:33 PM PDT 24
Finished Jul 30 05:26:35 PM PDT 24
Peak memory 215168 kb
Host smart-46012017-4bfc-45a5-b047-52f6ddecf78d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064656574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2064656574
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2986215300
Short name T1040
Test name
Test status
Simulation time 19198351 ps
CPU time 0.75 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:33 PM PDT 24
Peak memory 203676 kb
Host smart-6f979a64-e4ac-43d8-9d87-8a8e7ca059cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986215300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2986215300
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.32444928
Short name T1049
Test name
Test status
Simulation time 55102312 ps
CPU time 1.78 seconds
Started Jul 30 05:26:28 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 215196 kb
Host smart-a53f1791-f520-4190-bccc-88fbd82dbe64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32444928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sp
i_device_same_csr_outstanding.32444928
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3617349077
Short name T1127
Test name
Test status
Simulation time 339089149 ps
CPU time 4.06 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 215224 kb
Host smart-20f2e4d8-1a22-4d1f-8023-c99fd2c3970c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617349077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3617349077
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3150035451
Short name T1107
Test name
Test status
Simulation time 385700942 ps
CPU time 6.12 seconds
Started Jul 30 05:26:33 PM PDT 24
Finished Jul 30 05:26:39 PM PDT 24
Peak memory 215168 kb
Host smart-66c544d4-88db-415c-a050-eab34c87ef7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150035451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3150035451
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2425766188
Short name T1086
Test name
Test status
Simulation time 204894648 ps
CPU time 2.64 seconds
Started Jul 30 05:26:31 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 216168 kb
Host smart-4e592b6c-975f-4031-a027-eb2a2f09b03e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425766188 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2425766188
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4072010904
Short name T104
Test name
Test status
Simulation time 92879468 ps
CPU time 2.35 seconds
Started Jul 30 05:26:30 PM PDT 24
Finished Jul 30 05:26:32 PM PDT 24
Peak memory 215180 kb
Host smart-db94059d-0f1d-4f3d-b2ef-e83228c183e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072010904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4072010904
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3912911925
Short name T1122
Test name
Test status
Simulation time 12983772 ps
CPU time 0.75 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:35 PM PDT 24
Peak memory 203640 kb
Host smart-ee8fed94-6687-421c-81c1-e38d85a2d9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912911925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3912911925
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2701472436
Short name T1106
Test name
Test status
Simulation time 762068616 ps
CPU time 4.51 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:38 PM PDT 24
Peak memory 215112 kb
Host smart-aad99073-f3e7-4f9b-a463-10ef0196f9aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701472436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2701472436
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.833999314
Short name T1092
Test name
Test status
Simulation time 2487218813 ps
CPU time 12.76 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 215292 kb
Host smart-5c028c44-9438-42b5-aa66-c83211fd1bee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833999314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.833999314
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1367985942
Short name T1093
Test name
Test status
Simulation time 89503535 ps
CPU time 1.53 seconds
Started Jul 30 05:26:33 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 215140 kb
Host smart-956decce-eefb-41a8-8a2f-abb7876c1db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367985942 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1367985942
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1194029372
Short name T107
Test name
Test status
Simulation time 30428439 ps
CPU time 1.97 seconds
Started Jul 30 05:26:34 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 206916 kb
Host smart-3308f9c3-e0e1-4cc4-b33a-8c83e4fbc27e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194029372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1194029372
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3418927753
Short name T1097
Test name
Test status
Simulation time 53849647 ps
CPU time 0.77 seconds
Started Jul 30 05:26:33 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 203696 kb
Host smart-bcd3b7a4-64ef-4bae-b5c5-7121d2f12ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418927753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3418927753
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.657309625
Short name T133
Test name
Test status
Simulation time 604152535 ps
CPU time 4 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 215140 kb
Host smart-7e0acd00-d54d-409e-acf3-4a69d4abc883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657309625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.657309625
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4081436272
Short name T85
Test name
Test status
Simulation time 590635984 ps
CPU time 2.75 seconds
Started Jul 30 05:26:33 PM PDT 24
Finished Jul 30 05:26:36 PM PDT 24
Peak memory 215200 kb
Host smart-e4671e19-e99b-42da-9708-13070e75c3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081436272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4081436272
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.230762087
Short name T154
Test name
Test status
Simulation time 3129310653 ps
CPU time 21.65 seconds
Started Jul 30 05:26:35 PM PDT 24
Finished Jul 30 05:26:56 PM PDT 24
Peak memory 215860 kb
Host smart-c687b621-9b5d-4690-9e85-0440b22a2442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230762087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.230762087
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2540207802
Short name T1084
Test name
Test status
Simulation time 305918699 ps
CPU time 4.19 seconds
Started Jul 30 05:26:37 PM PDT 24
Finished Jul 30 05:26:41 PM PDT 24
Peak memory 217212 kb
Host smart-1e76519d-af18-4a97-ab9c-70ad262405b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540207802 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2540207802
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2835120061
Short name T1095
Test name
Test status
Simulation time 255709156 ps
CPU time 2.5 seconds
Started Jul 30 05:26:36 PM PDT 24
Finished Jul 30 05:26:38 PM PDT 24
Peak memory 215224 kb
Host smart-3871314a-b484-49ae-96bc-a3e5f30b4715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835120061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2835120061
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1650132241
Short name T1063
Test name
Test status
Simulation time 14639585 ps
CPU time 0.73 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:32 PM PDT 24
Peak memory 203636 kb
Host smart-ac037ab1-e790-4f39-b4a2-c6736128cb29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650132241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1650132241
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2391300303
Short name T1074
Test name
Test status
Simulation time 227135265 ps
CPU time 3.87 seconds
Started Jul 30 05:26:37 PM PDT 24
Finished Jul 30 05:26:41 PM PDT 24
Peak memory 215164 kb
Host smart-c56debd1-bb95-414b-9cfb-a948b1ecc553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391300303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2391300303
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3986377408
Short name T91
Test name
Test status
Simulation time 56154504 ps
CPU time 1.96 seconds
Started Jul 30 05:26:32 PM PDT 24
Finished Jul 30 05:26:34 PM PDT 24
Peak memory 216440 kb
Host smart-adec238f-c66b-4da1-ae38-c0da38e62ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986377408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3986377408
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2718317390
Short name T52
Test name
Test status
Simulation time 4364141407 ps
CPU time 25.36 seconds
Started Jul 30 05:26:30 PM PDT 24
Finished Jul 30 05:26:56 PM PDT 24
Peak memory 215568 kb
Host smart-e430357a-e3a5-4b26-a6df-bbc5243c7594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718317390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2718317390
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3615724269
Short name T1038
Test name
Test status
Simulation time 204013641 ps
CPU time 3.88 seconds
Started Jul 30 05:26:38 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 218160 kb
Host smart-684cadbd-8a71-41ad-9f6d-c746dbafe566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615724269 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3615724269
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2936686188
Short name T1042
Test name
Test status
Simulation time 137360051 ps
CPU time 1.35 seconds
Started Jul 30 05:26:37 PM PDT 24
Finished Jul 30 05:26:39 PM PDT 24
Peak memory 206848 kb
Host smart-15b0531d-ad4a-4d7e-9776-1479d9c163bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936686188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2936686188
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1725639275
Short name T1013
Test name
Test status
Simulation time 31845166 ps
CPU time 0.74 seconds
Started Jul 30 05:26:38 PM PDT 24
Finished Jul 30 05:26:39 PM PDT 24
Peak memory 203640 kb
Host smart-594e5b82-839a-497e-92d5-a59fed34ad95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725639275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1725639275
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2123912807
Short name T1081
Test name
Test status
Simulation time 395183094 ps
CPU time 1.91 seconds
Started Jul 30 05:26:39 PM PDT 24
Finished Jul 30 05:26:41 PM PDT 24
Peak memory 215184 kb
Host smart-b05ef6ec-df7e-482e-8b3d-7b6bb674ee08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123912807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2123912807
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1773895451
Short name T1128
Test name
Test status
Simulation time 81986556 ps
CPU time 1.86 seconds
Started Jul 30 05:26:40 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 215396 kb
Host smart-87f05e4c-bcf2-45a3-9740-fff446a42bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773895451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1773895451
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1349520384
Short name T1089
Test name
Test status
Simulation time 76486999 ps
CPU time 2.59 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:49 PM PDT 24
Peak memory 215220 kb
Host smart-72494ff1-4b0f-4eea-b9c8-489789ea77b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349520384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1349520384
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1425806846
Short name T1047
Test name
Test status
Simulation time 13321213 ps
CPU time 0.71 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 203656 kb
Host smart-20201503-b680-453b-acbc-ce9b52aee7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425806846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1425806846
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.562608820
Short name T144
Test name
Test status
Simulation time 892181460 ps
CPU time 4.38 seconds
Started Jul 30 05:26:43 PM PDT 24
Finished Jul 30 05:26:48 PM PDT 24
Peak memory 214992 kb
Host smart-a2d84f4f-c481-4f33-ad2b-2e56b33a1386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562608820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.562608820
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1598001987
Short name T1116
Test name
Test status
Simulation time 50020082 ps
CPU time 3.28 seconds
Started Jul 30 05:26:39 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 215488 kb
Host smart-19d61c1c-3b41-403c-a38e-c0bb80aeda4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598001987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1598001987
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3065098276
Short name T1056
Test name
Test status
Simulation time 2223431473 ps
CPU time 21.57 seconds
Started Jul 30 05:26:54 PM PDT 24
Finished Jul 30 05:27:16 PM PDT 24
Peak memory 215324 kb
Host smart-413c3f9e-f5c9-499a-983e-05b0bd1d30ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065098276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3065098276
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3026541693
Short name T1061
Test name
Test status
Simulation time 444773630 ps
CPU time 9.28 seconds
Started Jul 30 05:26:22 PM PDT 24
Finished Jul 30 05:26:31 PM PDT 24
Peak memory 215132 kb
Host smart-cb6debf5-d238-4a81-9463-d89fbdddd2b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026541693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3026541693
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.986557595
Short name T108
Test name
Test status
Simulation time 1851309892 ps
CPU time 27.41 seconds
Started Jul 30 05:26:16 PM PDT 24
Finished Jul 30 05:26:44 PM PDT 24
Peak memory 215176 kb
Host smart-eff9b250-083c-4d77-9243-3834aab14121
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986557595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.986557595
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.671156027
Short name T73
Test name
Test status
Simulation time 21884631 ps
CPU time 1.28 seconds
Started Jul 30 05:26:11 PM PDT 24
Finished Jul 30 05:26:13 PM PDT 24
Peak memory 207024 kb
Host smart-f0e510c7-975c-4816-b35e-1479741ff485
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671156027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.671156027
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2953055357
Short name T1030
Test name
Test status
Simulation time 99469915 ps
CPU time 3.5 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:21 PM PDT 24
Peak memory 218044 kb
Host smart-e46c0fb2-a0a0-4268-a14b-7b960019a7a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953055357 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2953055357
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4241440052
Short name T1119
Test name
Test status
Simulation time 76678106 ps
CPU time 2.03 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 215220 kb
Host smart-dc2e51f1-e7f7-400c-a6a8-4338c13b8e4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241440052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
241440052
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1980613483
Short name T1051
Test name
Test status
Simulation time 42797396 ps
CPU time 0.75 seconds
Started Jul 30 05:26:15 PM PDT 24
Finished Jul 30 05:26:16 PM PDT 24
Peak memory 203980 kb
Host smart-fb136607-4538-4dde-be58-db8049643bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980613483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
980613483
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2704371270
Short name T109
Test name
Test status
Simulation time 54014949 ps
CPU time 1.74 seconds
Started Jul 30 05:26:16 PM PDT 24
Finished Jul 30 05:26:18 PM PDT 24
Peak memory 215188 kb
Host smart-3fe82e8a-2886-403e-b967-ad0ebabdaed4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704371270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2704371270
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1260550085
Short name T1022
Test name
Test status
Simulation time 41371049 ps
CPU time 0.68 seconds
Started Jul 30 05:26:15 PM PDT 24
Finished Jul 30 05:26:16 PM PDT 24
Peak memory 203616 kb
Host smart-5799f0fe-b52f-47d6-abbf-4867c9256137
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260550085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1260550085
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2602870348
Short name T1016
Test name
Test status
Simulation time 42412622 ps
CPU time 2.88 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 215108 kb
Host smart-b68a1512-0bdd-442a-b3ab-921128b1308c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602870348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2602870348
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3796359061
Short name T92
Test name
Test status
Simulation time 120631623 ps
CPU time 4.09 seconds
Started Jul 30 05:26:20 PM PDT 24
Finished Jul 30 05:26:24 PM PDT 24
Peak memory 215352 kb
Host smart-ce2489c8-6dbe-49d8-9384-3f9e3458cecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796359061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
796359061
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.819122927
Short name T1077
Test name
Test status
Simulation time 710545693 ps
CPU time 17.3 seconds
Started Jul 30 05:26:15 PM PDT 24
Finished Jul 30 05:26:33 PM PDT 24
Peak memory 215244 kb
Host smart-f7c75008-c1ee-4c9b-8e65-71fd571cdca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819122927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.819122927
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.22159084
Short name T1076
Test name
Test status
Simulation time 16313051 ps
CPU time 0.77 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:44 PM PDT 24
Peak memory 203548 kb
Host smart-38e51f24-b5a0-433d-a524-2faa7dc2188b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.22159084
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1231997862
Short name T1009
Test name
Test status
Simulation time 27537212 ps
CPU time 0.76 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 203652 kb
Host smart-ab500f80-0543-4e05-8f69-eb59b507b21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231997862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1231997862
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1638207294
Short name T1010
Test name
Test status
Simulation time 16109285 ps
CPU time 0.75 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:46 PM PDT 24
Peak memory 203976 kb
Host smart-76fb3da1-d845-4770-a76f-6886228bae53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638207294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1638207294
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2747608292
Short name T1031
Test name
Test status
Simulation time 19016572 ps
CPU time 0.74 seconds
Started Jul 30 05:26:47 PM PDT 24
Finished Jul 30 05:26:48 PM PDT 24
Peak memory 203664 kb
Host smart-5ddb2e08-f2ed-400b-958d-6f48b8c41860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747608292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2747608292
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2247082486
Short name T1035
Test name
Test status
Simulation time 40854372 ps
CPU time 0.75 seconds
Started Jul 30 05:26:40 PM PDT 24
Finished Jul 30 05:26:40 PM PDT 24
Peak memory 203656 kb
Host smart-0f9ad575-ba11-429a-9ef8-a4527f68d5e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247082486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2247082486
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4023219005
Short name T1021
Test name
Test status
Simulation time 39766606 ps
CPU time 0.73 seconds
Started Jul 30 05:26:40 PM PDT 24
Finished Jul 30 05:26:41 PM PDT 24
Peak memory 203664 kb
Host smart-45fbbe8c-5d2b-4c1f-b622-4867287bc0b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023219005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4023219005
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3156314840
Short name T1045
Test name
Test status
Simulation time 66250542 ps
CPU time 0.77 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 203688 kb
Host smart-16f08422-3866-4040-8015-564a21a3f78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156314840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3156314840
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3880327665
Short name T1041
Test name
Test status
Simulation time 13052568 ps
CPU time 0.71 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203976 kb
Host smart-3fb322c0-71d1-4838-95cf-246ce610f144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880327665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3880327665
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.242066867
Short name T1018
Test name
Test status
Simulation time 67961338 ps
CPU time 0.76 seconds
Started Jul 30 05:26:41 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 203596 kb
Host smart-9f43ff50-e718-4e34-97e3-d0f12c8c9e51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242066867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.242066867
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2663173697
Short name T1020
Test name
Test status
Simulation time 47993257 ps
CPU time 0.76 seconds
Started Jul 30 05:26:42 PM PDT 24
Finished Jul 30 05:26:43 PM PDT 24
Peak memory 203664 kb
Host smart-2f113c2f-6ed6-4092-a6f4-56aa8001ed3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663173697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2663173697
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2597893375
Short name T111
Test name
Test status
Simulation time 1270929793 ps
CPU time 7.56 seconds
Started Jul 30 05:26:15 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 206860 kb
Host smart-a034f3a9-2784-48cc-a496-66d757285cc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597893375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2597893375
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3716126948
Short name T1124
Test name
Test status
Simulation time 9202056098 ps
CPU time 25.62 seconds
Started Jul 30 05:26:16 PM PDT 24
Finished Jul 30 05:26:42 PM PDT 24
Peak memory 206976 kb
Host smart-b294dcc5-bab4-4e56-836f-ef381f3d7125
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716126948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3716126948
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.86581923
Short name T72
Test name
Test status
Simulation time 135760165 ps
CPU time 1.21 seconds
Started Jul 30 05:26:15 PM PDT 24
Finished Jul 30 05:26:16 PM PDT 24
Peak memory 206820 kb
Host smart-943355f8-4645-4901-8510-d7c7bdb178af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86581923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
hw_reset.86581923
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3964673878
Short name T1069
Test name
Test status
Simulation time 834198791 ps
CPU time 2.9 seconds
Started Jul 30 05:26:26 PM PDT 24
Finished Jul 30 05:26:29 PM PDT 24
Peak memory 217000 kb
Host smart-936f0f62-3d4c-4231-8bb3-22b9aeec0673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964673878 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3964673878
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4022959828
Short name T1078
Test name
Test status
Simulation time 143113754 ps
CPU time 1.33 seconds
Started Jul 30 05:26:22 PM PDT 24
Finished Jul 30 05:26:23 PM PDT 24
Peak memory 215288 kb
Host smart-a9ce0ab6-cfcd-4fcf-ba0a-d90ea4ff37b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022959828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
022959828
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3006960338
Short name T1059
Test name
Test status
Simulation time 46037336 ps
CPU time 0.86 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:18 PM PDT 24
Peak memory 203860 kb
Host smart-5267d510-e8ac-4cc0-8b48-655792b50710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006960338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
006960338
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3112652907
Short name T116
Test name
Test status
Simulation time 46109794 ps
CPU time 1.8 seconds
Started Jul 30 05:26:13 PM PDT 24
Finished Jul 30 05:26:15 PM PDT 24
Peak memory 215312 kb
Host smart-058edb3f-0de3-4e0f-bb47-e8e6e8795767
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112652907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3112652907
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1869448270
Short name T1111
Test name
Test status
Simulation time 112934715 ps
CPU time 0.68 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:18 PM PDT 24
Peak memory 203600 kb
Host smart-02678f4f-ad3c-43d1-818c-c16ca7ce7745
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869448270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1869448270
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1813814838
Short name T132
Test name
Test status
Simulation time 61567430 ps
CPU time 3.74 seconds
Started Jul 30 05:26:16 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 215188 kb
Host smart-16a6ead6-918c-40c0-947b-f25142fc3f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813814838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1813814838
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3172830378
Short name T51
Test name
Test status
Simulation time 181401347 ps
CPU time 2.84 seconds
Started Jul 30 05:26:21 PM PDT 24
Finished Jul 30 05:26:24 PM PDT 24
Peak memory 215348 kb
Host smart-5443c7cf-8847-45c4-98fd-b4668c3503c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172830378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
172830378
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3880357405
Short name T1098
Test name
Test status
Simulation time 709597489 ps
CPU time 16.48 seconds
Started Jul 30 05:26:19 PM PDT 24
Finished Jul 30 05:26:35 PM PDT 24
Peak memory 216780 kb
Host smart-878820dc-6700-4b41-8199-4e9047e06793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880357405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3880357405
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2010212882
Short name T1091
Test name
Test status
Simulation time 144016800 ps
CPU time 0.76 seconds
Started Jul 30 05:26:43 PM PDT 24
Finished Jul 30 05:26:44 PM PDT 24
Peak memory 203664 kb
Host smart-5163a2f2-fe4e-4b60-9292-075caea9f134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010212882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2010212882
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2826434331
Short name T1036
Test name
Test status
Simulation time 46482901 ps
CPU time 0.73 seconds
Started Jul 30 05:26:43 PM PDT 24
Finished Jul 30 05:26:43 PM PDT 24
Peak memory 203668 kb
Host smart-63b3ea59-5652-41c4-b1ee-4db23228c283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826434331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2826434331
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.603549470
Short name T1046
Test name
Test status
Simulation time 72408769 ps
CPU time 0.77 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203680 kb
Host smart-2693a039-472b-44a2-9a85-d38ab41685cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603549470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.603549470
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.342481802
Short name T1066
Test name
Test status
Simulation time 20447882 ps
CPU time 0.76 seconds
Started Jul 30 05:26:43 PM PDT 24
Finished Jul 30 05:26:44 PM PDT 24
Peak memory 203476 kb
Host smart-af454c71-54c2-4335-a6a3-edafb2544ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342481802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.342481802
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3107187893
Short name T1088
Test name
Test status
Simulation time 37346877 ps
CPU time 0.72 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203644 kb
Host smart-d6d48d37-fcc3-4f37-aecb-5b82c022af0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107187893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3107187893
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2295907184
Short name T1017
Test name
Test status
Simulation time 28596896 ps
CPU time 0.73 seconds
Started Jul 30 05:26:45 PM PDT 24
Finished Jul 30 05:26:46 PM PDT 24
Peak memory 203620 kb
Host smart-2c92a6df-acd7-40af-9add-9ac95ae4be18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295907184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2295907184
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.592849056
Short name T1130
Test name
Test status
Simulation time 55187194 ps
CPU time 0.73 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:26:54 PM PDT 24
Peak memory 203564 kb
Host smart-8674160e-a781-42e0-b2c9-4dba5984f6eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592849056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.592849056
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4293369740
Short name T1072
Test name
Test status
Simulation time 23635605 ps
CPU time 0.77 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 203636 kb
Host smart-e1d26a68-566c-4927-941e-2e12cd745b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293369740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4293369740
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2424842224
Short name T1068
Test name
Test status
Simulation time 35194436 ps
CPU time 0.73 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203968 kb
Host smart-eedc5b8f-7531-42e3-9812-f9c38fff9d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424842224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2424842224
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.558450595
Short name T1037
Test name
Test status
Simulation time 43421102 ps
CPU time 0.76 seconds
Started Jul 30 05:26:43 PM PDT 24
Finished Jul 30 05:26:44 PM PDT 24
Peak memory 203648 kb
Host smart-9fe11ed7-e5f6-42ae-8018-140a425a5aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558450595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.558450595
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3484948575
Short name T1025
Test name
Test status
Simulation time 432615944 ps
CPU time 8.22 seconds
Started Jul 30 05:26:15 PM PDT 24
Finished Jul 30 05:26:23 PM PDT 24
Peak memory 206832 kb
Host smart-e9d7e65d-327f-43d3-8553-0ab4480ef224
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484948575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3484948575
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.405222495
Short name T1112
Test name
Test status
Simulation time 6736326737 ps
CPU time 14.59 seconds
Started Jul 30 05:26:16 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 207012 kb
Host smart-4379b378-db9d-4c1c-85cc-c0fa355fd522
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405222495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.405222495
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.732128595
Short name T1064
Test name
Test status
Simulation time 221528162 ps
CPU time 1.79 seconds
Started Jul 30 05:26:16 PM PDT 24
Finished Jul 30 05:26:18 PM PDT 24
Peak memory 215264 kb
Host smart-4c8bd44c-4d43-4022-8a78-26841a0d2ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732128595 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.732128595
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3254837373
Short name T1115
Test name
Test status
Simulation time 214791492 ps
CPU time 2.39 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:21 PM PDT 24
Peak memory 215232 kb
Host smart-e9e31686-6d1c-4564-bdaa-f2c4c354a924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254837373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
254837373
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1342366039
Short name T1110
Test name
Test status
Simulation time 42343611 ps
CPU time 0.75 seconds
Started Jul 30 05:26:21 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 203624 kb
Host smart-1b40236e-e83b-477c-9d8c-56de007dd883
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342366039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
342366039
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3087999798
Short name T115
Test name
Test status
Simulation time 129436436 ps
CPU time 1.33 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 214956 kb
Host smart-28b9601d-44a7-4554-b172-b29e06cfb1ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087999798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3087999798
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1906578176
Short name T1101
Test name
Test status
Simulation time 10761783 ps
CPU time 0.67 seconds
Started Jul 30 05:26:22 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 203576 kb
Host smart-ba511d42-2a9f-43ad-837a-e29a25f3de41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906578176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1906578176
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.296715739
Short name T1060
Test name
Test status
Simulation time 29306689 ps
CPU time 1.67 seconds
Started Jul 30 05:26:12 PM PDT 24
Finished Jul 30 05:26:14 PM PDT 24
Peak memory 215792 kb
Host smart-78f0e72a-e02b-4716-ba68-8b8af2e0e8a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296715739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.296715739
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3199147397
Short name T1070
Test name
Test status
Simulation time 261147179 ps
CPU time 4.32 seconds
Started Jul 30 05:26:21 PM PDT 24
Finished Jul 30 05:26:26 PM PDT 24
Peak memory 215280 kb
Host smart-a8e752e0-1718-4ec0-b9ea-ee124094d741
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199147397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
199147397
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.706869697
Short name T156
Test name
Test status
Simulation time 2564832077 ps
CPU time 13.54 seconds
Started Jul 30 05:26:20 PM PDT 24
Finished Jul 30 05:26:33 PM PDT 24
Peak memory 215448 kb
Host smart-e68ca671-2e0c-4f04-a2d1-5c59e4b1a3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706869697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.706869697
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3116879359
Short name T1094
Test name
Test status
Simulation time 25147053 ps
CPU time 0.77 seconds
Started Jul 30 05:26:47 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203940 kb
Host smart-6cb4d948-66b1-426c-99fe-1294bd118b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116879359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3116879359
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3163644153
Short name T1109
Test name
Test status
Simulation time 11419274 ps
CPU time 0.84 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 203708 kb
Host smart-8935e7ce-a071-4b82-8594-f98525aafbe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163644153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3163644153
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3667688802
Short name T1052
Test name
Test status
Simulation time 48867140 ps
CPU time 0.74 seconds
Started Jul 30 05:26:45 PM PDT 24
Finished Jul 30 05:26:46 PM PDT 24
Peak memory 203972 kb
Host smart-71cc80e7-3d64-4577-8177-f67fcc9ccad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667688802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3667688802
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1558585708
Short name T1104
Test name
Test status
Simulation time 14946693 ps
CPU time 0.74 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:46 PM PDT 24
Peak memory 203940 kb
Host smart-1f53727d-42d0-4bab-8ffe-97c3104cbb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558585708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1558585708
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1195560320
Short name T1006
Test name
Test status
Simulation time 12726309 ps
CPU time 0.75 seconds
Started Jul 30 05:26:53 PM PDT 24
Finished Jul 30 05:26:54 PM PDT 24
Peak memory 203872 kb
Host smart-3dc849bf-3db1-4421-9b45-995b241e55a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195560320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1195560320
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1773946355
Short name T1100
Test name
Test status
Simulation time 17671087 ps
CPU time 0.78 seconds
Started Jul 30 05:26:46 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203616 kb
Host smart-db7e3ce7-2232-42ea-ac46-5688100c2907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773946355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1773946355
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.571879647
Short name T1023
Test name
Test status
Simulation time 51862151 ps
CPU time 0.77 seconds
Started Jul 30 05:26:44 PM PDT 24
Finished Jul 30 05:26:45 PM PDT 24
Peak memory 203668 kb
Host smart-9019c7e8-1778-428c-939d-7c79c953b64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571879647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.571879647
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2167293391
Short name T1105
Test name
Test status
Simulation time 22754756 ps
CPU time 0.68 seconds
Started Jul 30 05:26:47 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 203612 kb
Host smart-57a7071a-4a5e-4cd4-acba-239047073ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167293391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2167293391
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.247668404
Short name T1033
Test name
Test status
Simulation time 35748449 ps
CPU time 0.73 seconds
Started Jul 30 05:26:51 PM PDT 24
Finished Jul 30 05:26:52 PM PDT 24
Peak memory 203720 kb
Host smart-33bc516e-2678-4310-b3f6-0cf4d29a64ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247668404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.247668404
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.281079979
Short name T1075
Test name
Test status
Simulation time 52583818 ps
CPU time 0.76 seconds
Started Jul 30 05:26:58 PM PDT 24
Finished Jul 30 05:26:59 PM PDT 24
Peak memory 203676 kb
Host smart-5128ae87-d561-4e4d-a3ed-70b033249e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281079979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.281079979
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.876986039
Short name T1096
Test name
Test status
Simulation time 50414529 ps
CPU time 1.66 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 215224 kb
Host smart-87639c3c-e67a-4cf1-9ad8-cf6a76711a1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876986039 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.876986039
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2612960553
Short name T117
Test name
Test status
Simulation time 245106010 ps
CPU time 1.38 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:18 PM PDT 24
Peak memory 215120 kb
Host smart-e69bacff-aba9-47ee-8a40-1d51e8034a60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612960553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
612960553
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.48999930
Short name T1034
Test name
Test status
Simulation time 29407908 ps
CPU time 0.75 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 203600 kb
Host smart-cc839bcf-49fc-4b16-9ccc-841b1c157526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48999930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.48999930
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2122811533
Short name T1085
Test name
Test status
Simulation time 53784989 ps
CPU time 3.5 seconds
Started Jul 30 05:26:19 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 215176 kb
Host smart-e87b1a7d-5398-45ba-9b22-ec9412374e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122811533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2122811533
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1651734666
Short name T1121
Test name
Test status
Simulation time 186321569 ps
CPU time 2.46 seconds
Started Jul 30 05:26:21 PM PDT 24
Finished Jul 30 05:26:23 PM PDT 24
Peak memory 215180 kb
Host smart-4f56b336-057d-45e7-91a9-8ad9b1b7786d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651734666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
651734666
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1967887840
Short name T1043
Test name
Test status
Simulation time 478636989 ps
CPU time 6.57 seconds
Started Jul 30 05:26:19 PM PDT 24
Finished Jul 30 05:26:26 PM PDT 24
Peak memory 215192 kb
Host smart-8f366543-8c62-46dc-afa6-b523efe1871d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967887840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1967887840
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3880312615
Short name T1108
Test name
Test status
Simulation time 89872945 ps
CPU time 2.64 seconds
Started Jul 30 05:26:19 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 216316 kb
Host smart-2d402436-e31a-488a-a4d9-09c90b869aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880312615 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3880312615
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2984490671
Short name T114
Test name
Test status
Simulation time 147428432 ps
CPU time 2.04 seconds
Started Jul 30 05:26:20 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 215120 kb
Host smart-a00e5bdd-d2d0-4689-9c1b-321cc2891c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984490671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
984490671
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.955081047
Short name T1073
Test name
Test status
Simulation time 15116709 ps
CPU time 0.74 seconds
Started Jul 30 05:26:19 PM PDT 24
Finished Jul 30 05:26:19 PM PDT 24
Peak memory 203628 kb
Host smart-f68a7383-92cf-4888-91c0-a21db0a55b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955081047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.955081047
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4285238984
Short name T140
Test name
Test status
Simulation time 226841845 ps
CPU time 2.89 seconds
Started Jul 30 05:26:19 PM PDT 24
Finished Jul 30 05:26:22 PM PDT 24
Peak memory 215200 kb
Host smart-02faf354-7e0f-4c7c-9649-0361099e6911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285238984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4285238984
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1184082555
Short name T1053
Test name
Test status
Simulation time 108193341 ps
CPU time 2.05 seconds
Started Jul 30 05:26:20 PM PDT 24
Finished Jul 30 05:26:23 PM PDT 24
Peak memory 215372 kb
Host smart-44dba334-cb1f-41c4-8a1b-dc3b5e21c7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184082555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
184082555
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1556359579
Short name T98
Test name
Test status
Simulation time 969558203 ps
CPU time 20.28 seconds
Started Jul 30 05:26:17 PM PDT 24
Finished Jul 30 05:26:37 PM PDT 24
Peak memory 215220 kb
Host smart-15199794-0d09-497d-9e6a-80109f380de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556359579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1556359579
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4048481958
Short name T1058
Test name
Test status
Simulation time 203359397 ps
CPU time 2.96 seconds
Started Jul 30 05:26:26 PM PDT 24
Finished Jul 30 05:26:29 PM PDT 24
Peak memory 217840 kb
Host smart-b45fe91f-a241-4ee5-a583-0e06128f8e5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048481958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4048481958
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2319228226
Short name T1102
Test name
Test status
Simulation time 92179059 ps
CPU time 1.77 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 215148 kb
Host smart-6db63d8e-55b9-4b7f-97e5-847716c06e22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319228226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
319228226
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1079797662
Short name T1079
Test name
Test status
Simulation time 37521717 ps
CPU time 0.75 seconds
Started Jul 30 05:26:20 PM PDT 24
Finished Jul 30 05:26:21 PM PDT 24
Peak memory 203668 kb
Host smart-80340e7d-911f-4f3f-ae05-90289fbe6b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079797662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
079797662
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.598766356
Short name T1071
Test name
Test status
Simulation time 326289080 ps
CPU time 1.88 seconds
Started Jul 30 05:26:23 PM PDT 24
Finished Jul 30 05:26:25 PM PDT 24
Peak memory 215140 kb
Host smart-44c75e53-16c0-46ec-bf4a-b64a872a8fd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598766356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.598766356
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1879271875
Short name T1087
Test name
Test status
Simulation time 180986099 ps
CPU time 2.26 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:20 PM PDT 24
Peak memory 215164 kb
Host smart-2ad46532-69ae-425c-8ae9-d4ee9dacc860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879271875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
879271875
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3568224696
Short name T87
Test name
Test status
Simulation time 409184810 ps
CPU time 6.69 seconds
Started Jul 30 05:26:18 PM PDT 24
Finished Jul 30 05:26:25 PM PDT 24
Peak memory 215184 kb
Host smart-0015382b-75e3-43ef-9bef-02816d38ff61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568224696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3568224696
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.138873453
Short name T97
Test name
Test status
Simulation time 221322354 ps
CPU time 1.92 seconds
Started Jul 30 05:26:24 PM PDT 24
Finished Jul 30 05:26:26 PM PDT 24
Peak memory 215200 kb
Host smart-0202f7c9-1257-45dc-8a6a-1af837320034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138873453 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.138873453
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3217965933
Short name T1090
Test name
Test status
Simulation time 78122927 ps
CPU time 1.38 seconds
Started Jul 30 05:26:25 PM PDT 24
Finished Jul 30 05:26:27 PM PDT 24
Peak memory 215176 kb
Host smart-65452192-8823-4d67-ada3-81ace72ee641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217965933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
217965933
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3414982628
Short name T1012
Test name
Test status
Simulation time 35889036 ps
CPU time 0.92 seconds
Started Jul 30 05:26:25 PM PDT 24
Finished Jul 30 05:26:26 PM PDT 24
Peak memory 203952 kb
Host smart-b49efdb9-5dc4-446c-8e99-035b22ffc320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414982628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
414982628
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2724637653
Short name T1118
Test name
Test status
Simulation time 136596210 ps
CPU time 2.21 seconds
Started Jul 30 05:26:25 PM PDT 24
Finished Jul 30 05:26:27 PM PDT 24
Peak memory 215216 kb
Host smart-9b70024c-6e5b-433c-ba95-a44ecf7e6712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724637653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2724637653
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1422099272
Short name T89
Test name
Test status
Simulation time 877163209 ps
CPU time 4.92 seconds
Started Jul 30 05:26:24 PM PDT 24
Finished Jul 30 05:26:29 PM PDT 24
Peak memory 215288 kb
Host smart-6ea2ec70-c83d-4711-81ab-3c5ecbdac3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422099272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
422099272
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.90763315
Short name T1103
Test name
Test status
Simulation time 529338979 ps
CPU time 3.46 seconds
Started Jul 30 05:26:26 PM PDT 24
Finished Jul 30 05:26:29 PM PDT 24
Peak memory 217680 kb
Host smart-bfb91a41-bf4f-41ee-a8d6-882c75a626e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90763315 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.90763315
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.443851215
Short name T1011
Test name
Test status
Simulation time 591081388 ps
CPU time 1.36 seconds
Started Jul 30 05:26:26 PM PDT 24
Finished Jul 30 05:26:27 PM PDT 24
Peak memory 206936 kb
Host smart-b0cf2671-d75a-4bd5-98eb-c1c3568c6b2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443851215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.443851215
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3268963195
Short name T1026
Test name
Test status
Simulation time 14987234 ps
CPU time 0.73 seconds
Started Jul 30 05:26:25 PM PDT 24
Finished Jul 30 05:26:26 PM PDT 24
Peak memory 203692 kb
Host smart-d94da4a2-9860-4c6d-9e29-26a2dc8ebb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268963195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
268963195
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2371089224
Short name T1044
Test name
Test status
Simulation time 128434809 ps
CPU time 3.97 seconds
Started Jul 30 05:26:24 PM PDT 24
Finished Jul 30 05:26:28 PM PDT 24
Peak memory 215196 kb
Host smart-2238a8c1-d1e0-4353-b7eb-cfdbbe04bc24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371089224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2371089224
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2196390347
Short name T88
Test name
Test status
Simulation time 425525100 ps
CPU time 5.04 seconds
Started Jul 30 05:26:25 PM PDT 24
Finished Jul 30 05:26:30 PM PDT 24
Peak memory 215300 kb
Host smart-a6508913-7e0d-4cc3-9769-b33e8f8f410f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196390347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
196390347
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.89906354
Short name T100
Test name
Test status
Simulation time 261992818 ps
CPU time 6.91 seconds
Started Jul 30 05:26:28 PM PDT 24
Finished Jul 30 05:26:35 PM PDT 24
Peak memory 215128 kb
Host smart-0c9145f5-09b0-4a90-8938-1c384a5b8812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89906354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.89906354
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.302673737
Short name T996
Test name
Test status
Simulation time 15732388 ps
CPU time 0.78 seconds
Started Jul 30 05:11:47 PM PDT 24
Finished Jul 30 05:11:48 PM PDT 24
Peak memory 205236 kb
Host smart-6023178a-d149-42cb-8112-d5f2391e175b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302673737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.302673737
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3461949897
Short name T625
Test name
Test status
Simulation time 482992472 ps
CPU time 2.91 seconds
Started Jul 30 05:11:35 PM PDT 24
Finished Jul 30 05:11:38 PM PDT 24
Peak memory 233128 kb
Host smart-192b883b-01f3-44ea-a57e-f1c125d639b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461949897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3461949897
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1137256492
Short name T981
Test name
Test status
Simulation time 22387918 ps
CPU time 0.85 seconds
Started Jul 30 05:11:39 PM PDT 24
Finished Jul 30 05:11:40 PM PDT 24
Peak memory 207332 kb
Host smart-e7815369-7cf6-4744-ac11-ce4fb15bfeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137256492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1137256492
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3014841463
Short name T970
Test name
Test status
Simulation time 49548114385 ps
CPU time 192.74 seconds
Started Jul 30 05:11:35 PM PDT 24
Finished Jul 30 05:14:48 PM PDT 24
Peak memory 265396 kb
Host smart-ff4bffac-a130-4286-8f67-c2927a21ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014841463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3014841463
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2074289739
Short name T236
Test name
Test status
Simulation time 5109159162 ps
CPU time 33.82 seconds
Started Jul 30 05:11:38 PM PDT 24
Finished Jul 30 05:12:12 PM PDT 24
Peak memory 225016 kb
Host smart-bca90a47-d721-4592-8d73-99b8d2a25a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074289739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2074289739
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.982494137
Short name T414
Test name
Test status
Simulation time 3582245184 ps
CPU time 30.09 seconds
Started Jul 30 05:11:36 PM PDT 24
Finished Jul 30 05:12:06 PM PDT 24
Peak memory 224964 kb
Host smart-e19caab5-55a1-4beb-89d4-30c1200d252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982494137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
982494137
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1917371315
Short name T891
Test name
Test status
Simulation time 9053719457 ps
CPU time 24.65 seconds
Started Jul 30 05:11:37 PM PDT 24
Finished Jul 30 05:12:02 PM PDT 24
Peak memory 224924 kb
Host smart-21f71033-f9e8-4c67-8276-13be4c4da5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917371315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1917371315
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1122005558
Short name T530
Test name
Test status
Simulation time 18728893988 ps
CPU time 37.97 seconds
Started Jul 30 05:11:39 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 249608 kb
Host smart-09369231-13a6-443f-ae25-092d7e8e3bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122005558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1122005558
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3657504518
Short name T518
Test name
Test status
Simulation time 391016223 ps
CPU time 3.55 seconds
Started Jul 30 05:11:38 PM PDT 24
Finished Jul 30 05:11:41 PM PDT 24
Peak memory 233100 kb
Host smart-ed06643d-1a0d-4027-9355-05d1ede65d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657504518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3657504518
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4168080256
Short name T350
Test name
Test status
Simulation time 1928927924 ps
CPU time 20.03 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:12:01 PM PDT 24
Peak memory 224872 kb
Host smart-2fcf2952-d370-4651-8a42-68edfd46a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168080256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4168080256
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.901790669
Short name T834
Test name
Test status
Simulation time 46381561731 ps
CPU time 17.23 seconds
Started Jul 30 05:11:38 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 224968 kb
Host smart-eb8c9be7-a981-47dc-a477-556c6aff06ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901790669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
901790669
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3135800622
Short name T394
Test name
Test status
Simulation time 2920658582 ps
CPU time 5.2 seconds
Started Jul 30 05:11:39 PM PDT 24
Finished Jul 30 05:11:44 PM PDT 24
Peak memory 233224 kb
Host smart-41017114-a1c1-4a06-a359-d68dda538c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135800622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3135800622
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3091339539
Short name T380
Test name
Test status
Simulation time 914442584 ps
CPU time 6.18 seconds
Started Jul 30 05:11:38 PM PDT 24
Finished Jul 30 05:11:44 PM PDT 24
Peak memory 221272 kb
Host smart-c97e090b-a619-463c-8938-17b99940b47f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091339539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3091339539
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.326469661
Short name T56
Test name
Test status
Simulation time 116788838 ps
CPU time 0.95 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:11:42 PM PDT 24
Peak memory 236888 kb
Host smart-d7fe4a54-c565-47c0-bdfd-6585015d7600
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326469661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.326469661
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2125974869
Short name T19
Test name
Test status
Simulation time 348156054 ps
CPU time 1 seconds
Started Jul 30 05:11:40 PM PDT 24
Finished Jul 30 05:11:41 PM PDT 24
Peak memory 206300 kb
Host smart-00ac7fe1-7660-4c90-be5f-55883b7ab2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125974869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2125974869
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1471436617
Short name T734
Test name
Test status
Simulation time 22080015 ps
CPU time 0.74 seconds
Started Jul 30 05:11:37 PM PDT 24
Finished Jul 30 05:11:38 PM PDT 24
Peak memory 206068 kb
Host smart-a375d739-a660-45dd-bbc5-96e046727863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471436617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1471436617
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1328766965
Short name T409
Test name
Test status
Simulation time 13041815385 ps
CPU time 9.02 seconds
Started Jul 30 05:11:37 PM PDT 24
Finished Jul 30 05:11:46 PM PDT 24
Peak memory 216708 kb
Host smart-54c3e4d5-bffd-4c33-a806-8f86ded83a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328766965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1328766965
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3522695115
Short name T612
Test name
Test status
Simulation time 40266076 ps
CPU time 0.7 seconds
Started Jul 30 05:11:37 PM PDT 24
Finished Jul 30 05:11:37 PM PDT 24
Peak memory 206008 kb
Host smart-036b9ba3-6e60-4a18-b237-d8bd5c0c0968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522695115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3522695115
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.462877602
Short name T632
Test name
Test status
Simulation time 70621713 ps
CPU time 0.79 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:11:42 PM PDT 24
Peak memory 206392 kb
Host smart-f322d520-5cda-45e9-b51e-b3d0aad68730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462877602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.462877602
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2536094472
Short name T428
Test name
Test status
Simulation time 533797922 ps
CPU time 6.65 seconds
Started Jul 30 05:11:36 PM PDT 24
Finished Jul 30 05:11:43 PM PDT 24
Peak memory 233056 kb
Host smart-84596cbc-b348-4f98-8a5a-e5240d5b40e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536094472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2536094472
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2220361056
Short name T773
Test name
Test status
Simulation time 20365639 ps
CPU time 0.77 seconds
Started Jul 30 05:11:46 PM PDT 24
Finished Jul 30 05:11:47 PM PDT 24
Peak memory 205812 kb
Host smart-692ada63-d5af-4ed2-996a-18ff23448068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220361056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
220361056
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2128107969
Short name T769
Test name
Test status
Simulation time 351692943 ps
CPU time 2.34 seconds
Started Jul 30 05:11:40 PM PDT 24
Finished Jul 30 05:11:43 PM PDT 24
Peak memory 224964 kb
Host smart-9f551efe-20c1-4069-97df-f3564ab965c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128107969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2128107969
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1150013420
Short name T613
Test name
Test status
Simulation time 21518483 ps
CPU time 0.78 seconds
Started Jul 30 05:11:43 PM PDT 24
Finished Jul 30 05:11:44 PM PDT 24
Peak memory 206944 kb
Host smart-aba18f6f-6a35-491f-b166-35b31dfd1444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150013420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1150013420
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3346055884
Short name T152
Test name
Test status
Simulation time 2634151273 ps
CPU time 38.35 seconds
Started Jul 30 05:11:45 PM PDT 24
Finished Jul 30 05:12:24 PM PDT 24
Peak memory 249532 kb
Host smart-65a19c1a-bfdc-4a3b-abaa-d9e56f58a562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346055884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3346055884
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.984638911
Short name T893
Test name
Test status
Simulation time 122636358283 ps
CPU time 312.2 seconds
Started Jul 30 05:11:45 PM PDT 24
Finished Jul 30 05:16:57 PM PDT 24
Peak memory 255716 kb
Host smart-d5b64b13-9ce0-4811-9812-5ed1912d4db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984638911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
984638911
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.495743330
Short name T593
Test name
Test status
Simulation time 48995269618 ps
CPU time 167.87 seconds
Started Jul 30 05:11:40 PM PDT 24
Finished Jul 30 05:14:28 PM PDT 24
Peak memory 255088 kb
Host smart-775e6c3a-fc21-4706-9d15-b86ceeb5b9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495743330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
495743330
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1748363432
Short name T391
Test name
Test status
Simulation time 1258849327 ps
CPU time 5.1 seconds
Started Jul 30 05:11:39 PM PDT 24
Finished Jul 30 05:11:44 PM PDT 24
Peak memory 233056 kb
Host smart-931b6716-6403-4d50-85c3-3c0976d1dd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748363432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1748363432
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3700614450
Short name T221
Test name
Test status
Simulation time 1198492203 ps
CPU time 19.84 seconds
Started Jul 30 05:11:42 PM PDT 24
Finished Jul 30 05:12:02 PM PDT 24
Peak memory 233164 kb
Host smart-67716952-3165-4f7f-a743-771e83b2bc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700614450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3700614450
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2432401001
Short name T554
Test name
Test status
Simulation time 1999912434 ps
CPU time 5.03 seconds
Started Jul 30 05:11:47 PM PDT 24
Finished Jul 30 05:11:52 PM PDT 24
Peak memory 224844 kb
Host smart-457c2fd2-61de-45b5-8951-311260bf85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432401001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2432401001
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4255565216
Short name T890
Test name
Test status
Simulation time 61765360656 ps
CPU time 17.08 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:11:58 PM PDT 24
Peak memory 225020 kb
Host smart-d39c9a76-84e4-4196-b403-e79afc5b7694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255565216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4255565216
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2045306296
Short name T758
Test name
Test status
Simulation time 1465564553 ps
CPU time 5.56 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:11:47 PM PDT 24
Peak memory 223088 kb
Host smart-8427e521-6fdd-423d-b84b-1194b30d378b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2045306296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2045306296
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2434876076
Short name T54
Test name
Test status
Simulation time 107524629 ps
CPU time 1.08 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:52 PM PDT 24
Peak memory 236276 kb
Host smart-55d5ee2f-a556-47ff-8741-5d3fe23afa04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434876076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2434876076
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3427354669
Short name T538
Test name
Test status
Simulation time 50011278 ps
CPU time 0.99 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 207920 kb
Host smart-0b1ca13e-3502-4e66-8fa3-a90ea53f2d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427354669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3427354669
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.86569090
Short name T915
Test name
Test status
Simulation time 58999967294 ps
CPU time 40.3 seconds
Started Jul 30 05:11:43 PM PDT 24
Finished Jul 30 05:12:23 PM PDT 24
Peak memory 216728 kb
Host smart-90985269-c6f1-437f-8ab3-556521c8ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86569090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.86569090
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4159707943
Short name T881
Test name
Test status
Simulation time 3009337146 ps
CPU time 8.37 seconds
Started Jul 30 05:11:42 PM PDT 24
Finished Jul 30 05:11:51 PM PDT 24
Peak memory 216656 kb
Host smart-348d44b9-f684-4642-acf2-1b69fe66eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159707943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4159707943
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1968537679
Short name T1003
Test name
Test status
Simulation time 174286433 ps
CPU time 3.81 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:11:44 PM PDT 24
Peak memory 216636 kb
Host smart-ad4068bc-41ce-46c1-b429-6436ced08d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968537679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1968537679
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.169715196
Short name T315
Test name
Test status
Simulation time 41720273 ps
CPU time 0.8 seconds
Started Jul 30 05:11:41 PM PDT 24
Finished Jul 30 05:11:42 PM PDT 24
Peak memory 206220 kb
Host smart-6fcaef13-f647-4586-aee7-e2be2297f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169715196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.169715196
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.704702625
Short name T202
Test name
Test status
Simulation time 60975719 ps
CPU time 2.68 seconds
Started Jul 30 05:11:40 PM PDT 24
Finished Jul 30 05:11:42 PM PDT 24
Peak memory 233092 kb
Host smart-919a6e91-8bcb-40ef-bb73-37d678bbec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704702625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.704702625
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.738448503
Short name T439
Test name
Test status
Simulation time 37795036 ps
CPU time 0.71 seconds
Started Jul 30 05:12:19 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 206180 kb
Host smart-939a0fdd-9cd3-4609-af7f-88da0b01f84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738448503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.738448503
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3256916801
Short name T634
Test name
Test status
Simulation time 71224906 ps
CPU time 2.53 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:12:27 PM PDT 24
Peak memory 233076 kb
Host smart-61bc5d59-b072-4a8c-888c-aecc6fabb616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256916801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3256916801
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1622439483
Short name T123
Test name
Test status
Simulation time 17356727 ps
CPU time 0.76 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:16 PM PDT 24
Peak memory 205912 kb
Host smart-ef63b511-c375-425b-a558-33fa827e893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622439483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1622439483
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.711748406
Short name T781
Test name
Test status
Simulation time 11101314524 ps
CPU time 137.49 seconds
Started Jul 30 05:12:19 PM PDT 24
Finished Jul 30 05:14:37 PM PDT 24
Peak memory 250020 kb
Host smart-9a0c6378-af4a-451c-9e6c-37ad2ee9266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711748406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.711748406
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3748797968
Short name T939
Test name
Test status
Simulation time 39690043327 ps
CPU time 340.69 seconds
Started Jul 30 05:12:22 PM PDT 24
Finished Jul 30 05:18:03 PM PDT 24
Peak memory 256604 kb
Host smart-9645ed6b-6926-4a76-b4ba-65acf438e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748797968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3748797968
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2048838105
Short name T260
Test name
Test status
Simulation time 50439888488 ps
CPU time 360.94 seconds
Started Jul 30 05:12:19 PM PDT 24
Finished Jul 30 05:18:20 PM PDT 24
Peak memory 265980 kb
Host smart-612188cf-410f-4c8b-bead-7ef12bd44fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048838105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2048838105
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2524636835
Short name T860
Test name
Test status
Simulation time 720480899 ps
CPU time 7.85 seconds
Started Jul 30 05:12:21 PM PDT 24
Finished Jul 30 05:12:29 PM PDT 24
Peak memory 233080 kb
Host smart-85671d21-da21-4530-b87d-a9a8a582f77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524636835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2524636835
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1993080974
Short name T157
Test name
Test status
Simulation time 37097756244 ps
CPU time 243.53 seconds
Started Jul 30 05:12:21 PM PDT 24
Finished Jul 30 05:16:24 PM PDT 24
Peak memory 249584 kb
Host smart-7f96a25c-ecaf-4e80-8686-96e971e594de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993080974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1993080974
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.631390356
Short name T546
Test name
Test status
Simulation time 258538403 ps
CPU time 2.34 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 224496 kb
Host smart-0672fc1b-577e-4142-af5f-a247ee58c288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631390356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.631390356
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2537040286
Short name T889
Test name
Test status
Simulation time 4311922333 ps
CPU time 39.61 seconds
Started Jul 30 05:12:20 PM PDT 24
Finished Jul 30 05:12:59 PM PDT 24
Peak memory 233164 kb
Host smart-df0e40af-bc6c-4d9d-b91c-68d56bbe1f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537040286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2537040286
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.712726047
Short name T237
Test name
Test status
Simulation time 4356739366 ps
CPU time 12.86 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:27 PM PDT 24
Peak memory 239908 kb
Host smart-662a48f4-2200-448f-86ad-e2d6925adfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712726047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.712726047
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.327764067
Short name T899
Test name
Test status
Simulation time 39876351627 ps
CPU time 24.7 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:40 PM PDT 24
Peak memory 233132 kb
Host smart-ddadde36-b1b0-42cc-b05a-30a95effa66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327764067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.327764067
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1741976362
Short name T832
Test name
Test status
Simulation time 2957632357 ps
CPU time 10.56 seconds
Started Jul 30 05:12:20 PM PDT 24
Finished Jul 30 05:12:31 PM PDT 24
Peak memory 223588 kb
Host smart-1ff0e00c-4822-444d-acac-07aaa133a590
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1741976362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1741976362
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.408340525
Short name T399
Test name
Test status
Simulation time 11655769368 ps
CPU time 30.52 seconds
Started Jul 30 05:12:22 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 224972 kb
Host smart-3bd93b2f-c28d-456d-9426-bdfcb5e9a943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408340525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.408340525
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2456208352
Short name T342
Test name
Test status
Simulation time 3500546894 ps
CPU time 17.75 seconds
Started Jul 30 05:12:23 PM PDT 24
Finished Jul 30 05:12:41 PM PDT 24
Peak memory 220680 kb
Host smart-059f2124-ee36-42a9-8d03-3c68c8f4c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456208352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2456208352
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1761781663
Short name T541
Test name
Test status
Simulation time 1577037185 ps
CPU time 4.79 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 216684 kb
Host smart-bb2d0f68-7bc0-40c9-a3f0-fe68274f7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761781663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1761781663
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3667661971
Short name T506
Test name
Test status
Simulation time 267635964 ps
CPU time 3.54 seconds
Started Jul 30 05:12:16 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 216628 kb
Host smart-6137f05c-7138-491f-ac47-f658a79f849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667661971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3667661971
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3573471485
Short name T800
Test name
Test status
Simulation time 107826638 ps
CPU time 1.02 seconds
Started Jul 30 05:12:16 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 206348 kb
Host smart-dd4ab4f2-d111-4612-b3fa-4b26b5fd495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573471485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3573471485
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3450723289
Short name T347
Test name
Test status
Simulation time 13705868548 ps
CPU time 10.78 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:25 PM PDT 24
Peak memory 233188 kb
Host smart-59846cfc-f390-4251-844f-d6ac0fb0ee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450723289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3450723289
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2685016227
Short name T410
Test name
Test status
Simulation time 192659748 ps
CPU time 0.72 seconds
Started Jul 30 05:12:27 PM PDT 24
Finished Jul 30 05:12:28 PM PDT 24
Peak memory 206144 kb
Host smart-fe1de2af-55cc-4c16-8dd6-c351a0130fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685016227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2685016227
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3007744471
Short name T702
Test name
Test status
Simulation time 69612513 ps
CPU time 0.78 seconds
Started Jul 30 05:12:22 PM PDT 24
Finished Jul 30 05:12:23 PM PDT 24
Peak memory 206984 kb
Host smart-11c04ac4-a502-45dc-be92-ee77886667fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007744471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3007744471
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3365930715
Short name T165
Test name
Test status
Simulation time 6125074770 ps
CPU time 41.44 seconds
Started Jul 30 05:12:23 PM PDT 24
Finished Jul 30 05:13:04 PM PDT 24
Peak memory 250944 kb
Host smart-0a915f35-a0bc-4e0f-8298-5b2309cf5946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365930715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3365930715
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1106526778
Short name T628
Test name
Test status
Simulation time 4867434487 ps
CPU time 50.21 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:13:15 PM PDT 24
Peak memory 239484 kb
Host smart-94a2b5a8-0e86-41a3-9ff8-582c54687b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106526778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1106526778
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1136120560
Short name T833
Test name
Test status
Simulation time 2687548051 ps
CPU time 59.19 seconds
Started Jul 30 05:12:23 PM PDT 24
Finished Jul 30 05:13:22 PM PDT 24
Peak memory 250040 kb
Host smart-c5d18c04-1e6e-481a-8cdf-2592fb6de5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136120560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1136120560
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1373250388
Short name T139
Test name
Test status
Simulation time 23110792309 ps
CPU time 48.91 seconds
Started Jul 30 05:12:25 PM PDT 24
Finished Jul 30 05:13:14 PM PDT 24
Peak memory 249572 kb
Host smart-1cf9195d-c5d2-461e-99b6-8ff4a350e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373250388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1373250388
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2799514119
Short name T916
Test name
Test status
Simulation time 519107474 ps
CPU time 7.59 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:12:32 PM PDT 24
Peak memory 224944 kb
Host smart-e458eca2-c747-4353-b0ed-361df54e0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799514119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2799514119
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1720658949
Short name T640
Test name
Test status
Simulation time 1108882283 ps
CPU time 13.15 seconds
Started Jul 30 05:12:26 PM PDT 24
Finished Jul 30 05:12:40 PM PDT 24
Peak memory 233172 kb
Host smart-e4713439-eb1b-4f0a-82eb-ad2db012dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720658949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1720658949
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2540922243
Short name T228
Test name
Test status
Simulation time 290057367 ps
CPU time 6.9 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:12:31 PM PDT 24
Peak memory 224832 kb
Host smart-cece3ca4-f29f-4f2c-b954-1c8b5d584706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540922243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2540922243
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1783321998
Short name T671
Test name
Test status
Simulation time 11548955190 ps
CPU time 11.7 seconds
Started Jul 30 05:12:25 PM PDT 24
Finished Jul 30 05:12:37 PM PDT 24
Peak memory 233152 kb
Host smart-581fd04a-453e-4f9c-9092-ea835b2c170a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783321998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1783321998
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3036403213
Short name T511
Test name
Test status
Simulation time 37304390 ps
CPU time 2.36 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:12:26 PM PDT 24
Peak memory 224884 kb
Host smart-d78fc006-1504-41cc-9b17-dfde77b7d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036403213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3036403213
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1076919216
Short name T135
Test name
Test status
Simulation time 4863014726 ps
CPU time 12.5 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:12:36 PM PDT 24
Peak memory 220664 kb
Host smart-17310854-4492-499b-ac4b-475e485677b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076919216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1076919216
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4081113000
Short name T131
Test name
Test status
Simulation time 93221583022 ps
CPU time 861.1 seconds
Started Jul 30 05:12:26 PM PDT 24
Finished Jul 30 05:26:47 PM PDT 24
Peak memory 306344 kb
Host smart-719ad0e6-d77f-4b0c-bc9a-498af3c98ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081113000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4081113000
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1981738005
Short name T723
Test name
Test status
Simulation time 5364260062 ps
CPU time 22.19 seconds
Started Jul 30 05:12:21 PM PDT 24
Finished Jul 30 05:12:44 PM PDT 24
Peak memory 216980 kb
Host smart-4aa883cc-1d47-4c68-a698-23ad8965caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981738005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1981738005
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2784966176
Short name T487
Test name
Test status
Simulation time 2009989084 ps
CPU time 3.61 seconds
Started Jul 30 05:12:20 PM PDT 24
Finished Jul 30 05:12:24 PM PDT 24
Peak memory 216656 kb
Host smart-a9432227-eacd-4a4a-a3a5-1688cd32637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784966176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2784966176
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1201451254
Short name T279
Test name
Test status
Simulation time 134699430 ps
CPU time 2.31 seconds
Started Jul 30 05:12:22 PM PDT 24
Finished Jul 30 05:12:24 PM PDT 24
Peak memory 216608 kb
Host smart-189b49c5-b2a3-4c85-afb0-c762213d4f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201451254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1201451254
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2608530869
Short name T433
Test name
Test status
Simulation time 78324888 ps
CPU time 0.77 seconds
Started Jul 30 05:12:22 PM PDT 24
Finished Jul 30 05:12:23 PM PDT 24
Peak memory 206352 kb
Host smart-f02af46a-ba2e-4c8e-9f4a-d012405dd627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608530869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2608530869
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3317945261
Short name T311
Test name
Test status
Simulation time 113387957 ps
CPU time 2.31 seconds
Started Jul 30 05:12:24 PM PDT 24
Finished Jul 30 05:12:26 PM PDT 24
Peak memory 232752 kb
Host smart-e1e29850-312e-4caf-a889-55a99419d8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317945261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3317945261
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2690160055
Short name T442
Test name
Test status
Simulation time 38836377 ps
CPU time 0.73 seconds
Started Jul 30 05:12:27 PM PDT 24
Finished Jul 30 05:12:28 PM PDT 24
Peak memory 205860 kb
Host smart-a4d569ef-5527-4f1c-9ae4-58d1f7a235b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690160055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2690160055
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3565317770
Short name T772
Test name
Test status
Simulation time 40620596 ps
CPU time 2.55 seconds
Started Jul 30 05:12:27 PM PDT 24
Finished Jul 30 05:12:30 PM PDT 24
Peak memory 233080 kb
Host smart-d5c4b17a-434b-4d85-a63e-01a779eab7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565317770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3565317770
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4003625585
Short name T611
Test name
Test status
Simulation time 23077846 ps
CPU time 0.76 seconds
Started Jul 30 05:12:23 PM PDT 24
Finished Jul 30 05:12:24 PM PDT 24
Peak memory 207324 kb
Host smart-2ade4b84-4d34-4921-ad9b-ff4b00f2446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003625585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4003625585
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2946151775
Short name T941
Test name
Test status
Simulation time 3080242334 ps
CPU time 16.22 seconds
Started Jul 30 05:12:28 PM PDT 24
Finished Jul 30 05:12:44 PM PDT 24
Peak memory 236704 kb
Host smart-508be7d8-a317-4b06-8793-ae1e31a807b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946151775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2946151775
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1846133852
Short name T247
Test name
Test status
Simulation time 8364045947 ps
CPU time 129.08 seconds
Started Jul 30 05:12:29 PM PDT 24
Finished Jul 30 05:14:38 PM PDT 24
Peak memory 249660 kb
Host smart-fe1a8799-e5b8-434b-9989-0c4e6b7e7406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846133852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1846133852
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.286701414
Short name T179
Test name
Test status
Simulation time 11410468958 ps
CPU time 70.5 seconds
Started Jul 30 05:12:29 PM PDT 24
Finished Jul 30 05:13:40 PM PDT 24
Peak memory 249596 kb
Host smart-a8f7e487-85f6-4a14-b9c0-8f37a41f581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286701414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.286701414
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2564505018
Short name T24
Test name
Test status
Simulation time 766401238 ps
CPU time 3.73 seconds
Started Jul 30 05:12:28 PM PDT 24
Finished Jul 30 05:12:32 PM PDT 24
Peak memory 224868 kb
Host smart-5d1d7ae6-1713-4abf-b990-5466f9502ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564505018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2564505018
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2203040917
Short name T62
Test name
Test status
Simulation time 12781199803 ps
CPU time 31.13 seconds
Started Jul 30 05:12:28 PM PDT 24
Finished Jul 30 05:13:00 PM PDT 24
Peak memory 237060 kb
Host smart-8be77c62-2cd6-47ab-8db9-fdea9083cbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203040917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2203040917
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.737281277
Short name T711
Test name
Test status
Simulation time 542875238 ps
CPU time 4.97 seconds
Started Jul 30 05:12:27 PM PDT 24
Finished Jul 30 05:12:32 PM PDT 24
Peak memory 224772 kb
Host smart-0cad61ee-5734-49b0-a6c6-1669633573e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737281277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.737281277
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3265334604
Short name T874
Test name
Test status
Simulation time 930186713 ps
CPU time 2.21 seconds
Started Jul 30 05:12:31 PM PDT 24
Finished Jul 30 05:12:33 PM PDT 24
Peak memory 224832 kb
Host smart-f758a83f-b0d4-43e1-a0a7-1721f73eaa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265334604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3265334604
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2686342810
Short name T587
Test name
Test status
Simulation time 3803814482 ps
CPU time 7.59 seconds
Started Jul 30 05:12:31 PM PDT 24
Finished Jul 30 05:12:39 PM PDT 24
Peak memory 220792 kb
Host smart-04a9223f-61c9-4e74-b6be-4ec27a10e2f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686342810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2686342810
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3299865737
Short name T355
Test name
Test status
Simulation time 12669792595 ps
CPU time 111.89 seconds
Started Jul 30 05:12:28 PM PDT 24
Finished Jul 30 05:14:20 PM PDT 24
Peak memory 241384 kb
Host smart-2420ec05-52e3-4e3e-a8d1-8a1316ded70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299865737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3299865737
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4161299612
Short name T618
Test name
Test status
Simulation time 9064854952 ps
CPU time 48.36 seconds
Started Jul 30 05:12:30 PM PDT 24
Finished Jul 30 05:13:18 PM PDT 24
Peak memory 216972 kb
Host smart-4275b8c6-78d6-488e-8cc0-d86f165ac401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161299612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4161299612
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.649662119
Short name T964
Test name
Test status
Simulation time 931289692 ps
CPU time 7.64 seconds
Started Jul 30 05:12:28 PM PDT 24
Finished Jul 30 05:12:35 PM PDT 24
Peak memory 216556 kb
Host smart-6cb34409-7fed-4209-81f1-b297e5c870d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649662119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.649662119
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4146599883
Short name T722
Test name
Test status
Simulation time 41962922 ps
CPU time 0.92 seconds
Started Jul 30 05:12:30 PM PDT 24
Finished Jul 30 05:12:31 PM PDT 24
Peak memory 207336 kb
Host smart-e3cead6d-2d8f-4ee3-85db-f217ca7db93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146599883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4146599883
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.411077602
Short name T326
Test name
Test status
Simulation time 30638526 ps
CPU time 0.88 seconds
Started Jul 30 05:12:31 PM PDT 24
Finished Jul 30 05:12:32 PM PDT 24
Peak memory 206388 kb
Host smart-3a5f3750-b76d-4c4f-a642-93c63b41390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411077602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.411077602
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2478222655
Short name T331
Test name
Test status
Simulation time 10164083188 ps
CPU time 32.65 seconds
Started Jul 30 05:12:26 PM PDT 24
Finished Jul 30 05:12:59 PM PDT 24
Peak memory 224928 kb
Host smart-78d3ea78-15c1-4fbf-a88a-5724482605c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478222655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2478222655
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3088033473
Short name T958
Test name
Test status
Simulation time 33018347 ps
CPU time 2.28 seconds
Started Jul 30 05:12:37 PM PDT 24
Finished Jul 30 05:12:39 PM PDT 24
Peak memory 224940 kb
Host smart-b5415735-0ea4-4872-b678-51caf157e694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088033473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3088033473
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.160968739
Short name T620
Test name
Test status
Simulation time 15891193 ps
CPU time 0.78 seconds
Started Jul 30 05:12:27 PM PDT 24
Finished Jul 30 05:12:28 PM PDT 24
Peak memory 206948 kb
Host smart-1d3a427f-02ab-44f4-9e3d-1b58e16fcac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160968739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.160968739
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2941941424
Short name T69
Test name
Test status
Simulation time 6277946888 ps
CPU time 79.48 seconds
Started Jul 30 05:12:36 PM PDT 24
Finished Jul 30 05:13:56 PM PDT 24
Peak memory 272604 kb
Host smart-2cb1e87f-71c4-4818-9880-13addf5efac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941941424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2941941424
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1981325618
Short name T407
Test name
Test status
Simulation time 2850467378 ps
CPU time 20.88 seconds
Started Jul 30 05:12:33 PM PDT 24
Finished Jul 30 05:12:54 PM PDT 24
Peak memory 218220 kb
Host smart-0cb6cec9-23ae-4d9c-b0f9-2f0e6419419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981325618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1981325618
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3512624224
Short name T422
Test name
Test status
Simulation time 380709499 ps
CPU time 6.77 seconds
Started Jul 30 05:12:33 PM PDT 24
Finished Jul 30 05:12:40 PM PDT 24
Peak memory 232952 kb
Host smart-1f5e7739-f41e-4b19-86ba-46967883c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512624224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3512624224
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1181149238
Short name T986
Test name
Test status
Simulation time 934516493 ps
CPU time 9.99 seconds
Started Jul 30 05:12:38 PM PDT 24
Finished Jul 30 05:12:48 PM PDT 24
Peak memory 224972 kb
Host smart-340313a2-6061-4809-a8d2-56037c4dfb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181149238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1181149238
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3568418604
Short name T498
Test name
Test status
Simulation time 10867433374 ps
CPU time 16.22 seconds
Started Jul 30 05:12:34 PM PDT 24
Finished Jul 30 05:12:50 PM PDT 24
Peak memory 233164 kb
Host smart-1df01ef1-dce6-4427-abb1-adf43c133387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568418604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3568418604
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1875477302
Short name T750
Test name
Test status
Simulation time 13493849912 ps
CPU time 37.9 seconds
Started Jul 30 05:12:37 PM PDT 24
Finished Jul 30 05:13:15 PM PDT 24
Peak memory 233236 kb
Host smart-d28caff6-5cde-4ae4-8d4e-ea0f9451f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875477302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1875477302
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3032704716
Short name T932
Test name
Test status
Simulation time 248530912 ps
CPU time 2.31 seconds
Started Jul 30 05:12:33 PM PDT 24
Finished Jul 30 05:12:35 PM PDT 24
Peak memory 223508 kb
Host smart-6927abfe-5771-407d-ba89-74f487378a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032704716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3032704716
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2343084944
Short name T955
Test name
Test status
Simulation time 338350821 ps
CPU time 3.83 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:39 PM PDT 24
Peak memory 220328 kb
Host smart-475c6241-10c1-4601-9068-9f2644b45e77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2343084944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2343084944
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4075935597
Short name T857
Test name
Test status
Simulation time 146671308 ps
CPU time 1.01 seconds
Started Jul 30 05:12:38 PM PDT 24
Finished Jul 30 05:12:40 PM PDT 24
Peak memory 207548 kb
Host smart-1292e65f-4901-4d14-8ba0-140f9a383f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075935597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4075935597
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2591507051
Short name T989
Test name
Test status
Simulation time 1566127197 ps
CPU time 15.72 seconds
Started Jul 30 05:12:33 PM PDT 24
Finished Jul 30 05:12:49 PM PDT 24
Peak memory 216716 kb
Host smart-38c1ba44-ecae-41e2-8d75-052cb8913bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591507051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2591507051
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.199264119
Short name T819
Test name
Test status
Simulation time 382252131 ps
CPU time 2.89 seconds
Started Jul 30 05:12:32 PM PDT 24
Finished Jul 30 05:12:35 PM PDT 24
Peak memory 216668 kb
Host smart-8a963aca-b83b-4105-9058-d4550bc41137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199264119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.199264119
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1792181508
Short name T645
Test name
Test status
Simulation time 99651140 ps
CPU time 2.01 seconds
Started Jul 30 05:12:33 PM PDT 24
Finished Jul 30 05:12:36 PM PDT 24
Peak memory 208476 kb
Host smart-90861bdd-8c07-4293-a4f5-dac64be5aba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792181508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1792181508
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1534398564
Short name T562
Test name
Test status
Simulation time 276784867 ps
CPU time 0.94 seconds
Started Jul 30 05:12:32 PM PDT 24
Finished Jul 30 05:12:33 PM PDT 24
Peak memory 206340 kb
Host smart-d4d974a1-b424-43f5-b57f-7643b77ce8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534398564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1534398564
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.826182747
Short name T693
Test name
Test status
Simulation time 15422516190 ps
CPU time 11.87 seconds
Started Jul 30 05:12:32 PM PDT 24
Finished Jul 30 05:12:44 PM PDT 24
Peak memory 237136 kb
Host smart-945f8b26-96b9-41fb-a724-6dafc5bdf5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826182747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.826182747
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1760906738
Short name T831
Test name
Test status
Simulation time 68641318 ps
CPU time 0.71 seconds
Started Jul 30 05:12:46 PM PDT 24
Finished Jul 30 05:12:46 PM PDT 24
Peak memory 206136 kb
Host smart-4629bc3b-e641-42a6-af4a-2b703a26403c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760906738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1760906738
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3879633553
Short name T519
Test name
Test status
Simulation time 2594187986 ps
CPU time 8.09 seconds
Started Jul 30 05:12:36 PM PDT 24
Finished Jul 30 05:12:45 PM PDT 24
Peak memory 224936 kb
Host smart-d0344c5e-1349-46f9-9142-5ec6d5188ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879633553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3879633553
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1329803872
Short name T336
Test name
Test status
Simulation time 14494365 ps
CPU time 0.77 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:36 PM PDT 24
Peak memory 206260 kb
Host smart-c07c34a1-1495-4c80-8884-d6c95ebb244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329803872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1329803872
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3232127248
Short name T178
Test name
Test status
Simulation time 5831639592 ps
CPU time 23.89 seconds
Started Jul 30 05:12:39 PM PDT 24
Finished Jul 30 05:13:03 PM PDT 24
Peak memory 249544 kb
Host smart-22dc5301-a9f6-46a2-b053-168761345345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232127248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3232127248
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.216434771
Short name T38
Test name
Test status
Simulation time 266656739 ps
CPU time 5.15 seconds
Started Jul 30 05:12:38 PM PDT 24
Finished Jul 30 05:12:43 PM PDT 24
Peak memory 224980 kb
Host smart-dfbc8cd5-8a79-4727-86f8-d5ab143ff794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216434771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.216434771
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3627517931
Short name T504
Test name
Test status
Simulation time 106843104972 ps
CPU time 213.2 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 257708 kb
Host smart-47296cc3-4c3b-4761-b235-5dd4f1fb846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627517931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3627517931
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3743936274
Short name T171
Test name
Test status
Simulation time 266678565 ps
CPU time 3.76 seconds
Started Jul 30 05:12:37 PM PDT 24
Finished Jul 30 05:12:41 PM PDT 24
Peak memory 224912 kb
Host smart-1ce0c26d-d0b5-401a-95e3-9674d43a6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743936274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3743936274
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.124948013
Short name T461
Test name
Test status
Simulation time 14158795504 ps
CPU time 23.27 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:59 PM PDT 24
Peak memory 225032 kb
Host smart-98bf2e8b-f733-49f2-83c3-2598c6d714dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124948013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.124948013
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4229005963
Short name T244
Test name
Test status
Simulation time 509669879 ps
CPU time 7.27 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:43 PM PDT 24
Peak memory 234160 kb
Host smart-b9502e37-32fe-401b-aa7f-785a21646259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229005963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4229005963
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3368183201
Short name T544
Test name
Test status
Simulation time 6454705212 ps
CPU time 6.95 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:42 PM PDT 24
Peak memory 233224 kb
Host smart-5cb3ce32-5a3c-4e53-9504-1045d2a45fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368183201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3368183201
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2788104077
Short name T701
Test name
Test status
Simulation time 858613553 ps
CPU time 10.69 seconds
Started Jul 30 05:12:42 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 222332 kb
Host smart-86236716-a12a-4434-97c6-500e53d54ca5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788104077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2788104077
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.819965702
Short name T627
Test name
Test status
Simulation time 24076078213 ps
CPU time 100.8 seconds
Started Jul 30 05:12:40 PM PDT 24
Finished Jul 30 05:14:21 PM PDT 24
Peak memory 249636 kb
Host smart-47950762-02f2-4a08-b799-573165e98eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819965702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.819965702
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1682239988
Short name T525
Test name
Test status
Simulation time 5525197082 ps
CPU time 15.06 seconds
Started Jul 30 05:12:38 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 216784 kb
Host smart-7bdb4894-de9d-4b85-b789-05453a2537dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682239988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1682239988
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1479245078
Short name T320
Test name
Test status
Simulation time 21399246 ps
CPU time 0.7 seconds
Started Jul 30 05:12:34 PM PDT 24
Finished Jul 30 05:12:35 PM PDT 24
Peak memory 206044 kb
Host smart-885229cf-53d1-494c-a7dc-22e2df75591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479245078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1479245078
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2687762695
Short name T934
Test name
Test status
Simulation time 2749489140 ps
CPU time 1.89 seconds
Started Jul 30 05:12:35 PM PDT 24
Finished Jul 30 05:12:37 PM PDT 24
Peak memory 216672 kb
Host smart-e5e6f6eb-ca3f-42da-83bd-6e37a09a2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687762695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2687762695
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.154540462
Short name T999
Test name
Test status
Simulation time 124217015 ps
CPU time 0.74 seconds
Started Jul 30 05:12:37 PM PDT 24
Finished Jul 30 05:12:38 PM PDT 24
Peak memory 206364 kb
Host smart-a94ab7f2-e98b-4972-ba48-134a1f2fa037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154540462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.154540462
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2464362024
Short name T666
Test name
Test status
Simulation time 118779539 ps
CPU time 2.58 seconds
Started Jul 30 05:12:40 PM PDT 24
Finished Jul 30 05:12:43 PM PDT 24
Peak memory 233100 kb
Host smart-43da9602-ab43-4413-892c-a0e15afbe6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464362024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2464362024
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.8985139
Short name T48
Test name
Test status
Simulation time 13664412 ps
CPU time 0.7 seconds
Started Jul 30 05:12:46 PM PDT 24
Finished Jul 30 05:12:47 PM PDT 24
Peak memory 205252 kb
Host smart-5ceaa50d-6eb5-47d9-ad09-d818ddde3ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8985139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.8985139
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1719029765
Short name T730
Test name
Test status
Simulation time 180837801 ps
CPU time 2.23 seconds
Started Jul 30 05:12:42 PM PDT 24
Finished Jul 30 05:12:45 PM PDT 24
Peak memory 224964 kb
Host smart-9192740a-0180-4eb1-afd1-043c50243537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719029765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1719029765
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.702446257
Short name T345
Test name
Test status
Simulation time 29919253 ps
CPU time 0.78 seconds
Started Jul 30 05:12:42 PM PDT 24
Finished Jul 30 05:12:43 PM PDT 24
Peak memory 206968 kb
Host smart-e177ffe1-2c34-4ad8-a29f-7489791c9b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702446257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.702446257
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1648251455
Short name T776
Test name
Test status
Simulation time 4991531821 ps
CPU time 86.39 seconds
Started Jul 30 05:12:51 PM PDT 24
Finished Jul 30 05:14:18 PM PDT 24
Peak memory 272624 kb
Host smart-d0afd548-2304-4231-a241-fed9deb0b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648251455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1648251455
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2121036715
Short name T763
Test name
Test status
Simulation time 4525372376 ps
CPU time 55.69 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:13:47 PM PDT 24
Peak memory 249664 kb
Host smart-2e9b0591-1e75-4466-8ba6-ab941c736838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121036715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2121036715
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3736931553
Short name T545
Test name
Test status
Simulation time 99341275 ps
CPU time 2.97 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:12:50 PM PDT 24
Peak memory 233100 kb
Host smart-58fb1713-9c09-4646-b03a-4e266a535bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736931553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3736931553
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4246459553
Short name T919
Test name
Test status
Simulation time 53677218284 ps
CPU time 89.72 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:14:14 PM PDT 24
Peak memory 239592 kb
Host smart-f7a8d1db-2b72-4273-bbed-5317fa54d321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246459553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4246459553
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1637985466
Short name T233
Test name
Test status
Simulation time 6763444912 ps
CPU time 6.04 seconds
Started Jul 30 05:12:41 PM PDT 24
Finished Jul 30 05:12:47 PM PDT 24
Peak memory 224940 kb
Host smart-85f84c9f-2c53-477e-b1b9-6a9d53868adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637985466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1637985466
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2598202762
Short name T293
Test name
Test status
Simulation time 558013490 ps
CPU time 2.31 seconds
Started Jul 30 05:12:43 PM PDT 24
Finished Jul 30 05:12:45 PM PDT 24
Peak memory 224508 kb
Host smart-7b8125a5-f150-4e5c-abc3-ac50df76d1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598202762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2598202762
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3350924233
Short name T248
Test name
Test status
Simulation time 692235057 ps
CPU time 7.79 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:12:54 PM PDT 24
Peak memory 233036 kb
Host smart-4400a1a4-58e0-4d3b-9e62-5ee7e43b2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350924233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3350924233
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2923071849
Short name T1004
Test name
Test status
Simulation time 4196184433 ps
CPU time 5.23 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 224952 kb
Host smart-0d3edfc9-de94-435b-8bee-59e8b76d23e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923071849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2923071849
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.498748535
Short name T680
Test name
Test status
Simulation time 164136983 ps
CPU time 3.44 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:12:48 PM PDT 24
Peak memory 219228 kb
Host smart-c1789305-6984-47dd-ac5b-0d9079bf170e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=498748535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.498748535
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3582149652
Short name T843
Test name
Test status
Simulation time 8771627025 ps
CPU time 161.2 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:15:25 PM PDT 24
Peak memory 270428 kb
Host smart-230fc056-4109-48ab-84f5-dd5656789a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582149652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3582149652
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3481320285
Short name T755
Test name
Test status
Simulation time 2279688128 ps
CPU time 5.85 seconds
Started Jul 30 05:12:41 PM PDT 24
Finished Jul 30 05:12:47 PM PDT 24
Peak memory 216908 kb
Host smart-4a576038-0094-43ea-ba59-56205c3dc8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481320285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3481320285
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.292819620
Short name T459
Test name
Test status
Simulation time 33523564417 ps
CPU time 22.37 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:13:09 PM PDT 24
Peak memory 216708 kb
Host smart-23d6a7a1-8ba9-476d-bd4c-48c0d101a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292819620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.292819620
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3670740544
Short name T305
Test name
Test status
Simulation time 247252310 ps
CPU time 1.71 seconds
Started Jul 30 05:12:42 PM PDT 24
Finished Jul 30 05:12:44 PM PDT 24
Peak memory 216656 kb
Host smart-0813c550-fdd3-4fdf-87a7-58e650af1bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670740544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3670740544
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3092788493
Short name T396
Test name
Test status
Simulation time 72038748 ps
CPU time 0.8 seconds
Started Jul 30 05:12:42 PM PDT 24
Finished Jul 30 05:12:43 PM PDT 24
Peak memory 206328 kb
Host smart-f34ce1cc-7d2d-443f-8b8b-61fd1e499946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092788493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3092788493
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1538425963
Short name T746
Test name
Test status
Simulation time 52552036804 ps
CPU time 35.88 seconds
Started Jul 30 05:12:43 PM PDT 24
Finished Jul 30 05:13:18 PM PDT 24
Peak memory 224936 kb
Host smart-9e4b36fc-781b-4151-8896-b5809679e49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538425963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1538425963
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3993586813
Short name T559
Test name
Test status
Simulation time 14333123 ps
CPU time 0.71 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:12:48 PM PDT 24
Peak memory 206104 kb
Host smart-f142c8af-ba60-4799-a731-d123fa077b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993586813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3993586813
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.116175204
Short name T706
Test name
Test status
Simulation time 1655494910 ps
CPU time 10.7 seconds
Started Jul 30 05:12:46 PM PDT 24
Finished Jul 30 05:12:56 PM PDT 24
Peak memory 233120 kb
Host smart-bcf6b2af-b590-4bb2-9a15-21dc61d0182a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116175204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.116175204
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1884311359
Short name T681
Test name
Test status
Simulation time 18938674 ps
CPU time 0.87 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:12:45 PM PDT 24
Peak memory 206984 kb
Host smart-0f611303-9ebd-42b7-9938-f4c40e95de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884311359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1884311359
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3808708587
Short name T264
Test name
Test status
Simulation time 6910874872 ps
CPU time 98.41 seconds
Started Jul 30 05:12:49 PM PDT 24
Finished Jul 30 05:14:28 PM PDT 24
Peak memory 257700 kb
Host smart-0509409a-ac37-4241-8a9d-627abb2f7c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808708587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3808708587
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1146247271
Short name T862
Test name
Test status
Simulation time 17765142011 ps
CPU time 126.74 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:14:54 PM PDT 24
Peak memory 254880 kb
Host smart-0986ef3a-979a-497d-896d-f94c3346455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146247271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1146247271
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3354487216
Short name T724
Test name
Test status
Simulation time 12933642690 ps
CPU time 190.39 seconds
Started Jul 30 05:12:53 PM PDT 24
Finished Jul 30 05:16:03 PM PDT 24
Peak memory 257860 kb
Host smart-bcafbf5b-9f77-4d19-90f9-eb198696b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354487216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3354487216
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.754004934
Short name T405
Test name
Test status
Simulation time 4481873997 ps
CPU time 42.89 seconds
Started Jul 30 05:12:45 PM PDT 24
Finished Jul 30 05:13:28 PM PDT 24
Peak memory 249560 kb
Host smart-869b7700-f254-4b43-ac31-14d8c8eee078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754004934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.754004934
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.532784629
Short name T592
Test name
Test status
Simulation time 425284197711 ps
CPU time 301.04 seconds
Started Jul 30 05:12:51 PM PDT 24
Finished Jul 30 05:17:53 PM PDT 24
Peak memory 264724 kb
Host smart-0c08d3fa-989b-4bab-ae87-4f21f9504a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532784629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.532784629
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.904851432
Short name T1005
Test name
Test status
Simulation time 476117248 ps
CPU time 5.76 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:12:50 PM PDT 24
Peak memory 224876 kb
Host smart-d332ed79-d073-4910-9e6e-ea096156ddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904851432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.904851432
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3382113739
Short name T641
Test name
Test status
Simulation time 4031682436 ps
CPU time 34.71 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:13:19 PM PDT 24
Peak memory 224888 kb
Host smart-4041f0cd-f50e-4d55-9d17-7361d1ee525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382113739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3382113739
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3930025382
Short name T830
Test name
Test status
Simulation time 14797464592 ps
CPU time 25.57 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:13:13 PM PDT 24
Peak memory 233152 kb
Host smart-4e56cca7-57b6-48d7-9850-b722c5f822e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930025382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3930025382
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1534936675
Short name T692
Test name
Test status
Simulation time 16518779533 ps
CPU time 15.02 seconds
Started Jul 30 05:12:45 PM PDT 24
Finished Jul 30 05:13:00 PM PDT 24
Peak memory 233168 kb
Host smart-54d1f062-6723-45d5-94b7-f3ab1ca31bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534936675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1534936675
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1457103234
Short name T856
Test name
Test status
Simulation time 564802638 ps
CPU time 4.71 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:12:52 PM PDT 24
Peak memory 223528 kb
Host smart-94865da6-c10d-4005-9140-dbf79bc14ca6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1457103234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1457103234
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.45303170
Short name T740
Test name
Test status
Simulation time 187206094 ps
CPU time 0.96 seconds
Started Jul 30 05:12:48 PM PDT 24
Finished Jul 30 05:12:49 PM PDT 24
Peak memory 207096 kb
Host smart-b884b0de-6a76-43c4-b042-634ffce38d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45303170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.45303170
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.124322012
Short name T686
Test name
Test status
Simulation time 2900154774 ps
CPU time 15.73 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:13:00 PM PDT 24
Peak memory 216720 kb
Host smart-c3f207b7-b813-47df-af53-adb48a49be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124322012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.124322012
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.417712643
Short name T998
Test name
Test status
Simulation time 13768345186 ps
CPU time 24.12 seconds
Started Jul 30 05:12:44 PM PDT 24
Finished Jul 30 05:13:08 PM PDT 24
Peak memory 216648 kb
Host smart-778bf878-d204-4e58-ae11-1ff5cd958c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417712643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.417712643
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3531540761
Short name T283
Test name
Test status
Simulation time 77624871 ps
CPU time 0.89 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 207392 kb
Host smart-9f5df5a2-104c-4b01-bef6-7086dbf1dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531540761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3531540761
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1927270080
Short name T616
Test name
Test status
Simulation time 26121945 ps
CPU time 0.71 seconds
Started Jul 30 05:12:47 PM PDT 24
Finished Jul 30 05:12:48 PM PDT 24
Peak memory 206036 kb
Host smart-2f25a42c-6c26-4d87-ad65-28c54aa4272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927270080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1927270080
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1057222370
Short name T483
Test name
Test status
Simulation time 383222440 ps
CPU time 3.39 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 224772 kb
Host smart-9644b3c4-b1ed-41cc-b983-679a1b03f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057222370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1057222370
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.547648556
Short name T767
Test name
Test status
Simulation time 57578422 ps
CPU time 0.75 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 206016 kb
Host smart-00f09441-1bbd-48d7-90b9-11396c767c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547648556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.547648556
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4023609126
Short name T765
Test name
Test status
Simulation time 35795388 ps
CPU time 2.47 seconds
Started Jul 30 05:12:51 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 232880 kb
Host smart-231ce72f-1d5b-498a-a0ea-6915aa07e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023609126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4023609126
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2529237747
Short name T314
Test name
Test status
Simulation time 148909841 ps
CPU time 0.79 seconds
Started Jul 30 05:12:48 PM PDT 24
Finished Jul 30 05:12:49 PM PDT 24
Peak memory 206980 kb
Host smart-edde66f4-763a-48c2-9f14-4f5d6659daa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529237747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2529237747
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2400163850
Short name T659
Test name
Test status
Simulation time 40584742281 ps
CPU time 203.52 seconds
Started Jul 30 05:12:53 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 249680 kb
Host smart-94b8badb-a5f2-4982-b7ca-19b97f36e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400163850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2400163850
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.140446233
Short name T607
Test name
Test status
Simulation time 2515581958 ps
CPU time 18.14 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:13:10 PM PDT 24
Peak memory 253348 kb
Host smart-38aa0665-1ccf-4919-a8c7-bf852d08dc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140446233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.140446233
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.310905844
Short name T610
Test name
Test status
Simulation time 216267428 ps
CPU time 5.06 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 233168 kb
Host smart-9165c921-f6a1-4402-b929-4c284080731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310905844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.310905844
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1325007422
Short name T858
Test name
Test status
Simulation time 1246885239 ps
CPU time 3.31 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 233104 kb
Host smart-8068ba43-6e06-4c5a-9b33-778ccf7a6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325007422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1325007422
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3699114629
Short name T550
Test name
Test status
Simulation time 1608939691 ps
CPU time 13.03 seconds
Started Jul 30 05:12:53 PM PDT 24
Finished Jul 30 05:13:06 PM PDT 24
Peak memory 233176 kb
Host smart-e4f36bd2-7079-4b00-a8be-15ec0c40cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699114629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3699114629
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1129230752
Short name T947
Test name
Test status
Simulation time 835017907 ps
CPU time 5.73 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:12:56 PM PDT 24
Peak memory 240848 kb
Host smart-2271e418-2820-412b-a0b0-edd3175306d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129230752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1129230752
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1548073548
Short name T802
Test name
Test status
Simulation time 318042521 ps
CPU time 5.37 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:12:56 PM PDT 24
Peak memory 225004 kb
Host smart-58bd5263-8e42-47be-9545-eb2c190f6e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548073548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1548073548
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1044341413
Short name T588
Test name
Test status
Simulation time 5969226408 ps
CPU time 15.21 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 220864 kb
Host smart-510a29fe-530c-4c65-b2c7-7a18f2f23979
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1044341413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1044341413
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.430919849
Short name T503
Test name
Test status
Simulation time 115417993 ps
CPU time 0.9 seconds
Started Jul 30 05:12:53 PM PDT 24
Finished Jul 30 05:12:54 PM PDT 24
Peak memory 206004 kb
Host smart-457c64d4-8520-44a0-b8e3-bd328137f91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430919849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.430919849
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1766398739
Short name T527
Test name
Test status
Simulation time 3118207002 ps
CPU time 15.51 seconds
Started Jul 30 05:12:48 PM PDT 24
Finished Jul 30 05:13:04 PM PDT 24
Peak memory 220276 kb
Host smart-581e0379-f24e-4712-aacb-c7c0dfb845a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766398739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1766398739
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.863825129
Short name T463
Test name
Test status
Simulation time 2894827751 ps
CPU time 4.59 seconds
Started Jul 30 05:12:53 PM PDT 24
Finished Jul 30 05:12:58 PM PDT 24
Peak memory 216744 kb
Host smart-5ab63f41-5065-41f5-8d40-aab24af4f9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863825129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.863825129
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4177237421
Short name T60
Test name
Test status
Simulation time 54967875 ps
CPU time 1.05 seconds
Started Jul 30 05:12:49 PM PDT 24
Finished Jul 30 05:12:50 PM PDT 24
Peak memory 207592 kb
Host smart-018aa7dc-f17a-4558-aebd-5ecaf4908b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177237421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4177237421
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.639741198
Short name T595
Test name
Test status
Simulation time 125269638 ps
CPU time 0.87 seconds
Started Jul 30 05:12:51 PM PDT 24
Finished Jul 30 05:12:52 PM PDT 24
Peak memory 206520 kb
Host smart-4d2bae44-eabf-4fbc-bbfc-7a30915e5f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639741198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.639741198
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.210048613
Short name T28
Test name
Test status
Simulation time 249612159 ps
CPU time 2.76 seconds
Started Jul 30 05:12:50 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 224976 kb
Host smart-b07570d3-6bfd-4588-9bec-de14c06f1346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210048613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.210048613
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.270307246
Short name T871
Test name
Test status
Simulation time 13411755 ps
CPU time 0.72 seconds
Started Jul 30 05:12:51 PM PDT 24
Finished Jul 30 05:12:52 PM PDT 24
Peak memory 205308 kb
Host smart-1905222e-b705-4cc5-ac9e-8ef1cae9928e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270307246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.270307246
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1909835695
Short name T455
Test name
Test status
Simulation time 147867549 ps
CPU time 2.48 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 224812 kb
Host smart-1359eaf5-b236-4979-b31c-07df05c6685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909835695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1909835695
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.200145257
Short name T298
Test name
Test status
Simulation time 14951918 ps
CPU time 0.79 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 205928 kb
Host smart-8848861a-1ccd-453a-ad7a-8f99714e4821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200145257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.200145257
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1277736524
Short name T190
Test name
Test status
Simulation time 391381691 ps
CPU time 8.63 seconds
Started Jul 30 05:12:56 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 224916 kb
Host smart-616ade02-0b5d-4a1a-9145-c725c67c2109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277736524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1277736524
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2644234380
Short name T395
Test name
Test status
Simulation time 23294535180 ps
CPU time 53.05 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:13:47 PM PDT 24
Peak memory 250988 kb
Host smart-a8599e7e-ccf3-4213-a5da-436056cd044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644234380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2644234380
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2178969257
Short name T785
Test name
Test status
Simulation time 1835082762 ps
CPU time 7.84 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:13:02 PM PDT 24
Peak memory 238800 kb
Host smart-ba2f830d-d350-49b2-944a-b9146ccbad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178969257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2178969257
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2042520691
Short name T731
Test name
Test status
Simulation time 2262507246 ps
CPU time 12.69 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:13:06 PM PDT 24
Peak memory 237836 kb
Host smart-a79b4d45-21a7-4d55-8079-ce05e5479cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042520691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2042520691
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1910806464
Short name T807
Test name
Test status
Simulation time 2145070916 ps
CPU time 11.93 seconds
Started Jul 30 05:12:53 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 224920 kb
Host smart-b7200f8d-55dd-4c06-b88a-40134c781025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910806464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1910806464
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.896712519
Short name T167
Test name
Test status
Simulation time 3114330395 ps
CPU time 33.59 seconds
Started Jul 30 05:13:04 PM PDT 24
Finished Jul 30 05:13:38 PM PDT 24
Peak memory 233164 kb
Host smart-28c15a46-bf8f-4f53-9593-5c56dacc5799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896712519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.896712519
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.730856939
Short name T543
Test name
Test status
Simulation time 3164288897 ps
CPU time 8.7 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:13:02 PM PDT 24
Peak memory 237144 kb
Host smart-129547f5-1eb7-4f16-99f0-d637a226c647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730856939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.730856939
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3916232118
Short name T960
Test name
Test status
Simulation time 666859900 ps
CPU time 4.98 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:12:59 PM PDT 24
Peak memory 233140 kb
Host smart-96466776-78f1-476d-b1ef-5c42a3be535e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916232118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3916232118
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3177388834
Short name T548
Test name
Test status
Simulation time 229778535 ps
CPU time 5.15 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:12:57 PM PDT 24
Peak memory 223544 kb
Host smart-60a7d200-fdb1-4cec-ad39-77174aac6b04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3177388834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3177388834
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2583536116
Short name T185
Test name
Test status
Simulation time 16888892833 ps
CPU time 61.89 seconds
Started Jul 30 05:12:56 PM PDT 24
Finished Jul 30 05:13:58 PM PDT 24
Peak memory 225060 kb
Host smart-695f48bf-88a4-4e11-8c11-c9d843873102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583536116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2583536116
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3230025223
Short name T453
Test name
Test status
Simulation time 3412950966 ps
CPU time 19.91 seconds
Started Jul 30 05:12:52 PM PDT 24
Finished Jul 30 05:13:12 PM PDT 24
Peak memory 216844 kb
Host smart-eee1b9c1-1c78-43be-81c7-b626da02f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230025223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3230025223
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1260790827
Short name T841
Test name
Test status
Simulation time 32605707305 ps
CPU time 20.57 seconds
Started Jul 30 05:12:58 PM PDT 24
Finished Jul 30 05:13:19 PM PDT 24
Peak memory 217040 kb
Host smart-4fcda9a6-5fb7-4347-91ef-f4eb3664c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260790827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1260790827
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2331484556
Short name T508
Test name
Test status
Simulation time 18894009 ps
CPU time 0.7 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 205996 kb
Host smart-104ba885-b236-482d-aaf1-a2fb3f114367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331484556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2331484556
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3340482759
Short name T633
Test name
Test status
Simulation time 122033352 ps
CPU time 0.93 seconds
Started Jul 30 05:12:54 PM PDT 24
Finished Jul 30 05:12:55 PM PDT 24
Peak memory 206400 kb
Host smart-93f8df8f-2eaf-496a-a763-df0390d6cc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340482759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3340482759
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4043122977
Short name T169
Test name
Test status
Simulation time 5667183776 ps
CPU time 9.48 seconds
Started Jul 30 05:12:55 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 240944 kb
Host smart-97fbc3a0-6129-4c9c-afc0-198040a111f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043122977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4043122977
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3922997502
Short name T926
Test name
Test status
Simulation time 194650574 ps
CPU time 0.78 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:13:03 PM PDT 24
Peak memory 206184 kb
Host smart-2167c563-590b-49e1-b438-5f4e9b30b236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922997502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3922997502
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.922761612
Short name T361
Test name
Test status
Simulation time 523851449 ps
CPU time 3.65 seconds
Started Jul 30 05:12:57 PM PDT 24
Finished Jul 30 05:13:01 PM PDT 24
Peak memory 224968 kb
Host smart-3e6fb318-9aa0-49fb-958f-f7636121a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922761612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.922761612
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.940821379
Short name T425
Test name
Test status
Simulation time 15347405 ps
CPU time 0.75 seconds
Started Jul 30 05:12:55 PM PDT 24
Finished Jul 30 05:12:56 PM PDT 24
Peak memory 206280 kb
Host smart-31f7adbc-95a7-4ff1-bb21-51fb1f75b899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940821379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.940821379
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1283884260
Short name T691
Test name
Test status
Simulation time 14785694514 ps
CPU time 67.36 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:14:09 PM PDT 24
Peak memory 249508 kb
Host smart-a44bb5ed-82bb-43cd-b100-80e5bcd3d2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283884260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1283884260
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1611510605
Short name T22
Test name
Test status
Simulation time 10198953985 ps
CPU time 64.18 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:14:07 PM PDT 24
Peak memory 252612 kb
Host smart-e37893d2-bd14-42c8-b90f-9ca730a00024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611510605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1611510605
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.809933361
Short name T827
Test name
Test status
Simulation time 11364108632 ps
CPU time 95.65 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:14:46 PM PDT 24
Peak memory 241360 kb
Host smart-f7a47bfc-5498-47b5-9999-a1d36fc0b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809933361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.809933361
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.432119854
Short name T334
Test name
Test status
Simulation time 143078885 ps
CPU time 3.67 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:13:06 PM PDT 24
Peak memory 234108 kb
Host smart-cfc235e9-5693-4bbc-a3d4-30374a42a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432119854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.432119854
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4175706208
Short name T484
Test name
Test status
Simulation time 78370821 ps
CPU time 0.8 seconds
Started Jul 30 05:12:57 PM PDT 24
Finished Jul 30 05:12:58 PM PDT 24
Peak memory 216328 kb
Host smart-c4a83f47-2d7b-44b8-9748-54732d15ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175706208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4175706208
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2596978392
Short name T933
Test name
Test status
Simulation time 170978527 ps
CPU time 4.88 seconds
Started Jul 30 05:12:58 PM PDT 24
Finished Jul 30 05:13:03 PM PDT 24
Peak memory 224888 kb
Host smart-48075255-82a8-4f56-8fe7-4a9636e02f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596978392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2596978392
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4135127847
Short name T571
Test name
Test status
Simulation time 118380821274 ps
CPU time 100.07 seconds
Started Jul 30 05:12:58 PM PDT 24
Finished Jul 30 05:14:38 PM PDT 24
Peak memory 233136 kb
Host smart-2bc9c210-6274-4098-aef7-d187e686e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135127847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4135127847
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2563702863
Short name T235
Test name
Test status
Simulation time 2596676336 ps
CPU time 8.25 seconds
Started Jul 30 05:12:57 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 224904 kb
Host smart-ba5cc111-c26a-4466-a40b-9f1fdcf6d810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563702863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2563702863
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1850047317
Short name T930
Test name
Test status
Simulation time 4520507418 ps
CPU time 15.23 seconds
Started Jul 30 05:12:57 PM PDT 24
Finished Jul 30 05:13:13 PM PDT 24
Peak memory 224928 kb
Host smart-7aced65f-6146-4721-968d-10724a35c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850047317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1850047317
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2132501987
Short name T370
Test name
Test status
Simulation time 358453171 ps
CPU time 6.97 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:13:09 PM PDT 24
Peak memory 223416 kb
Host smart-54ad22af-c745-4f3e-a0f7-adedd1d2238c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132501987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2132501987
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2806874527
Short name T961
Test name
Test status
Simulation time 193979972593 ps
CPU time 545.19 seconds
Started Jul 30 05:13:06 PM PDT 24
Finished Jul 30 05:22:11 PM PDT 24
Peak memory 285440 kb
Host smart-7acb9969-6a56-4fa6-a70d-3b01ca956fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806874527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2806874527
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.368992312
Short name T338
Test name
Test status
Simulation time 43116217445 ps
CPU time 26.83 seconds
Started Jul 30 05:12:56 PM PDT 24
Finished Jul 30 05:13:23 PM PDT 24
Peak memory 216676 kb
Host smart-895fe8c1-358b-4e66-8475-6dd9dd50cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368992312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.368992312
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.47408781
Short name T387
Test name
Test status
Simulation time 19552324693 ps
CPU time 15.89 seconds
Started Jul 30 05:13:00 PM PDT 24
Finished Jul 30 05:13:15 PM PDT 24
Peak memory 218896 kb
Host smart-bdb3f7b1-1b36-4887-aa00-996f2458e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47408781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.47408781
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2173461319
Short name T412
Test name
Test status
Simulation time 171089060 ps
CPU time 7.88 seconds
Started Jul 30 05:12:57 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 216616 kb
Host smart-f692ab8d-1a40-4edf-ac82-c814dedbd8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173461319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2173461319
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3838985726
Short name T520
Test name
Test status
Simulation time 179648852 ps
CPU time 0.94 seconds
Started Jul 30 05:12:58 PM PDT 24
Finished Jul 30 05:12:59 PM PDT 24
Peak memory 206396 kb
Host smart-468e0f6f-dc32-4373-a31c-8b55cca04dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838985726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3838985726
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3501982558
Short name T661
Test name
Test status
Simulation time 18736663585 ps
CPU time 11.86 seconds
Started Jul 30 05:12:57 PM PDT 24
Finished Jul 30 05:13:09 PM PDT 24
Peak memory 233204 kb
Host smart-01ab59f7-bb75-4bc8-883b-b7c3d21a4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501982558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3501982558
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1661667271
Short name T312
Test name
Test status
Simulation time 14259987 ps
CPU time 0.77 seconds
Started Jul 30 05:11:52 PM PDT 24
Finished Jul 30 05:11:53 PM PDT 24
Peak memory 205300 kb
Host smart-ac2399d3-75d3-4e92-bafd-ace6a066d442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661667271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
661667271
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1274558883
Short name T753
Test name
Test status
Simulation time 354631942 ps
CPU time 3.65 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:55 PM PDT 24
Peak memory 224856 kb
Host smart-bd07c925-d415-4699-8d17-4d7ee9be47e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274558883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1274558883
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3098904214
Short name T340
Test name
Test status
Simulation time 18066848 ps
CPU time 0.74 seconds
Started Jul 30 05:11:45 PM PDT 24
Finished Jul 30 05:11:45 PM PDT 24
Peak memory 206200 kb
Host smart-822f6c16-fb69-4198-960a-3961dcd093b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098904214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3098904214
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3667940817
Short name T991
Test name
Test status
Simulation time 61696941343 ps
CPU time 415.22 seconds
Started Jul 30 05:11:48 PM PDT 24
Finished Jul 30 05:18:44 PM PDT 24
Peak memory 255924 kb
Host smart-e8aa3440-b4f5-4336-91e2-f7321a6584e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667940817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3667940817
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4073333413
Short name T720
Test name
Test status
Simulation time 68259068392 ps
CPU time 271.68 seconds
Started Jul 30 05:11:50 PM PDT 24
Finished Jul 30 05:16:22 PM PDT 24
Peak memory 262600 kb
Host smart-3bd9fd39-0345-4826-85b2-6b83cf584eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073333413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4073333413
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2755596177
Short name T664
Test name
Test status
Simulation time 1138845729 ps
CPU time 5.83 seconds
Started Jul 30 05:11:45 PM PDT 24
Finished Jul 30 05:11:51 PM PDT 24
Peak memory 224924 kb
Host smart-3d6510cf-efa6-4b91-826a-2da4184919e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755596177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2755596177
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1188787440
Short name T170
Test name
Test status
Simulation time 197944739967 ps
CPU time 202.34 seconds
Started Jul 30 05:11:45 PM PDT 24
Finished Jul 30 05:15:08 PM PDT 24
Peak memory 256436 kb
Host smart-71485ae3-34a8-43c5-8ee4-1a7ddd72d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188787440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1188787440
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2532431096
Short name T80
Test name
Test status
Simulation time 721340101 ps
CPU time 3.88 seconds
Started Jul 30 05:11:48 PM PDT 24
Finished Jul 30 05:11:52 PM PDT 24
Peak memory 233116 kb
Host smart-8adc253e-5d08-4c44-bb2b-f7d3dfc97fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532431096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2532431096
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2680515578
Short name T343
Test name
Test status
Simulation time 6026113070 ps
CPU time 46.83 seconds
Started Jul 30 05:11:46 PM PDT 24
Finished Jul 30 05:12:33 PM PDT 24
Peak memory 225004 kb
Host smart-14f9d51f-3008-48b2-a8c8-072403d4c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680515578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2680515578
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3893977875
Short name T397
Test name
Test status
Simulation time 838811908 ps
CPU time 3.09 seconds
Started Jul 30 05:11:47 PM PDT 24
Finished Jul 30 05:11:51 PM PDT 24
Peak memory 233100 kb
Host smart-3ebac673-b9fd-4e21-9aa8-c39b782236d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893977875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3893977875
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1609628781
Short name T882
Test name
Test status
Simulation time 73726712 ps
CPU time 2.1 seconds
Started Jul 30 05:11:46 PM PDT 24
Finished Jul 30 05:11:49 PM PDT 24
Peak memory 223472 kb
Host smart-305b9ae0-3b8d-4116-afaa-8216281b1a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609628781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1609628781
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3393727733
Short name T606
Test name
Test status
Simulation time 1297531387 ps
CPU time 8.17 seconds
Started Jul 30 05:11:47 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 223396 kb
Host smart-dbaeb9fd-fba7-4147-a6f8-54481c3706b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3393727733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3393727733
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3954881088
Short name T672
Test name
Test status
Simulation time 97026038 ps
CPU time 1.2 seconds
Started Jul 30 05:11:50 PM PDT 24
Finished Jul 30 05:11:51 PM PDT 24
Peak memory 207504 kb
Host smart-40b6a0a6-01bf-44b9-817e-715318ae8a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954881088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3954881088
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1731770870
Short name T910
Test name
Test status
Simulation time 5093218876 ps
CPU time 21.18 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:12:13 PM PDT 24
Peak memory 216688 kb
Host smart-77867589-51e0-42fb-ae89-4b2f779514ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731770870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1731770870
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1514905257
Short name T537
Test name
Test status
Simulation time 21666246513 ps
CPU time 8.53 seconds
Started Jul 30 05:11:46 PM PDT 24
Finished Jul 30 05:11:55 PM PDT 24
Peak memory 216704 kb
Host smart-3a7f1d2d-c822-4503-93a2-0457473a3539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514905257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1514905257
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1873973333
Short name T322
Test name
Test status
Simulation time 206666104 ps
CPU time 0.85 seconds
Started Jul 30 05:11:45 PM PDT 24
Finished Jul 30 05:11:46 PM PDT 24
Peak memory 206324 kb
Host smart-05cc4980-5e62-438a-b951-1b13baa779d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873973333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1873973333
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.90128369
Short name T556
Test name
Test status
Simulation time 114169955 ps
CPU time 0.69 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:52 PM PDT 24
Peak memory 206016 kb
Host smart-1e197389-77f8-4bde-9f26-84163f223be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90128369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.90128369
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2982863506
Short name T954
Test name
Test status
Simulation time 428449518 ps
CPU time 3.27 seconds
Started Jul 30 05:11:48 PM PDT 24
Finished Jul 30 05:11:51 PM PDT 24
Peak memory 233124 kb
Host smart-340796fc-1f32-445a-9e05-e4419510f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982863506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2982863506
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3025712511
Short name T751
Test name
Test status
Simulation time 18859685 ps
CPU time 0.74 seconds
Started Jul 30 05:13:08 PM PDT 24
Finished Jul 30 05:13:09 PM PDT 24
Peak memory 205344 kb
Host smart-c4e89de9-adf6-4dca-9d68-d62d5642a008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025712511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3025712511
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2160584005
Short name T553
Test name
Test status
Simulation time 48381414 ps
CPU time 2.84 seconds
Started Jul 30 05:13:09 PM PDT 24
Finished Jul 30 05:13:12 PM PDT 24
Peak memory 232968 kb
Host smart-27ba3ae3-f83d-482b-a266-c2d04b454bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160584005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2160584005
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3567654171
Short name T652
Test name
Test status
Simulation time 23304382 ps
CPU time 0.81 seconds
Started Jul 30 05:13:00 PM PDT 24
Finished Jul 30 05:13:01 PM PDT 24
Peak memory 206976 kb
Host smart-1c763d30-3be0-4b9b-b01e-25bc9f5ebda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567654171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3567654171
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3919142380
Short name T886
Test name
Test status
Simulation time 16429328289 ps
CPU time 41.14 seconds
Started Jul 30 05:13:05 PM PDT 24
Finished Jul 30 05:13:46 PM PDT 24
Peak memory 249508 kb
Host smart-82cb326d-437a-4eb3-b95d-40161fbc57f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919142380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3919142380
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3773214939
Short name T663
Test name
Test status
Simulation time 116507171592 ps
CPU time 255.62 seconds
Started Jul 30 05:13:05 PM PDT 24
Finished Jul 30 05:17:21 PM PDT 24
Peak memory 266028 kb
Host smart-04eb26c0-574c-4fa1-972b-20142f615444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773214939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3773214939
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4142358776
Short name T180
Test name
Test status
Simulation time 7523943755 ps
CPU time 115.34 seconds
Started Jul 30 05:13:07 PM PDT 24
Finished Jul 30 05:15:02 PM PDT 24
Peak memory 263836 kb
Host smart-cea6906b-a3f2-4f6b-8cf7-de35bc79fbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142358776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4142358776
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.65152200
Short name T685
Test name
Test status
Simulation time 472420857 ps
CPU time 2.85 seconds
Started Jul 30 05:13:07 PM PDT 24
Finished Jul 30 05:13:10 PM PDT 24
Peak memory 233940 kb
Host smart-9090e3d7-b04a-4d9d-b8f8-b39bdf0471d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65152200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.65152200
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3964264900
Short name T479
Test name
Test status
Simulation time 23031087221 ps
CPU time 92.25 seconds
Started Jul 30 05:13:07 PM PDT 24
Finished Jul 30 05:14:39 PM PDT 24
Peak memory 252168 kb
Host smart-bf31cbb4-afd7-4eb5-b3a2-0b4b8f036eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964264900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3964264900
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1741326174
Short name T509
Test name
Test status
Simulation time 1251005504 ps
CPU time 5.99 seconds
Started Jul 30 05:13:01 PM PDT 24
Finished Jul 30 05:13:08 PM PDT 24
Peak memory 219156 kb
Host smart-93412ede-e8d5-4c37-ac70-249b03eb6a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741326174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1741326174
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3016843808
Short name T507
Test name
Test status
Simulation time 92486893 ps
CPU time 2.68 seconds
Started Jul 30 05:13:01 PM PDT 24
Finished Jul 30 05:13:04 PM PDT 24
Peak memory 232828 kb
Host smart-873e3358-d53c-4d50-aa44-59d0f31fe482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016843808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3016843808
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3889100196
Short name T636
Test name
Test status
Simulation time 3613243251 ps
CPU time 11.87 seconds
Started Jul 30 05:13:00 PM PDT 24
Finished Jul 30 05:13:12 PM PDT 24
Peak memory 233176 kb
Host smart-81aba20d-2cf2-470d-b507-ef9d22254c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889100196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3889100196
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2472732241
Short name T921
Test name
Test status
Simulation time 5325857458 ps
CPU time 19.02 seconds
Started Jul 30 05:13:01 PM PDT 24
Finished Jul 30 05:13:20 PM PDT 24
Peak memory 241092 kb
Host smart-344fa233-1fb6-4a3e-8f5d-254989d70d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472732241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2472732241
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1472512396
Short name T367
Test name
Test status
Simulation time 176652649 ps
CPU time 3.92 seconds
Started Jul 30 05:13:07 PM PDT 24
Finished Jul 30 05:13:10 PM PDT 24
Peak memory 223492 kb
Host smart-b6a2035b-a569-4ab2-a2c6-227e9c38ba68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1472512396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1472512396
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2665666468
Short name T21
Test name
Test status
Simulation time 392856654299 ps
CPU time 646.65 seconds
Started Jul 30 05:13:05 PM PDT 24
Finished Jul 30 05:23:52 PM PDT 24
Peak memory 266380 kb
Host smart-6ec592ed-bea4-4739-9c81-d85b01962020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665666468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2665666468
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.723767177
Short name T275
Test name
Test status
Simulation time 3634515454 ps
CPU time 29.19 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:13:31 PM PDT 24
Peak memory 220824 kb
Host smart-fdc70a58-a8ab-491d-aa6e-6b2be2851e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723767177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.723767177
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2319130049
Short name T789
Test name
Test status
Simulation time 454552591 ps
CPU time 3.41 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 216704 kb
Host smart-36e35d42-b2e9-487d-9d82-b42243d34a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319130049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2319130049
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1507292999
Short name T376
Test name
Test status
Simulation time 54697243 ps
CPU time 1.47 seconds
Started Jul 30 05:13:04 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 216672 kb
Host smart-8ee627c1-6ae0-455c-b43e-f3b2613f5afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507292999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1507292999
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1892284643
Short name T531
Test name
Test status
Simulation time 92175584 ps
CPU time 0.72 seconds
Started Jul 30 05:13:06 PM PDT 24
Finished Jul 30 05:13:07 PM PDT 24
Peak memory 206212 kb
Host smart-05363ba1-0af8-49e0-b89a-05cdadf954a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892284643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1892284643
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2316802016
Short name T844
Test name
Test status
Simulation time 612794899 ps
CPU time 4.03 seconds
Started Jul 30 05:13:02 PM PDT 24
Finished Jul 30 05:13:06 PM PDT 24
Peak memory 233176 kb
Host smart-13f2d8c8-b87e-45fd-a4ae-5005c347d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316802016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2316802016
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3699862368
Short name T992
Test name
Test status
Simulation time 11085044 ps
CPU time 0.75 seconds
Started Jul 30 05:13:11 PM PDT 24
Finished Jul 30 05:13:12 PM PDT 24
Peak memory 205252 kb
Host smart-ccd267d8-414f-4038-94dc-663887c748e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699862368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3699862368
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2050533988
Short name T243
Test name
Test status
Simulation time 33985910 ps
CPU time 2.1 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:13:12 PM PDT 24
Peak memory 224968 kb
Host smart-92ced6bc-7dc3-46eb-908d-c0e522579ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050533988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2050533988
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1086927294
Short name T799
Test name
Test status
Simulation time 284450858 ps
CPU time 0.8 seconds
Started Jul 30 05:13:04 PM PDT 24
Finished Jul 30 05:13:05 PM PDT 24
Peak memory 206960 kb
Host smart-f0bdafc4-e65d-43d7-9b7a-b97c892d905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086927294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1086927294
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2091054680
Short name T522
Test name
Test status
Simulation time 11480984114 ps
CPU time 81.55 seconds
Started Jul 30 05:13:09 PM PDT 24
Finished Jul 30 05:14:31 PM PDT 24
Peak memory 237152 kb
Host smart-c9c7122d-b97a-4e6a-aef2-aab806ad3a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091054680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2091054680
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1013031143
Short name T561
Test name
Test status
Simulation time 19945479167 ps
CPU time 163.76 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:15:54 PM PDT 24
Peak memory 253728 kb
Host smart-cc0212b3-ce2c-40fd-a8e9-632545174d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013031143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1013031143
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2823791713
Short name T273
Test name
Test status
Simulation time 1405449348 ps
CPU time 25.25 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 224944 kb
Host smart-d77524d1-51bb-4ed6-9c1c-821344ff1cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823791713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2823791713
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1369381309
Short name T655
Test name
Test status
Simulation time 3193761783 ps
CPU time 24.31 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 237272 kb
Host smart-7fee8fce-004c-4b3e-99c1-a4936e0530cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369381309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1369381309
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3091024974
Short name T516
Test name
Test status
Simulation time 36662195 ps
CPU time 2.28 seconds
Started Jul 30 05:13:11 PM PDT 24
Finished Jul 30 05:13:14 PM PDT 24
Peak memory 233080 kb
Host smart-cf1afa9a-806a-4377-b3b7-2012988b2794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091024974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3091024974
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2351709570
Short name T811
Test name
Test status
Simulation time 6601516916 ps
CPU time 23.4 seconds
Started Jul 30 05:13:09 PM PDT 24
Finished Jul 30 05:13:33 PM PDT 24
Peak memory 234144 kb
Host smart-fbb350e4-909d-4368-820a-cf6db287036d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351709570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2351709570
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.543236192
Short name T372
Test name
Test status
Simulation time 62677159 ps
CPU time 2.59 seconds
Started Jul 30 05:13:05 PM PDT 24
Finished Jul 30 05:13:07 PM PDT 24
Peak memory 233136 kb
Host smart-1f4686a9-117e-4857-a05a-0dcd065194bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543236192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.543236192
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2347830701
Short name T199
Test name
Test status
Simulation time 1957817104 ps
CPU time 8.06 seconds
Started Jul 30 05:13:04 PM PDT 24
Finished Jul 30 05:13:12 PM PDT 24
Peak memory 224968 kb
Host smart-8bf0ef9b-c173-47be-831f-30fbe0a19c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347830701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2347830701
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3590689802
Short name T736
Test name
Test status
Simulation time 1096636278 ps
CPU time 5.34 seconds
Started Jul 30 05:13:11 PM PDT 24
Finished Jul 30 05:13:16 PM PDT 24
Peak memory 219180 kb
Host smart-75b2e9f0-d8af-4ba4-9a70-083130f0b231
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3590689802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3590689802
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.210171572
Short name T513
Test name
Test status
Simulation time 22505596137 ps
CPU time 173.54 seconds
Started Jul 30 05:13:11 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 269796 kb
Host smart-191385b6-a9f2-47b5-9136-2efe208c50a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210171572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.210171572
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3458615533
Short name T788
Test name
Test status
Simulation time 9110780955 ps
CPU time 29.32 seconds
Started Jul 30 05:13:06 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 216644 kb
Host smart-d8861efd-bb02-4e3b-a855-b7c8ee834f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458615533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3458615533
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1598230463
Short name T445
Test name
Test status
Simulation time 31502367410 ps
CPU time 23.15 seconds
Started Jul 30 05:13:06 PM PDT 24
Finished Jul 30 05:13:30 PM PDT 24
Peak memory 216732 kb
Host smart-8f8f3013-923a-4c21-90cb-ed6379c328d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598230463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1598230463
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2853258479
Short name T622
Test name
Test status
Simulation time 19938624 ps
CPU time 1.17 seconds
Started Jul 30 05:13:07 PM PDT 24
Finished Jul 30 05:13:09 PM PDT 24
Peak memory 208304 kb
Host smart-d3fd6276-18b4-48b1-b2c9-90968cd1c4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853258479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2853258479
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3152781444
Short name T307
Test name
Test status
Simulation time 490587616 ps
CPU time 0.84 seconds
Started Jul 30 05:13:06 PM PDT 24
Finished Jul 30 05:13:07 PM PDT 24
Peak memory 207328 kb
Host smart-8979f9b8-c457-4908-ae88-43bc1c0873ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152781444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3152781444
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2909911224
Short name T438
Test name
Test status
Simulation time 6971309157 ps
CPU time 6.18 seconds
Started Jul 30 05:13:10 PM PDT 24
Finished Jul 30 05:13:17 PM PDT 24
Peak memory 233072 kb
Host smart-4ddd492a-152f-45a8-810c-ce5383002427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909911224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2909911224
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2686450010
Short name T49
Test name
Test status
Simulation time 13198598 ps
CPU time 0.74 seconds
Started Jul 30 05:13:14 PM PDT 24
Finished Jul 30 05:13:15 PM PDT 24
Peak memory 206184 kb
Host smart-c4b6826d-2480-434d-97c3-a8b72ed47f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686450010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2686450010
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3802296553
Short name T674
Test name
Test status
Simulation time 328076623 ps
CPU time 3.62 seconds
Started Jul 30 05:13:19 PM PDT 24
Finished Jul 30 05:13:23 PM PDT 24
Peak memory 224912 kb
Host smart-d78f6b36-e17d-4a2d-af1d-5622efa9c36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802296553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3802296553
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.865299797
Short name T289
Test name
Test status
Simulation time 34752779 ps
CPU time 0.84 seconds
Started Jul 30 05:13:09 PM PDT 24
Finished Jul 30 05:13:10 PM PDT 24
Peak memory 207008 kb
Host smart-f624ccf2-d5a9-4ed6-8286-651d9fc956b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865299797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.865299797
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2484660080
Short name T239
Test name
Test status
Simulation time 468071481246 ps
CPU time 281.91 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:18:06 PM PDT 24
Peak memory 255776 kb
Host smart-fe083b0b-061e-44e9-b7a5-1a460b11fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484660080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2484660080
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2314258995
Short name T637
Test name
Test status
Simulation time 51641760880 ps
CPU time 122.49 seconds
Started Jul 30 05:13:15 PM PDT 24
Finished Jul 30 05:15:18 PM PDT 24
Peak memory 240684 kb
Host smart-7ce236d8-5323-4c41-8e04-84b65e00e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314258995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2314258995
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1821358185
Short name T344
Test name
Test status
Simulation time 1065079608 ps
CPU time 5 seconds
Started Jul 30 05:13:15 PM PDT 24
Finished Jul 30 05:13:20 PM PDT 24
Peak memory 233068 kb
Host smart-f1bcd800-be26-411c-aea5-12c9ef7a7a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821358185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1821358185
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1407153904
Short name T866
Test name
Test status
Simulation time 22959155776 ps
CPU time 154.61 seconds
Started Jul 30 05:13:13 PM PDT 24
Finished Jul 30 05:15:47 PM PDT 24
Peak memory 249540 kb
Host smart-1f46cb92-8ecc-471b-a49f-3ed9d84e608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407153904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1407153904
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4115483434
Short name T601
Test name
Test status
Simulation time 573070668 ps
CPU time 4.51 seconds
Started Jul 30 05:13:15 PM PDT 24
Finished Jul 30 05:13:19 PM PDT 24
Peak memory 224900 kb
Host smart-ada71249-c35c-47bc-8207-f312ddf117cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115483434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4115483434
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3288198441
Short name T805
Test name
Test status
Simulation time 734204281 ps
CPU time 2.97 seconds
Started Jul 30 05:13:14 PM PDT 24
Finished Jul 30 05:13:17 PM PDT 24
Peak memory 233088 kb
Host smart-3f39cd45-cddb-42fb-931f-44b18934be98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288198441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3288198441
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2978553317
Short name T341
Test name
Test status
Simulation time 2071759802 ps
CPU time 9.34 seconds
Started Jul 30 05:13:20 PM PDT 24
Finished Jul 30 05:13:29 PM PDT 24
Peak memory 241308 kb
Host smart-5e48f07b-cd58-403e-a36f-6191a74b4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978553317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2978553317
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1597117269
Short name T797
Test name
Test status
Simulation time 2110499045 ps
CPU time 4.17 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:13:29 PM PDT 24
Peak memory 232968 kb
Host smart-22a30f88-d2a3-4674-b67f-47eeedd9989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597117269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1597117269
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.226979626
Short name T493
Test name
Test status
Simulation time 4405242713 ps
CPU time 8.73 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 219112 kb
Host smart-1e7f88c7-06a7-48bf-9600-03b85c4756bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=226979626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.226979626
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3587539807
Short name T969
Test name
Test status
Simulation time 118776585856 ps
CPU time 196.12 seconds
Started Jul 30 05:13:25 PM PDT 24
Finished Jul 30 05:16:42 PM PDT 24
Peak memory 265660 kb
Host smart-1f2f0054-bb91-4fd3-92de-99436223f4a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587539807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3587539807
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2266789843
Short name T949
Test name
Test status
Simulation time 2268947307 ps
CPU time 9.36 seconds
Started Jul 30 05:13:14 PM PDT 24
Finished Jul 30 05:13:23 PM PDT 24
Peak memory 216688 kb
Host smart-0463682a-d06e-4451-b310-819eb6791235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266789843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2266789843
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.793287965
Short name T829
Test name
Test status
Simulation time 130186402 ps
CPU time 1.45 seconds
Started Jul 30 05:13:09 PM PDT 24
Finished Jul 30 05:13:11 PM PDT 24
Peak memory 208072 kb
Host smart-f096afb6-44d0-4b41-a20c-350a176a2433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793287965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.793287965
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3059251375
Short name T286
Test name
Test status
Simulation time 3159850148 ps
CPU time 5.67 seconds
Started Jul 30 05:13:19 PM PDT 24
Finished Jul 30 05:13:25 PM PDT 24
Peak memory 216780 kb
Host smart-7e9cb6fe-667e-4177-a925-cd21dc4a8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059251375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3059251375
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3000131148
Short name T757
Test name
Test status
Simulation time 67678213 ps
CPU time 0.75 seconds
Started Jul 30 05:13:12 PM PDT 24
Finished Jul 30 05:13:13 PM PDT 24
Peak memory 206308 kb
Host smart-f9f8e8e6-62d2-49b8-a55f-b9a8620077ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000131148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3000131148
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1296061958
Short name T162
Test name
Test status
Simulation time 942712771 ps
CPU time 5.09 seconds
Started Jul 30 05:13:13 PM PDT 24
Finished Jul 30 05:13:18 PM PDT 24
Peak memory 233124 kb
Host smart-15a5b643-e60a-44e0-a771-216104826bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296061958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1296061958
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3759929627
Short name T390
Test name
Test status
Simulation time 36599771 ps
CPU time 0.7 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:24 PM PDT 24
Peak memory 205248 kb
Host smart-8f84c170-1aa5-4187-a2b7-5f3cf3d97771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759929627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3759929627
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3826592388
Short name T756
Test name
Test status
Simulation time 75582064 ps
CPU time 2.51 seconds
Started Jul 30 05:13:18 PM PDT 24
Finished Jul 30 05:13:20 PM PDT 24
Peak memory 233012 kb
Host smart-4bfeb8b8-730f-4935-8bd0-b399f559208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826592388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3826592388
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.510186020
Short name T682
Test name
Test status
Simulation time 33216367 ps
CPU time 0.77 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:13:26 PM PDT 24
Peak memory 206816 kb
Host smart-5df07266-22f9-4d73-9984-1390abab6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510186020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.510186020
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1813708892
Short name T462
Test name
Test status
Simulation time 51410797158 ps
CPU time 96.65 seconds
Started Jul 30 05:13:22 PM PDT 24
Finished Jul 30 05:14:59 PM PDT 24
Peak memory 249568 kb
Host smart-3b890a57-8cd9-4e4c-82bc-ec3b15f9d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813708892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1813708892
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2749793678
Short name T795
Test name
Test status
Simulation time 2042891379 ps
CPU time 32.52 seconds
Started Jul 30 05:13:19 PM PDT 24
Finished Jul 30 05:13:51 PM PDT 24
Peak memory 225180 kb
Host smart-5c78064d-8d9a-4de7-8a04-c79807a8e1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749793678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2749793678
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.972439290
Short name T942
Test name
Test status
Simulation time 23681350991 ps
CPU time 208.06 seconds
Started Jul 30 05:13:20 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 249572 kb
Host smart-0841d23f-697f-470e-ae7c-d88e8c375394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972439290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.972439290
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.656654282
Short name T725
Test name
Test status
Simulation time 2524013491 ps
CPU time 13.57 seconds
Started Jul 30 05:13:18 PM PDT 24
Finished Jul 30 05:13:31 PM PDT 24
Peak memory 253648 kb
Host smart-0cc5dfa5-ef12-4346-8f66-0883d5d881d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656654282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.656654282
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3300958758
Short name T468
Test name
Test status
Simulation time 1470414891 ps
CPU time 16.54 seconds
Started Jul 30 05:13:18 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 233008 kb
Host smart-54787f52-bb6b-4c5c-afd0-3d49f79f26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300958758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3300958758
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2531061517
Short name T33
Test name
Test status
Simulation time 61788959371 ps
CPU time 130.57 seconds
Started Jul 30 05:13:20 PM PDT 24
Finished Jul 30 05:15:31 PM PDT 24
Peak memory 233120 kb
Host smart-5ed17695-20be-43ee-bdab-ef60f974d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531061517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2531061517
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1916241250
Short name T747
Test name
Test status
Simulation time 26045870221 ps
CPU time 10.66 seconds
Started Jul 30 05:13:17 PM PDT 24
Finished Jul 30 05:13:27 PM PDT 24
Peak memory 241008 kb
Host smart-0676111a-117b-4390-ad9a-2cdb5feabb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916241250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1916241250
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3696837648
Short name T579
Test name
Test status
Simulation time 16563114838 ps
CPU time 11.37 seconds
Started Jul 30 05:13:21 PM PDT 24
Finished Jul 30 05:13:32 PM PDT 24
Peak memory 234932 kb
Host smart-dc8b1fd6-44f4-435f-bc5a-5f15135dad75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696837648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3696837648
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3782942892
Short name T963
Test name
Test status
Simulation time 5044966911 ps
CPU time 15.82 seconds
Started Jul 30 05:13:18 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 221060 kb
Host smart-bb8c54a4-de2a-4bd4-8cfc-f450de3fc1f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3782942892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3782942892
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.539685154
Short name T31
Test name
Test status
Simulation time 12158081262 ps
CPU time 171.83 seconds
Started Jul 30 05:13:22 PM PDT 24
Finished Jul 30 05:16:14 PM PDT 24
Peak memory 266040 kb
Host smart-4bd1c4b5-07bc-4cde-96e1-0ecec38a9e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539685154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.539685154
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1778688510
Short name T416
Test name
Test status
Simulation time 5056799468 ps
CPU time 30.55 seconds
Started Jul 30 05:13:22 PM PDT 24
Finished Jul 30 05:13:53 PM PDT 24
Peak memory 216720 kb
Host smart-04028c44-bde9-4808-9d61-9da65d5119a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778688510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1778688510
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2671853449
Short name T582
Test name
Test status
Simulation time 6793242685 ps
CPU time 17.07 seconds
Started Jul 30 05:13:19 PM PDT 24
Finished Jul 30 05:13:36 PM PDT 24
Peak memory 216644 kb
Host smart-647e5b71-28f1-46e7-a9ab-e2c314c7473e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671853449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2671853449
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1348891693
Short name T349
Test name
Test status
Simulation time 1063432253 ps
CPU time 10.97 seconds
Started Jul 30 05:13:17 PM PDT 24
Finished Jul 30 05:13:28 PM PDT 24
Peak memory 216652 kb
Host smart-25753626-8983-4f13-929f-be0508fb8254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348891693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1348891693
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2950954261
Short name T529
Test name
Test status
Simulation time 103420838 ps
CPU time 0.82 seconds
Started Jul 30 05:13:18 PM PDT 24
Finished Jul 30 05:13:19 PM PDT 24
Peak memory 206352 kb
Host smart-7e77ca53-7a3d-439d-9099-ae56b9d67017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950954261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2950954261
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.545421148
Short name T779
Test name
Test status
Simulation time 129928613 ps
CPU time 2.5 seconds
Started Jul 30 05:13:18 PM PDT 24
Finished Jul 30 05:13:21 PM PDT 24
Peak memory 232844 kb
Host smart-2723f3bb-382b-4916-a81f-c8fdcbf0275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545421148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.545421148
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3842833534
Short name T780
Test name
Test status
Simulation time 13836016 ps
CPU time 0.73 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:13:28 PM PDT 24
Peak memory 206148 kb
Host smart-cedb746b-af05-438a-95b5-accbc3e7693f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842833534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3842833534
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3801267116
Short name T865
Test name
Test status
Simulation time 249067745 ps
CPU time 3.94 seconds
Started Jul 30 05:13:22 PM PDT 24
Finished Jul 30 05:13:26 PM PDT 24
Peak memory 224976 kb
Host smart-9c16537a-636c-4acc-8812-6980cb0d199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801267116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3801267116
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1237373060
Short name T638
Test name
Test status
Simulation time 15342236 ps
CPU time 0.74 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:23 PM PDT 24
Peak memory 205956 kb
Host smart-41081b69-5414-49e7-a226-03c9a1e764df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237373060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1237373060
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3353615128
Short name T974
Test name
Test status
Simulation time 66172114816 ps
CPU time 129.17 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 270916 kb
Host smart-813092ba-e9be-4058-ad80-e3ef789cca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353615128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3353615128
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1575463256
Short name T988
Test name
Test status
Simulation time 8336419940 ps
CPU time 59.98 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 249672 kb
Host smart-304c6af8-595e-4b19-a664-eac67f2169e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575463256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1575463256
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.832754232
Short name T900
Test name
Test status
Simulation time 10440273221 ps
CPU time 65.95 seconds
Started Jul 30 05:13:25 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 225032 kb
Host smart-ebae539d-c06c-4aca-b8df-1a8c95a30d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832754232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.832754232
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.645221685
Short name T683
Test name
Test status
Simulation time 172974598 ps
CPU time 3.92 seconds
Started Jul 30 05:13:25 PM PDT 24
Finished Jul 30 05:13:29 PM PDT 24
Peak memory 224920 kb
Host smart-b0861ad6-52ff-4dd4-8c51-ea514da29e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645221685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.645221685
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.377606825
Short name T261
Test name
Test status
Simulation time 1040672765 ps
CPU time 13.32 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:13:41 PM PDT 24
Peak memory 224876 kb
Host smart-5f785217-346a-49e2-9a7b-a2c14353e5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377606825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.377606825
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1064103950
Short name T119
Test name
Test status
Simulation time 6813664049 ps
CPU time 19.22 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:42 PM PDT 24
Peak memory 225036 kb
Host smart-80883663-8a69-4dcd-b48b-4e9e1f2bb0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064103950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1064103950
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1070400592
Short name T913
Test name
Test status
Simulation time 945386505 ps
CPU time 3.69 seconds
Started Jul 30 05:13:21 PM PDT 24
Finished Jul 30 05:13:25 PM PDT 24
Peak memory 224888 kb
Host smart-791adf8f-08f8-44ad-b77c-e70c953606b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070400592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1070400592
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.188394667
Short name T245
Test name
Test status
Simulation time 2964428901 ps
CPU time 9.74 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:32 PM PDT 24
Peak memory 224932 kb
Host smart-b2b6cdd4-73a9-488e-8cab-7ac839070d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188394667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.188394667
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1934595166
Short name T517
Test name
Test status
Simulation time 153359733 ps
CPU time 2.13 seconds
Started Jul 30 05:13:22 PM PDT 24
Finished Jul 30 05:13:25 PM PDT 24
Peak memory 224244 kb
Host smart-6e1f2a3c-c871-4ea1-b12f-156d1a5ec570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934595166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1934595166
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.500833664
Short name T914
Test name
Test status
Simulation time 8255674265 ps
CPU time 19.82 seconds
Started Jul 30 05:13:28 PM PDT 24
Finished Jul 30 05:13:48 PM PDT 24
Peak memory 219712 kb
Host smart-38a5b387-7494-421f-8760-9691a59c83af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=500833664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.500833664
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1401795716
Short name T145
Test name
Test status
Simulation time 49947140 ps
CPU time 0.94 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:13:27 PM PDT 24
Peak memory 207260 kb
Host smart-76395054-76e2-462b-aa1f-4564920d0c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401795716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1401795716
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3167411560
Short name T944
Test name
Test status
Simulation time 3462323092 ps
CPU time 13.5 seconds
Started Jul 30 05:13:20 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 220036 kb
Host smart-3edfdeec-3bd8-43d4-8c18-619fee0b1f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167411560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3167411560
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1723264721
Short name T306
Test name
Test status
Simulation time 13890119 ps
CPU time 0.7 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:24 PM PDT 24
Peak memory 206064 kb
Host smart-5921733b-fdc4-48fa-ac80-5ebe2675538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723264721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1723264721
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2983043858
Short name T318
Test name
Test status
Simulation time 144392358 ps
CPU time 2.42 seconds
Started Jul 30 05:13:24 PM PDT 24
Finished Jul 30 05:13:26 PM PDT 24
Peak memory 216652 kb
Host smart-c85ba110-6f21-4afe-aba8-a452b1088063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983043858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2983043858
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3186423573
Short name T995
Test name
Test status
Simulation time 23026854 ps
CPU time 0.78 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:24 PM PDT 24
Peak memory 206316 kb
Host smart-307fa886-0b09-4aed-a303-9d904e40d337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186423573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3186423573
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3294821095
Short name T300
Test name
Test status
Simulation time 4629273774 ps
CPU time 6.34 seconds
Started Jul 30 05:13:23 PM PDT 24
Finished Jul 30 05:13:29 PM PDT 24
Peak memory 224960 kb
Host smart-538f0915-1b93-481e-ba99-1635bc9d481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294821095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3294821095
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3435008399
Short name T909
Test name
Test status
Simulation time 32988187 ps
CPU time 0.76 seconds
Started Jul 30 05:13:33 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 205308 kb
Host smart-c81c389d-4337-4e1d-a01b-f4c9c1a0aa04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435008399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3435008399
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1404910649
Short name T714
Test name
Test status
Simulation time 140091397 ps
CPU time 3.46 seconds
Started Jul 30 05:13:29 PM PDT 24
Finished Jul 30 05:13:32 PM PDT 24
Peak memory 233080 kb
Host smart-1f73aac2-e28d-42ef-a24a-8ee4ea514916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404910649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1404910649
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.495130081
Short name T309
Test name
Test status
Simulation time 13959100 ps
CPU time 0.72 seconds
Started Jul 30 05:13:25 PM PDT 24
Finished Jul 30 05:13:26 PM PDT 24
Peak memory 206256 kb
Host smart-59d45219-65dd-420d-9472-4112a27efe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495130081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.495130081
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.609993069
Short name T813
Test name
Test status
Simulation time 2052834809 ps
CPU time 19.09 seconds
Started Jul 30 05:13:32 PM PDT 24
Finished Jul 30 05:13:51 PM PDT 24
Peak memory 233068 kb
Host smart-db0924b7-463a-4734-b821-d5fd3a497aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609993069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.609993069
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.161653908
Short name T839
Test name
Test status
Simulation time 3212762325 ps
CPU time 77.93 seconds
Started Jul 30 05:13:32 PM PDT 24
Finished Jul 30 05:14:50 PM PDT 24
Peak memory 249624 kb
Host smart-5c1f82b8-2f70-4406-a661-50eac8d9b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161653908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.161653908
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4011955169
Short name T764
Test name
Test status
Simulation time 6764129775 ps
CPU time 23.31 seconds
Started Jul 30 05:13:30 PM PDT 24
Finished Jul 30 05:13:54 PM PDT 24
Peak memory 249636 kb
Host smart-5c8938b2-efd3-49c6-b525-cb6600a4c311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011955169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4011955169
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2011763400
Short name T589
Test name
Test status
Simulation time 3956818002 ps
CPU time 58.14 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:14:25 PM PDT 24
Peak memory 250744 kb
Host smart-a110ee84-9228-4e0e-82b5-6f546b3aa222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011763400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2011763400
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2792594995
Short name T198
Test name
Test status
Simulation time 47496282022 ps
CPU time 92.38 seconds
Started Jul 30 05:13:33 PM PDT 24
Finished Jul 30 05:15:05 PM PDT 24
Peak memory 238772 kb
Host smart-4e557f78-5c88-41c1-94d3-bda8fbf5a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792594995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2792594995
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4271828574
Short name T441
Test name
Test status
Simulation time 1367787337 ps
CPU time 5.04 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:13:32 PM PDT 24
Peak memory 224940 kb
Host smart-780a1f0f-f6ef-47d5-a423-05f5d402f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271828574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4271828574
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1037291738
Short name T651
Test name
Test status
Simulation time 33360925 ps
CPU time 2.3 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:13:29 PM PDT 24
Peak memory 232796 kb
Host smart-aa1b3016-27f1-4e1a-b4ab-7b2644523a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037291738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1037291738
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.366931402
Short name T967
Test name
Test status
Simulation time 2451585589 ps
CPU time 9.28 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 233112 kb
Host smart-b9ba3c4f-c482-47cb-ae2d-ec403848a1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366931402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.366931402
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.188245157
Short name T700
Test name
Test status
Simulation time 65483316 ps
CPU time 2.15 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:13:29 PM PDT 24
Peak memory 224884 kb
Host smart-4b200491-61df-4c29-b647-6b029f84b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188245157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.188245157
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.380019697
Short name T353
Test name
Test status
Simulation time 718951349 ps
CPU time 4.47 seconds
Started Jul 30 05:13:31 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 223540 kb
Host smart-3acb7e25-9105-4792-8ce1-9de6aec922f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=380019697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.380019697
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2006961129
Short name T66
Test name
Test status
Simulation time 42035560499 ps
CPU time 51.06 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 216696 kb
Host smart-7a0a5f9e-45bf-4880-bbde-7302e3216e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006961129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2006961129
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3698471573
Short name T837
Test name
Test status
Simulation time 1738335992 ps
CPU time 3.45 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:13:30 PM PDT 24
Peak memory 216672 kb
Host smart-1274749c-776c-42c9-af98-681e141cec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698471573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3698471573
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3320616450
Short name T719
Test name
Test status
Simulation time 41751569 ps
CPU time 2.14 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:13:28 PM PDT 24
Peak memory 216620 kb
Host smart-26264f35-cb89-44f2-97ef-0dc5036b91dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320616450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3320616450
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3475824742
Short name T330
Test name
Test status
Simulation time 12468326 ps
CPU time 0.7 seconds
Started Jul 30 05:13:26 PM PDT 24
Finished Jul 30 05:13:27 PM PDT 24
Peak memory 206028 kb
Host smart-3e47ca1c-2bb5-482c-86ae-b9a9ecc0a22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475824742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3475824742
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3934573974
Short name T564
Test name
Test status
Simulation time 3596831761 ps
CPU time 12.21 seconds
Started Jul 30 05:13:27 PM PDT 24
Finished Jul 30 05:13:39 PM PDT 24
Peak memory 224988 kb
Host smart-fe9a2697-d314-43f2-af0c-d0aa3962cf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934573974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3934573974
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4003128780
Short name T413
Test name
Test status
Simulation time 11623300 ps
CPU time 0.72 seconds
Started Jul 30 05:13:34 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 205800 kb
Host smart-285b9fbf-8455-4828-b51e-39fd0a3feabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003128780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4003128780
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1371551138
Short name T78
Test name
Test status
Simulation time 136897971 ps
CPU time 2.9 seconds
Started Jul 30 05:13:34 PM PDT 24
Finished Jul 30 05:13:37 PM PDT 24
Peak memory 224868 kb
Host smart-cd2a5fb6-f336-4cdb-8eac-3760dad934e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371551138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1371551138
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4204817040
Short name T567
Test name
Test status
Simulation time 14014716 ps
CPU time 0.76 seconds
Started Jul 30 05:13:31 PM PDT 24
Finished Jul 30 05:13:32 PM PDT 24
Peak memory 206988 kb
Host smart-32e4ef38-2684-4d61-b1dd-cee3bbe28cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204817040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4204817040
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.720905241
Short name T791
Test name
Test status
Simulation time 1375626105 ps
CPU time 31.94 seconds
Started Jul 30 05:13:36 PM PDT 24
Finished Jul 30 05:14:08 PM PDT 24
Peak memory 252624 kb
Host smart-ad63b2aa-c968-465e-aa16-1056710ad0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720905241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.720905241
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3666965706
Short name T186
Test name
Test status
Simulation time 37826282828 ps
CPU time 403.06 seconds
Started Jul 30 05:13:35 PM PDT 24
Finished Jul 30 05:20:18 PM PDT 24
Peak memory 262792 kb
Host smart-9c9893bc-699b-4b7f-a7c5-a5c3f07fc877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666965706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3666965706
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3150965323
Short name T689
Test name
Test status
Simulation time 4816987471 ps
CPU time 115.38 seconds
Started Jul 30 05:13:35 PM PDT 24
Finished Jul 30 05:15:31 PM PDT 24
Peak memory 266084 kb
Host smart-8f418f50-49fb-4b94-b9eb-afe20edd2cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150965323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3150965323
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2583042491
Short name T206
Test name
Test status
Simulation time 1513801662 ps
CPU time 7.38 seconds
Started Jul 30 05:13:35 PM PDT 24
Finished Jul 30 05:13:43 PM PDT 24
Peak memory 233072 kb
Host smart-70fff39a-f45c-4f90-a8a6-7b1c68ed6004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583042491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2583042491
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.4272972394
Short name T208
Test name
Test status
Simulation time 68432660495 ps
CPU time 129.26 seconds
Started Jul 30 05:13:34 PM PDT 24
Finished Jul 30 05:15:44 PM PDT 24
Peak memory 249576 kb
Host smart-c6aa48f8-b5e3-4e37-9708-10913478335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272972394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.4272972394
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1777641584
Short name T193
Test name
Test status
Simulation time 2301833975 ps
CPU time 6.96 seconds
Started Jul 30 05:13:34 PM PDT 24
Finished Jul 30 05:13:41 PM PDT 24
Peak memory 225012 kb
Host smart-28ffc04d-23c6-484f-91f0-ffe7f50c3661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777641584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1777641584
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1229967314
Short name T229
Test name
Test status
Simulation time 141760324 ps
CPU time 5.38 seconds
Started Jul 30 05:13:31 PM PDT 24
Finished Jul 30 05:13:36 PM PDT 24
Peak memory 220384 kb
Host smart-23159834-1ebb-439e-af25-c079d6193e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229967314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1229967314
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.368043275
Short name T524
Test name
Test status
Simulation time 1612774245 ps
CPU time 6.4 seconds
Started Jul 30 05:13:32 PM PDT 24
Finished Jul 30 05:13:38 PM PDT 24
Peak memory 233320 kb
Host smart-c136b14a-03fc-4a9e-bbcc-556b76577946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368043275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.368043275
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3148643276
Short name T383
Test name
Test status
Simulation time 9738124700 ps
CPU time 5.32 seconds
Started Jul 30 05:13:32 PM PDT 24
Finished Jul 30 05:13:38 PM PDT 24
Peak memory 224980 kb
Host smart-698a2639-a3d0-49f8-8a22-4281765963e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148643276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3148643276
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.878180208
Short name T968
Test name
Test status
Simulation time 1842458105 ps
CPU time 10.21 seconds
Started Jul 30 05:13:37 PM PDT 24
Finished Jul 30 05:13:47 PM PDT 24
Peak memory 220860 kb
Host smart-37f9de04-90bf-4647-862b-ce76adbede0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878180208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.878180208
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1470038639
Short name T63
Test name
Test status
Simulation time 6270925245 ps
CPU time 23.1 seconds
Started Jul 30 05:13:32 PM PDT 24
Finished Jul 30 05:13:55 PM PDT 24
Peak memory 216884 kb
Host smart-280e22bb-34f2-4ac2-97b4-0271cf3d3bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470038639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1470038639
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.176075203
Short name T576
Test name
Test status
Simulation time 540994900 ps
CPU time 2.43 seconds
Started Jul 30 05:13:31 PM PDT 24
Finished Jul 30 05:13:34 PM PDT 24
Peak memory 208312 kb
Host smart-73f62cbf-cd1c-4891-bc51-ece4b51412e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176075203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.176075203
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2390366792
Short name T532
Test name
Test status
Simulation time 627843061 ps
CPU time 2.74 seconds
Started Jul 30 05:13:30 PM PDT 24
Finished Jul 30 05:13:33 PM PDT 24
Peak memory 216588 kb
Host smart-7c016901-5975-4bda-bc6d-258c0137e9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390366792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2390366792
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.904071334
Short name T329
Test name
Test status
Simulation time 113362091 ps
CPU time 0.86 seconds
Started Jul 30 05:13:31 PM PDT 24
Finished Jul 30 05:13:32 PM PDT 24
Peak memory 206340 kb
Host smart-6545bd5d-6a1c-407b-af89-d22df8f18e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904071334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.904071334
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2697640367
Short name T58
Test name
Test status
Simulation time 17505778391 ps
CPU time 25.52 seconds
Started Jul 30 05:13:34 PM PDT 24
Finished Jul 30 05:14:00 PM PDT 24
Peak memory 233264 kb
Host smart-52a4f591-850b-41c2-8540-6a68a7975f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697640367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2697640367
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2895482073
Short name T821
Test name
Test status
Simulation time 14149536 ps
CPU time 0.7 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:41 PM PDT 24
Peak memory 205820 kb
Host smart-13facee2-a4d7-4d23-a5ce-117e0ff1e252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895482073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2895482073
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2960317767
Short name T375
Test name
Test status
Simulation time 3661305444 ps
CPU time 8.08 seconds
Started Jul 30 05:13:38 PM PDT 24
Finished Jul 30 05:13:46 PM PDT 24
Peak memory 225016 kb
Host smart-d590c33d-5907-407c-a16b-80f3e0e7c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960317767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2960317767
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.28104568
Short name T432
Test name
Test status
Simulation time 65703213 ps
CPU time 0.78 seconds
Started Jul 30 05:13:36 PM PDT 24
Finished Jul 30 05:13:37 PM PDT 24
Peak memory 206928 kb
Host smart-d7fcccca-95a1-41ce-8408-a20ea418438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28104568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.28104568
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3891746104
Short name T196
Test name
Test status
Simulation time 25950884363 ps
CPU time 99.07 seconds
Started Jul 30 05:13:38 PM PDT 24
Finished Jul 30 05:15:17 PM PDT 24
Peak memory 249552 kb
Host smart-33c2762d-b7dd-4743-b964-0ea409521451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891746104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3891746104
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1158227842
Short name T127
Test name
Test status
Simulation time 28191437163 ps
CPU time 255.99 seconds
Started Jul 30 05:13:41 PM PDT 24
Finished Jul 30 05:17:57 PM PDT 24
Peak memory 271108 kb
Host smart-a89a965f-80d7-48f1-ad27-fe11c95ec7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158227842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1158227842
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3263124500
Short name T265
Test name
Test status
Simulation time 12046551462 ps
CPU time 53.58 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:14:33 PM PDT 24
Peak memory 225016 kb
Host smart-96aa24eb-34d9-403c-b399-f73bea06d3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263124500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3263124500
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3658923161
Short name T134
Test name
Test status
Simulation time 1528543302 ps
CPU time 9.86 seconds
Started Jul 30 05:13:38 PM PDT 24
Finished Jul 30 05:13:48 PM PDT 24
Peak memory 224884 kb
Host smart-61fe1032-aa67-4670-a6ff-f3919cfdb2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658923161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3658923161
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2002929749
Short name T250
Test name
Test status
Simulation time 39967521534 ps
CPU time 270.82 seconds
Started Jul 30 05:13:41 PM PDT 24
Finished Jul 30 05:18:12 PM PDT 24
Peak memory 256632 kb
Host smart-481d645e-5742-4861-832d-e42593c64459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002929749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2002929749
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2144460683
Short name T408
Test name
Test status
Simulation time 73505927 ps
CPU time 2.1 seconds
Started Jul 30 05:13:38 PM PDT 24
Finished Jul 30 05:13:40 PM PDT 24
Peak memory 224564 kb
Host smart-35346639-2186-434e-933c-786903abde7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144460683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2144460683
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4121506917
Short name T316
Test name
Test status
Simulation time 128296881886 ps
CPU time 167.68 seconds
Started Jul 30 05:13:44 PM PDT 24
Finished Jul 30 05:16:32 PM PDT 24
Peak memory 233152 kb
Host smart-3f72f2b7-09bf-4a22-b8eb-e4803e126134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121506917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4121506917
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2473560
Short name T699
Test name
Test status
Simulation time 1323523645 ps
CPU time 5.8 seconds
Started Jul 30 05:13:35 PM PDT 24
Finished Jul 30 05:13:41 PM PDT 24
Peak memory 224788 kb
Host smart-ff426602-8be5-4ce3-8121-ec7654d8b136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.2473560
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3818232601
Short name T101
Test name
Test status
Simulation time 2221476165 ps
CPU time 10.15 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:50 PM PDT 24
Peak memory 238900 kb
Host smart-f42c1e57-53bc-4289-a45b-5c602174cfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818232601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3818232601
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.727816148
Short name T792
Test name
Test status
Simulation time 7455722062 ps
CPU time 5.77 seconds
Started Jul 30 05:13:38 PM PDT 24
Finished Jul 30 05:13:44 PM PDT 24
Peak memory 220300 kb
Host smart-f7ba7003-4476-4ddd-b64a-74a33e49b94e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=727816148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.727816148
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1014252134
Short name T450
Test name
Test status
Simulation time 3541990453 ps
CPU time 25.72 seconds
Started Jul 30 05:13:38 PM PDT 24
Finished Jul 30 05:14:04 PM PDT 24
Peak memory 216780 kb
Host smart-bd6fa204-fa1f-43f9-9a88-7a4866581171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014252134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1014252134
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2402542680
Short name T581
Test name
Test status
Simulation time 3396739116 ps
CPU time 5.73 seconds
Started Jul 30 05:13:35 PM PDT 24
Finished Jul 30 05:13:41 PM PDT 24
Peak memory 216676 kb
Host smart-b42c7205-fb4b-4a80-8b18-8fe6620579f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402542680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2402542680
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.511087763
Short name T801
Test name
Test status
Simulation time 60960881 ps
CPU time 1.11 seconds
Started Jul 30 05:13:35 PM PDT 24
Finished Jul 30 05:13:36 PM PDT 24
Peak memory 208144 kb
Host smart-3732d78a-3bc2-4500-8e1a-25c3413d3fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511087763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.511087763
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1319338510
Short name T586
Test name
Test status
Simulation time 51758570 ps
CPU time 0.89 seconds
Started Jul 30 05:13:34 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 207408 kb
Host smart-4fff132b-f63c-4323-9615-b880bf38c9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319338510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1319338510
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1227508632
Short name T863
Test name
Test status
Simulation time 3074462600 ps
CPU time 11.3 seconds
Started Jul 30 05:13:42 PM PDT 24
Finished Jul 30 05:13:53 PM PDT 24
Peak memory 224996 kb
Host smart-1cb4eac7-27bd-4fdc-bcd8-08b256a9aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227508632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1227508632
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1967878837
Short name T867
Test name
Test status
Simulation time 38520292 ps
CPU time 0.73 seconds
Started Jul 30 05:13:46 PM PDT 24
Finished Jul 30 05:13:47 PM PDT 24
Peak memory 205840 kb
Host smart-fa192ef3-cbfc-4d63-9159-94517329fe74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967878837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1967878837
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.847328620
Short name T861
Test name
Test status
Simulation time 7142831796 ps
CPU time 21.81 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:14:02 PM PDT 24
Peak memory 233176 kb
Host smart-69247171-414a-4b8f-aca2-aa263ce69333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847328620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.847328620
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2222932594
Short name T8
Test name
Test status
Simulation time 34438626 ps
CPU time 0.78 seconds
Started Jul 30 05:13:39 PM PDT 24
Finished Jul 30 05:13:40 PM PDT 24
Peak memory 207288 kb
Host smart-662a5898-b9f5-4ce3-ac99-664ea0d2937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222932594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2222932594
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.179710435
Short name T191
Test name
Test status
Simulation time 44155682959 ps
CPU time 114.59 seconds
Started Jul 30 05:13:43 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 257628 kb
Host smart-fde4f43a-6b97-4e1a-b842-d5ef086e6941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179710435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.179710435
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.956260660
Short name T281
Test name
Test status
Simulation time 6042821043 ps
CPU time 42 seconds
Started Jul 30 05:13:45 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 218188 kb
Host smart-b3c54e69-966f-4820-89f6-04b62f1d810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956260660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.956260660
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3519567400
Short name T29
Test name
Test status
Simulation time 7798651348 ps
CPU time 12.75 seconds
Started Jul 30 05:13:45 PM PDT 24
Finished Jul 30 05:13:57 PM PDT 24
Peak memory 218120 kb
Host smart-76c85f6a-55a1-490c-b343-565a62f05494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519567400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3519567400
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1693688386
Short name T451
Test name
Test status
Simulation time 2728965009 ps
CPU time 42.24 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:14:22 PM PDT 24
Peak memory 237672 kb
Host smart-a9434f4a-cc2c-45d6-b980-6a341a6d1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693688386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1693688386
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1161593504
Short name T446
Test name
Test status
Simulation time 9391248002 ps
CPU time 64.3 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:14:44 PM PDT 24
Peak memory 240372 kb
Host smart-3248c6dc-f39b-4200-af13-5dc34899f3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161593504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1161593504
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4195208663
Short name T898
Test name
Test status
Simulation time 2123541074 ps
CPU time 5.15 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:45 PM PDT 24
Peak memory 224940 kb
Host smart-d95ff263-ba1f-47e0-8539-7de823be6ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195208663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4195208663
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2665829391
Short name T737
Test name
Test status
Simulation time 1493455698 ps
CPU time 12.95 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:53 PM PDT 24
Peak memory 224904 kb
Host smart-3a9e39da-922b-45c0-bbb8-cf26fd73ec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665829391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2665829391
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3225189257
Short name T184
Test name
Test status
Simulation time 4514282581 ps
CPU time 15.78 seconds
Started Jul 30 05:13:41 PM PDT 24
Finished Jul 30 05:13:57 PM PDT 24
Peak memory 224944 kb
Host smart-226e390a-679d-4fa5-baff-115e90d112bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225189257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3225189257
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2936963576
Short name T362
Test name
Test status
Simulation time 143722757 ps
CPU time 2.71 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:43 PM PDT 24
Peak memory 233080 kb
Host smart-0307543c-e914-486c-a2cf-6df7e9b7566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936963576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2936963576
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3611436539
Short name T354
Test name
Test status
Simulation time 757645885 ps
CPU time 4.96 seconds
Started Jul 30 05:13:47 PM PDT 24
Finished Jul 30 05:13:52 PM PDT 24
Peak memory 220536 kb
Host smart-75c0e48d-3a3e-42ee-98d3-44bd9ef50a99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3611436539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3611436539
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2582775858
Short name T277
Test name
Test status
Simulation time 7716915131 ps
CPU time 38.31 seconds
Started Jul 30 05:13:39 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 216708 kb
Host smart-5ee5547a-d6e6-49ee-854a-ec24ae4f655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582775858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2582775858
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4044954919
Short name T759
Test name
Test status
Simulation time 707872838 ps
CPU time 3.27 seconds
Started Jul 30 05:13:42 PM PDT 24
Finished Jul 30 05:13:46 PM PDT 24
Peak memory 216668 kb
Host smart-73f6e462-5c75-4e96-9948-23c410e5b78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044954919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4044954919
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1626963090
Short name T327
Test name
Test status
Simulation time 62519415 ps
CPU time 1.77 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:42 PM PDT 24
Peak memory 216656 kb
Host smart-2e6c7341-a868-4109-a604-c48d08222c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626963090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1626963090
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1540352566
Short name T656
Test name
Test status
Simulation time 33358105 ps
CPU time 0.77 seconds
Started Jul 30 05:13:40 PM PDT 24
Finished Jul 30 05:13:41 PM PDT 24
Peak memory 206392 kb
Host smart-1a42a048-15fe-452f-8d0f-9fad040550e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540352566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1540352566
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3529887249
Short name T224
Test name
Test status
Simulation time 375466161 ps
CPU time 5.03 seconds
Started Jul 30 05:13:42 PM PDT 24
Finished Jul 30 05:13:47 PM PDT 24
Peak memory 224844 kb
Host smart-60f43bee-b093-407d-b8d7-02f836b53197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529887249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3529887249
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.355742201
Short name T935
Test name
Test status
Simulation time 11676302 ps
CPU time 0.71 seconds
Started Jul 30 05:13:50 PM PDT 24
Finished Jul 30 05:13:51 PM PDT 24
Peak memory 205268 kb
Host smart-857d8f22-9c47-4570-acf1-3766af1738d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355742201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.355742201
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.107566806
Short name T469
Test name
Test status
Simulation time 8101184540 ps
CPU time 24.66 seconds
Started Jul 30 05:13:46 PM PDT 24
Finished Jul 30 05:14:10 PM PDT 24
Peak memory 224984 kb
Host smart-eae91bea-15b2-438a-8707-98e3382e28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107566806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.107566806
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.127937083
Short name T512
Test name
Test status
Simulation time 19077293 ps
CPU time 0.82 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:13:49 PM PDT 24
Peak memory 207012 kb
Host smart-7d230373-0bf3-484c-b4ae-b208a9c1c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127937083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.127937083
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2502721384
Short name T67
Test name
Test status
Simulation time 180188307358 ps
CPU time 223.88 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:17:32 PM PDT 24
Peak memory 257776 kb
Host smart-f76d557d-f212-41c6-b7e9-6ef7e1eb96bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502721384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2502721384
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4073140958
Short name T192
Test name
Test status
Simulation time 3623740666 ps
CPU time 98.37 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:15:26 PM PDT 24
Peak memory 250488 kb
Host smart-f2b7fb10-0658-4f0b-9b11-c95ef67954cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073140958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4073140958
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3124465715
Short name T126
Test name
Test status
Simulation time 166757599723 ps
CPU time 555.99 seconds
Started Jul 30 05:13:49 PM PDT 24
Finished Jul 30 05:23:05 PM PDT 24
Peak memory 272840 kb
Host smart-aaf157f4-3737-4a92-818f-ba98e69f5bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124465715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3124465715
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1975013528
Short name T274
Test name
Test status
Simulation time 5572711925 ps
CPU time 88.23 seconds
Started Jul 30 05:13:49 PM PDT 24
Finished Jul 30 05:15:18 PM PDT 24
Peak memory 234156 kb
Host smart-bd680baa-9a76-43ab-b441-c2458c37dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975013528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1975013528
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3448825135
Short name T888
Test name
Test status
Simulation time 3574560994 ps
CPU time 50.26 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:14:38 PM PDT 24
Peak memory 257768 kb
Host smart-1332d3ab-bbfa-40dc-8d21-04527d196cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448825135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3448825135
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2766320308
Short name T617
Test name
Test status
Simulation time 638437745 ps
CPU time 6.11 seconds
Started Jul 30 05:13:45 PM PDT 24
Finished Jul 30 05:13:52 PM PDT 24
Peak memory 233144 kb
Host smart-77942224-9e52-49af-8938-b130cab09c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766320308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2766320308
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2012209066
Short name T716
Test name
Test status
Simulation time 1967974718 ps
CPU time 15.03 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:14:03 PM PDT 24
Peak memory 237372 kb
Host smart-c8739764-a09c-40e5-a226-f89f09ad3fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012209066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2012209066
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3380716209
Short name T240
Test name
Test status
Simulation time 1451064781 ps
CPU time 3.2 seconds
Started Jul 30 05:13:46 PM PDT 24
Finished Jul 30 05:13:49 PM PDT 24
Peak memory 233104 kb
Host smart-30abf517-652a-4331-82a0-3194308d8490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380716209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3380716209
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3353815633
Short name T560
Test name
Test status
Simulation time 10757706093 ps
CPU time 32.94 seconds
Started Jul 30 05:13:44 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 233948 kb
Host smart-4076ffef-3bdf-4e9c-94bc-fb7ec7f0730c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353815633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3353815633
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3213954945
Short name T895
Test name
Test status
Simulation time 688850302 ps
CPU time 7.01 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:13:55 PM PDT 24
Peak memory 220828 kb
Host smart-02f4de6c-aa71-49d5-8960-521ba3352b8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3213954945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3213954945
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2450178834
Short name T45
Test name
Test status
Simulation time 39942686906 ps
CPU time 403 seconds
Started Jul 30 05:13:47 PM PDT 24
Finished Jul 30 05:20:30 PM PDT 24
Peak memory 257852 kb
Host smart-72896ec7-dd06-4fba-b3ed-19e1e06c538d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450178834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2450178834
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1050760910
Short name T424
Test name
Test status
Simulation time 2792330272 ps
CPU time 7.44 seconds
Started Jul 30 05:13:45 PM PDT 24
Finished Jul 30 05:13:53 PM PDT 24
Peak memory 220076 kb
Host smart-aca7e405-16aa-40a8-8d53-7e99b581f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050760910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1050760910
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4262834488
Short name T308
Test name
Test status
Simulation time 2679515673 ps
CPU time 4.66 seconds
Started Jul 30 05:13:46 PM PDT 24
Finished Jul 30 05:13:51 PM PDT 24
Peak memory 216676 kb
Host smart-f2e974d0-2f3a-4bba-9add-c879598128fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262834488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4262834488
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2585306991
Short name T743
Test name
Test status
Simulation time 11036996 ps
CPU time 0.69 seconds
Started Jul 30 05:13:49 PM PDT 24
Finished Jul 30 05:13:50 PM PDT 24
Peak memory 206048 kb
Host smart-0cc42810-6cfc-41a0-b2f2-33c8b2e12df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585306991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2585306991
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2594020042
Short name T460
Test name
Test status
Simulation time 17894461 ps
CPU time 0.73 seconds
Started Jul 30 05:13:45 PM PDT 24
Finished Jul 30 05:13:46 PM PDT 24
Peak memory 206356 kb
Host smart-34564576-f907-497a-aea4-9bffdc4ba9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594020042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2594020042
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3491501395
Short name T603
Test name
Test status
Simulation time 658348556 ps
CPU time 5.3 seconds
Started Jul 30 05:13:45 PM PDT 24
Finished Jul 30 05:13:50 PM PDT 24
Peak memory 233100 kb
Host smart-0fa8c996-9412-4d0a-a8b8-7fc1b3200a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491501395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3491501395
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2391771182
Short name T783
Test name
Test status
Simulation time 14123795 ps
CPU time 0.74 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:02 PM PDT 24
Peak memory 205756 kb
Host smart-4ec8e096-e6c4-41ca-a36f-8ae951144407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391771182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
391771182
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3394104750
Short name T950
Test name
Test status
Simulation time 2029628942 ps
CPU time 6.53 seconds
Started Jul 30 05:11:49 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 224904 kb
Host smart-475a7267-f730-41ed-871b-9b2402c5f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394104750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3394104750
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3467505422
Short name T761
Test name
Test status
Simulation time 16460188 ps
CPU time 0.76 seconds
Started Jul 30 05:11:56 PM PDT 24
Finished Jul 30 05:11:57 PM PDT 24
Peak memory 206928 kb
Host smart-40618410-e436-416a-a925-fd589d122b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467505422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3467505422
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1204924386
Short name T710
Test name
Test status
Simulation time 9542754817 ps
CPU time 86.95 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:13:22 PM PDT 24
Peak memory 250676 kb
Host smart-65068484-fd72-4441-8245-cf0c8b8704d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204924386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1204924386
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.424383080
Short name T207
Test name
Test status
Simulation time 16390925890 ps
CPU time 146.12 seconds
Started Jul 30 05:11:52 PM PDT 24
Finished Jul 30 05:14:18 PM PDT 24
Peak memory 255756 kb
Host smart-bda6799d-cbd5-4e11-bc82-8f7f30556de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424383080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.424383080
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.410984309
Short name T679
Test name
Test status
Simulation time 17335942932 ps
CPU time 163.58 seconds
Started Jul 30 05:11:56 PM PDT 24
Finished Jul 30 05:14:40 PM PDT 24
Peak memory 249612 kb
Host smart-d1d72af4-6b45-4c62-8bc2-ec96a82b773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410984309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
410984309
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2249842891
Short name T878
Test name
Test status
Simulation time 1209537139 ps
CPU time 21.13 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:12:12 PM PDT 24
Peak memory 249196 kb
Host smart-e1646e2d-cc1a-470f-b2ab-c09e46c79121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249842891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2249842891
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2784333966
Short name T61
Test name
Test status
Simulation time 22641336627 ps
CPU time 74.61 seconds
Started Jul 30 05:11:49 PM PDT 24
Finished Jul 30 05:13:04 PM PDT 24
Peak memory 253408 kb
Host smart-a4e2775b-a05f-40b6-9774-a86017718e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784333966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2784333966
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3479734853
Short name T777
Test name
Test status
Simulation time 1664977221 ps
CPU time 3.86 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:55 PM PDT 24
Peak memory 233152 kb
Host smart-484033e0-4083-4c5a-8a30-fcd3f9b7f2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479734853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3479734853
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.60754965
Short name T431
Test name
Test status
Simulation time 196064783 ps
CPU time 2.5 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:53 PM PDT 24
Peak memory 224840 kb
Host smart-148e9076-41a6-418a-8ff8-6fea86940e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60754965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.60754965
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3817370415
Short name T535
Test name
Test status
Simulation time 102559143933 ps
CPU time 24.78 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:12:16 PM PDT 24
Peak memory 238676 kb
Host smart-e4942f79-5300-4682-99d5-c998d62461bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817370415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3817370415
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2809732727
Short name T488
Test name
Test status
Simulation time 33187938387 ps
CPU time 22.13 seconds
Started Jul 30 05:11:50 PM PDT 24
Finished Jul 30 05:12:12 PM PDT 24
Peak memory 250844 kb
Host smart-c97a0265-d743-4527-8ae8-00484921dab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809732727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2809732727
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3554469946
Short name T918
Test name
Test status
Simulation time 1492159469 ps
CPU time 11.19 seconds
Started Jul 30 05:11:57 PM PDT 24
Finished Jul 30 05:12:08 PM PDT 24
Peak memory 220652 kb
Host smart-cc557502-f622-4c4f-b413-091fae7b3c1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554469946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3554469946
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4229990205
Short name T55
Test name
Test status
Simulation time 93352797 ps
CPU time 1.19 seconds
Started Jul 30 05:11:56 PM PDT 24
Finished Jul 30 05:11:57 PM PDT 24
Peak memory 236880 kb
Host smart-2c692d6d-6c50-412a-b5e9-cf688e9ce34a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229990205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4229990205
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3213401773
Short name T251
Test name
Test status
Simulation time 57116130468 ps
CPU time 104.57 seconds
Started Jul 30 05:11:54 PM PDT 24
Finished Jul 30 05:13:39 PM PDT 24
Peak memory 252336 kb
Host smart-9b7a2d32-c6fc-4363-b43f-e003a02d22fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213401773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3213401773
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.723430210
Short name T496
Test name
Test status
Simulation time 30076888094 ps
CPU time 35.97 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:12:27 PM PDT 24
Peak memory 216788 kb
Host smart-04d7a47d-0df1-4708-b48c-fab9c38bb7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723430210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.723430210
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2603131360
Short name T917
Test name
Test status
Simulation time 911927342 ps
CPU time 5.15 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 216652 kb
Host smart-40a59150-03fa-4a5f-8018-ce0764b71c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603131360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2603131360
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1118755563
Short name T786
Test name
Test status
Simulation time 32886644 ps
CPU time 0.94 seconds
Started Jul 30 05:11:49 PM PDT 24
Finished Jul 30 05:11:50 PM PDT 24
Peak memory 207048 kb
Host smart-5da9d268-a49a-47ab-b3c2-ca0ff85af17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118755563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1118755563
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3138846512
Short name T1001
Test name
Test status
Simulation time 44771724 ps
CPU time 0.69 seconds
Started Jul 30 05:11:51 PM PDT 24
Finished Jul 30 05:11:52 PM PDT 24
Peak memory 206012 kb
Host smart-b03dc3e4-16e4-4720-a3bf-7fbeb29640dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138846512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3138846512
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1437651464
Short name T787
Test name
Test status
Simulation time 56594576582 ps
CPU time 18.23 seconds
Started Jul 30 05:11:49 PM PDT 24
Finished Jul 30 05:12:07 PM PDT 24
Peak memory 234172 kb
Host smart-dfc73bbb-9c22-4d57-9b05-ddb773ee5519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437651464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1437651464
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3855516931
Short name T846
Test name
Test status
Simulation time 34076902 ps
CPU time 0.71 seconds
Started Jul 30 05:13:53 PM PDT 24
Finished Jul 30 05:13:54 PM PDT 24
Peak memory 205212 kb
Host smart-4c53c660-7cca-48b0-96f6-4360f4fb8f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855516931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3855516931
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1964838494
Short name T497
Test name
Test status
Simulation time 50574184 ps
CPU time 2.25 seconds
Started Jul 30 05:13:54 PM PDT 24
Finished Jul 30 05:13:56 PM PDT 24
Peak memory 224380 kb
Host smart-000be268-a4a4-4458-8069-b574507b1a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964838494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1964838494
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1762924632
Short name T324
Test name
Test status
Simulation time 51174181 ps
CPU time 0.76 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:13:49 PM PDT 24
Peak memory 205908 kb
Host smart-770f29bb-ab95-4fd1-9fd6-1abc1423b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762924632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1762924632
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3551743022
Short name T574
Test name
Test status
Simulation time 67978375123 ps
CPU time 238.92 seconds
Started Jul 30 05:13:52 PM PDT 24
Finished Jul 30 05:17:51 PM PDT 24
Peak memory 241328 kb
Host smart-298c1b49-e4e6-4890-86d1-d254c0383ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551743022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3551743022
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.369452527
Short name T149
Test name
Test status
Simulation time 27136249199 ps
CPU time 262.34 seconds
Started Jul 30 05:13:52 PM PDT 24
Finished Jul 30 05:18:14 PM PDT 24
Peak memory 257772 kb
Host smart-0170b849-d530-4bb7-ba68-c3bfc6619466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369452527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.369452527
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2479524321
Short name T272
Test name
Test status
Simulation time 3972088734 ps
CPU time 33.83 seconds
Started Jul 30 05:13:53 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 241296 kb
Host smart-2c9b4088-80d6-41aa-92bb-4a1c98b58459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479524321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2479524321
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1270223443
Short name T621
Test name
Test status
Simulation time 6738556142 ps
CPU time 13.28 seconds
Started Jul 30 05:13:54 PM PDT 24
Finished Jul 30 05:14:07 PM PDT 24
Peak memory 233156 kb
Host smart-2b6610ba-04fb-4a1d-9874-8b52b2cdacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270223443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1270223443
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3361864063
Short name T124
Test name
Test status
Simulation time 2950047529 ps
CPU time 6.17 seconds
Started Jul 30 05:13:53 PM PDT 24
Finished Jul 30 05:14:00 PM PDT 24
Peak memory 237088 kb
Host smart-87ac01eb-c9cb-42af-a4bf-01ed8aa879b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361864063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3361864063
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3166641278
Short name T922
Test name
Test status
Simulation time 710745463 ps
CPU time 4.43 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:13:53 PM PDT 24
Peak memory 224872 kb
Host smart-bb8868bd-30b9-46f2-911b-e04f049e1ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166641278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3166641278
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1384218483
Short name T26
Test name
Test status
Simulation time 113609703937 ps
CPU time 22.89 seconds
Started Jul 30 05:13:49 PM PDT 24
Finished Jul 30 05:14:12 PM PDT 24
Peak memory 233156 kb
Host smart-ef4600fd-a933-4683-a181-73ff45f70057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384218483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1384218483
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.905632688
Short name T923
Test name
Test status
Simulation time 1413478942 ps
CPU time 9.32 seconds
Started Jul 30 05:13:53 PM PDT 24
Finished Jul 30 05:14:02 PM PDT 24
Peak memory 222456 kb
Host smart-5cfef365-b21a-44fe-bac8-68c1ad1546f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905632688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.905632688
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1084082858
Short name T423
Test name
Test status
Simulation time 67064709 ps
CPU time 1.07 seconds
Started Jul 30 05:13:51 PM PDT 24
Finished Jul 30 05:13:52 PM PDT 24
Peak memory 207620 kb
Host smart-b42b18d8-f879-4268-b60c-2838d5adc6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084082858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1084082858
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.385674588
Short name T475
Test name
Test status
Simulation time 553135166 ps
CPU time 6.8 seconds
Started Jul 30 05:13:49 PM PDT 24
Finished Jul 30 05:13:55 PM PDT 24
Peak memory 216692 kb
Host smart-00502ec9-07f1-4703-8319-b9e95cffe081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385674588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.385674588
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3590068075
Short name T400
Test name
Test status
Simulation time 262677859 ps
CPU time 2.38 seconds
Started Jul 30 05:13:46 PM PDT 24
Finished Jul 30 05:13:49 PM PDT 24
Peak memory 216420 kb
Host smart-dea32011-337b-4a46-b831-734d836e30ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590068075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3590068075
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1105776580
Short name T657
Test name
Test status
Simulation time 236134035 ps
CPU time 1.02 seconds
Started Jul 30 05:13:48 PM PDT 24
Finished Jul 30 05:13:49 PM PDT 24
Peak memory 207404 kb
Host smart-cd93d41d-b120-40da-9146-12225f3a55ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105776580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1105776580
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1023054896
Short name T794
Test name
Test status
Simulation time 73169695 ps
CPU time 0.95 seconds
Started Jul 30 05:13:47 PM PDT 24
Finished Jul 30 05:13:48 PM PDT 24
Peak memory 206348 kb
Host smart-68043b11-fe1f-4f97-8169-199d6a59648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023054896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1023054896
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3724100880
Short name T505
Test name
Test status
Simulation time 226333995 ps
CPU time 2.85 seconds
Started Jul 30 05:13:53 PM PDT 24
Finished Jul 30 05:13:56 PM PDT 24
Peak memory 224904 kb
Host smart-9642b4d9-c088-4003-bfa1-82e5a532418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724100880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3724100880
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.255475638
Short name T982
Test name
Test status
Simulation time 20822148 ps
CPU time 0.72 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 205272 kb
Host smart-9159c30c-b578-4cd1-8836-2ea8b009041b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255475638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.255475638
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2540035759
Short name T378
Test name
Test status
Simulation time 130304660 ps
CPU time 2.59 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:14:01 PM PDT 24
Peak memory 233060 kb
Host smart-31ef8087-b36a-485c-9804-3d3a695d32c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540035759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2540035759
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.237167167
Short name T317
Test name
Test status
Simulation time 15710978 ps
CPU time 0.78 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:13:59 PM PDT 24
Peak memory 207260 kb
Host smart-bd03c872-b47f-406c-ba5e-83f5ce3120d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237167167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.237167167
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2977373109
Short name T704
Test name
Test status
Simulation time 8303159504 ps
CPU time 67.64 seconds
Started Jul 30 05:14:01 PM PDT 24
Finished Jul 30 05:15:08 PM PDT 24
Peak memory 240204 kb
Host smart-bf6f49c5-3b89-4186-9947-b5abe4e2bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977373109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2977373109
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1699629598
Short name T335
Test name
Test status
Simulation time 26313184909 ps
CPU time 44.04 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:49 PM PDT 24
Peak memory 238536 kb
Host smart-52c9afef-6af6-425c-91bd-1341e220417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699629598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1699629598
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1247693973
Short name T953
Test name
Test status
Simulation time 11614769348 ps
CPU time 50.62 seconds
Started Jul 30 05:13:56 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 249564 kb
Host smart-17ed6396-546c-4627-8a86-49659a97f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247693973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1247693973
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.597409014
Short name T707
Test name
Test status
Simulation time 718260036 ps
CPU time 9.76 seconds
Started Jul 30 05:13:57 PM PDT 24
Finished Jul 30 05:14:07 PM PDT 24
Peak memory 233124 kb
Host smart-3b138ac6-14e6-4f40-8ff2-5a7800425708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597409014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.597409014
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2670177758
Short name T665
Test name
Test status
Simulation time 355732361 ps
CPU time 7.93 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:14:10 PM PDT 24
Peak memory 233312 kb
Host smart-e23f9c30-78b2-4c82-9889-9608f3736d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670177758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2670177758
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1629373376
Short name T928
Test name
Test status
Simulation time 8507793517 ps
CPU time 9.64 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:14:08 PM PDT 24
Peak memory 249328 kb
Host smart-6a6c64fc-e722-44f0-b4cb-39f7673e6e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629373376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1629373376
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1927675361
Short name T577
Test name
Test status
Simulation time 770585224 ps
CPU time 8.9 seconds
Started Jul 30 05:13:57 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 233080 kb
Host smart-fc632d74-401d-49a8-9b63-ca89e8effc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927675361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1927675361
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3742492500
Short name T389
Test name
Test status
Simulation time 2427245975 ps
CPU time 4.86 seconds
Started Jul 30 05:13:57 PM PDT 24
Finished Jul 30 05:14:02 PM PDT 24
Peak memory 221148 kb
Host smart-56a6b5a5-6130-42a7-b43e-7cb9e3ff1f93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742492500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3742492500
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3852139669
Short name T17
Test name
Test status
Simulation time 5291282614 ps
CPU time 56.57 seconds
Started Jul 30 05:14:04 PM PDT 24
Finished Jul 30 05:15:00 PM PDT 24
Peak memory 249868 kb
Host smart-58f4ef00-f3a7-44e9-8244-6bf35fc390b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852139669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3852139669
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2873505243
Short name T358
Test name
Test status
Simulation time 578873014 ps
CPU time 2.14 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:14:01 PM PDT 24
Peak memory 216836 kb
Host smart-7422b709-4ae6-4d16-a600-3d52ef380861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873505243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2873505243
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3532991595
Short name T728
Test name
Test status
Simulation time 3325768591 ps
CPU time 6.27 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:14:04 PM PDT 24
Peak memory 216680 kb
Host smart-550c68be-4e06-41b5-b126-5a689592b2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532991595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3532991595
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3460138474
Short name T464
Test name
Test status
Simulation time 349746677 ps
CPU time 2.86 seconds
Started Jul 30 05:13:59 PM PDT 24
Finished Jul 30 05:14:02 PM PDT 24
Peak memory 216676 kb
Host smart-7217b78d-95a1-47cd-82e1-f58d008e42cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460138474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3460138474
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1173582708
Short name T927
Test name
Test status
Simulation time 14552606 ps
CPU time 0.7 seconds
Started Jul 30 05:14:00 PM PDT 24
Finished Jul 30 05:14:01 PM PDT 24
Peak memory 206348 kb
Host smart-d9f8190e-e2ba-4e3c-9f21-acb5d992cd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173582708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1173582708
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2863205453
Short name T223
Test name
Test status
Simulation time 1106944738 ps
CPU time 3.82 seconds
Started Jul 30 05:13:58 PM PDT 24
Finished Jul 30 05:14:02 PM PDT 24
Peak memory 233108 kb
Host smart-24247826-00f2-4b90-9584-0e395d2b768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863205453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2863205453
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3621889235
Short name T879
Test name
Test status
Simulation time 17333499 ps
CPU time 0.72 seconds
Started Jul 30 05:14:07 PM PDT 24
Finished Jul 30 05:14:08 PM PDT 24
Peak memory 205820 kb
Host smart-8f850b8f-dca9-4767-bf2a-3d332598eb6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621889235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3621889235
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3227935992
Short name T549
Test name
Test status
Simulation time 2413094219 ps
CPU time 6.79 seconds
Started Jul 30 05:13:59 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 233160 kb
Host smart-77e2ff10-1122-4210-8cc0-f4618ebbb58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227935992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3227935992
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3165854006
Short name T467
Test name
Test status
Simulation time 64078871 ps
CPU time 0.74 seconds
Started Jul 30 05:14:00 PM PDT 24
Finished Jul 30 05:14:01 PM PDT 24
Peak memory 205948 kb
Host smart-1a796fd2-e54a-4000-9199-994c68d47f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165854006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3165854006
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3156805880
Short name T760
Test name
Test status
Simulation time 10269753698 ps
CPU time 109.77 seconds
Started Jul 30 05:14:06 PM PDT 24
Finished Jul 30 05:15:56 PM PDT 24
Peak memory 250596 kb
Host smart-24be17b4-ab00-470c-b928-b6d93d8267fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156805880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3156805880
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.4053057653
Short name T41
Test name
Test status
Simulation time 233392903431 ps
CPU time 170.78 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:16:56 PM PDT 24
Peak memory 254320 kb
Host smart-daf5eb73-0c4b-4336-b9be-1054845742a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053057653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.4053057653
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4047206022
Short name T490
Test name
Test status
Simulation time 2835844882 ps
CPU time 33.38 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:38 PM PDT 24
Peak memory 239924 kb
Host smart-e0276e9e-5bfe-4e35-a7c0-ce024a6f3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047206022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4047206022
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3469102529
Short name T677
Test name
Test status
Simulation time 111560097 ps
CPU time 4.03 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 233136 kb
Host smart-d2556623-a47e-46d0-a3f9-eedd36be48b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469102529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3469102529
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2654300601
Short name T500
Test name
Test status
Simulation time 74531214537 ps
CPU time 152.1 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 249448 kb
Host smart-14af1889-5eb1-4039-a035-83de65e39015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654300601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2654300601
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1622737882
Short name T363
Test name
Test status
Simulation time 921253100 ps
CPU time 4.18 seconds
Started Jul 30 05:14:01 PM PDT 24
Finished Jul 30 05:14:05 PM PDT 24
Peak memory 224916 kb
Host smart-4b5dbc26-a8e6-4a74-9a47-d4b4405f1278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622737882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1622737882
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1740655870
Short name T219
Test name
Test status
Simulation time 3194604790 ps
CPU time 13.63 seconds
Started Jul 30 05:14:01 PM PDT 24
Finished Jul 30 05:14:15 PM PDT 24
Peak memory 233120 kb
Host smart-90a4c042-4144-4563-980e-cb05e07ce5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740655870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1740655870
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.676735263
Short name T990
Test name
Test status
Simulation time 1628417874 ps
CPU time 7.07 seconds
Started Jul 30 05:14:01 PM PDT 24
Finished Jul 30 05:14:08 PM PDT 24
Peak memory 233124 kb
Host smart-08223a8e-8b0a-42b0-827a-a4e4348304a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676735263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.676735263
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1870790287
Short name T398
Test name
Test status
Simulation time 120946047 ps
CPU time 3.4 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 233100 kb
Host smart-231bfe23-27de-4b13-a6c1-c91ec56b1b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870790287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1870790287
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2972161139
Short name T364
Test name
Test status
Simulation time 1382008138 ps
CPU time 6.25 seconds
Started Jul 30 05:14:00 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 219268 kb
Host smart-cf2e0d0c-53fe-4e6f-b426-36a8af2cfa15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2972161139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2972161139
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2549619085
Short name T36
Test name
Test status
Simulation time 10836372757 ps
CPU time 87.69 seconds
Started Jul 30 05:14:06 PM PDT 24
Finished Jul 30 05:15:34 PM PDT 24
Peak memory 263928 kb
Host smart-73980329-e47c-4324-b64a-399af86e5ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549619085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2549619085
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4282528651
Short name T276
Test name
Test status
Simulation time 3583480544 ps
CPU time 29.15 seconds
Started Jul 30 05:14:00 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 216780 kb
Host smart-fe54860d-bd34-4938-ac6b-ab8027eddec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282528651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4282528651
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.43596970
Short name T515
Test name
Test status
Simulation time 61266294 ps
CPU time 1.19 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 216664 kb
Host smart-b40721c9-d3e8-471a-9c61-e9e301ca3b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43596970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.43596970
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3770673647
Short name T296
Test name
Test status
Simulation time 85913722 ps
CPU time 0.87 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:14:03 PM PDT 24
Peak memory 206432 kb
Host smart-e0be6786-5fa5-4e3b-b13d-5364c66aae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770673647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3770673647
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1105314920
Short name T160
Test name
Test status
Simulation time 11361176588 ps
CPU time 14.18 seconds
Started Jul 30 05:14:02 PM PDT 24
Finished Jul 30 05:14:16 PM PDT 24
Peak memory 233172 kb
Host smart-8c106833-d2a1-485f-95f5-7616f5e91cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105314920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1105314920
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3429436887
Short name T449
Test name
Test status
Simulation time 12727105 ps
CPU time 0.71 seconds
Started Jul 30 05:14:11 PM PDT 24
Finished Jul 30 05:14:12 PM PDT 24
Peak memory 206152 kb
Host smart-95d9a4a3-2484-4805-b01c-d7bd30fd2609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429436887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3429436887
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2387943920
Short name T231
Test name
Test status
Simulation time 166355140 ps
CPU time 2.36 seconds
Started Jul 30 05:14:07 PM PDT 24
Finished Jul 30 05:14:10 PM PDT 24
Peak memory 233140 kb
Host smart-b8ad01c1-6669-4c7e-8189-8279da08ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387943920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2387943920
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4258326361
Short name T369
Test name
Test status
Simulation time 52697012 ps
CPU time 0.79 seconds
Started Jul 30 05:14:04 PM PDT 24
Finished Jul 30 05:14:05 PM PDT 24
Peak memory 206992 kb
Host smart-9463d177-e92a-4274-9780-63d172adbe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258326361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4258326361
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1625034014
Short name T30
Test name
Test status
Simulation time 76932204882 ps
CPU time 228.51 seconds
Started Jul 30 05:14:04 PM PDT 24
Finished Jul 30 05:17:53 PM PDT 24
Peak memory 249604 kb
Host smart-8ba4bc31-e94f-464e-957c-072dfaca404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625034014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1625034014
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1312813361
Short name T27
Test name
Test status
Simulation time 13734105242 ps
CPU time 131.15 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 257788 kb
Host smart-84fe7849-f2b9-4dfc-bc45-7c3e53785908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312813361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1312813361
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2218544460
Short name T956
Test name
Test status
Simulation time 51040942 ps
CPU time 2.95 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:14:15 PM PDT 24
Peak memory 224732 kb
Host smart-22f051de-42ef-4951-a1db-1603e8f662c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218544460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2218544460
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3835653302
Short name T474
Test name
Test status
Simulation time 3569781853 ps
CPU time 29.87 seconds
Started Jul 30 05:14:11 PM PDT 24
Finished Jul 30 05:14:41 PM PDT 24
Peak memory 237968 kb
Host smart-0c73ca69-acc3-4434-8230-c993afa1d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835653302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3835653302
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4232972390
Short name T542
Test name
Test status
Simulation time 911965107 ps
CPU time 6.63 seconds
Started Jul 30 05:14:11 PM PDT 24
Finished Jul 30 05:14:18 PM PDT 24
Peak memory 233168 kb
Host smart-ec2250fb-1458-4644-a3bd-3d2988a6a320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232972390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4232972390
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2188651214
Short name T435
Test name
Test status
Simulation time 125724583 ps
CPU time 2.54 seconds
Started Jul 30 05:14:07 PM PDT 24
Finished Jul 30 05:14:10 PM PDT 24
Peak memory 232856 kb
Host smart-a35a602a-cd7e-447c-961e-89642c1f63fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188651214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2188651214
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2192839562
Short name T215
Test name
Test status
Simulation time 247030315 ps
CPU time 2.67 seconds
Started Jul 30 05:14:13 PM PDT 24
Finished Jul 30 05:14:15 PM PDT 24
Peak memory 233168 kb
Host smart-2be6c516-68be-4197-89ae-3ac29ad2f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192839562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2192839562
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2203754779
Short name T523
Test name
Test status
Simulation time 552799866 ps
CPU time 5.81 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:14:18 PM PDT 24
Peak memory 222728 kb
Host smart-8a15e3c6-17dd-4e98-9671-fa4a3a493345
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2203754779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2203754779
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.748316835
Short name T457
Test name
Test status
Simulation time 5674101996 ps
CPU time 34.55 seconds
Started Jul 30 05:14:08 PM PDT 24
Finished Jul 30 05:14:43 PM PDT 24
Peak memory 216816 kb
Host smart-255d9560-ab86-46d0-b6c4-cac4593651bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748316835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.748316835
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.521085122
Short name T494
Test name
Test status
Simulation time 12214761363 ps
CPU time 10 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:15 PM PDT 24
Peak memory 216540 kb
Host smart-8d418503-50b0-4388-9140-bdc888f58c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521085122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.521085122
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.829472240
Short name T912
Test name
Test status
Simulation time 120274854 ps
CPU time 1.41 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:06 PM PDT 24
Peak memory 216628 kb
Host smart-686affd4-c2c4-425c-8f8a-62f49a9b0e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829472240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.829472240
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.293379589
Short name T533
Test name
Test status
Simulation time 28754591 ps
CPU time 0.84 seconds
Started Jul 30 05:14:06 PM PDT 24
Finished Jul 30 05:14:07 PM PDT 24
Peak memory 206360 kb
Host smart-45170f2c-1b28-477f-810d-2ecb01db8cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293379589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.293379589
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3370916637
Short name T938
Test name
Test status
Simulation time 9228627398 ps
CPU time 30.17 seconds
Started Jul 30 05:14:05 PM PDT 24
Finished Jul 30 05:14:36 PM PDT 24
Peak memory 233132 kb
Host smart-b9edd98f-2cfe-4202-baaf-03cfb01b0bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370916637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3370916637
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1231550233
Short name T822
Test name
Test status
Simulation time 57604662 ps
CPU time 0.72 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:14:11 PM PDT 24
Peak memory 205252 kb
Host smart-f2467b21-43d5-4218-b64b-1bda9c8c55af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231550233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1231550233
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1913218619
Short name T804
Test name
Test status
Simulation time 375345823 ps
CPU time 5.91 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:14:16 PM PDT 24
Peak memory 233136 kb
Host smart-f0ae84fa-4ae2-495c-9b8c-15f4d56a201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913218619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1913218619
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1134144855
Short name T417
Test name
Test status
Simulation time 34850560 ps
CPU time 0.75 seconds
Started Jul 30 05:14:13 PM PDT 24
Finished Jul 30 05:14:14 PM PDT 24
Peak memory 207004 kb
Host smart-74ca8c49-2209-4157-8094-dc3459baf771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134144855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1134144855
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1403647218
Short name T150
Test name
Test status
Simulation time 30406961271 ps
CPU time 204.69 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:17:37 PM PDT 24
Peak memory 251368 kb
Host smart-305e7ff7-fb53-45f3-a19a-c6852b1f2ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403647218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1403647218
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2518225317
Short name T189
Test name
Test status
Simulation time 16422864407 ps
CPU time 40.64 seconds
Started Jul 30 05:14:11 PM PDT 24
Finished Jul 30 05:14:52 PM PDT 24
Peak memory 255252 kb
Host smart-c00b5003-efeb-4b96-b388-437e92f6935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518225317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2518225317
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1572588177
Short name T252
Test name
Test status
Simulation time 109716166303 ps
CPU time 328.96 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:19:41 PM PDT 24
Peak memory 264152 kb
Host smart-121023b3-60c6-4f30-ae6b-f2851ca94df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572588177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1572588177
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3186141170
Short name T359
Test name
Test status
Simulation time 357407413 ps
CPU time 2.96 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:14:13 PM PDT 24
Peak memory 224820 kb
Host smart-a3dcc478-cfd4-40e7-ad5a-1d35b872c261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186141170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3186141170
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3098126572
Short name T406
Test name
Test status
Simulation time 19698642683 ps
CPU time 139.05 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:16:31 PM PDT 24
Peak memory 254240 kb
Host smart-020d68b3-7132-44db-955c-333bfa232eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098126572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3098126572
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.467893345
Short name T204
Test name
Test status
Simulation time 209052438 ps
CPU time 5.31 seconds
Started Jul 30 05:14:11 PM PDT 24
Finished Jul 30 05:14:16 PM PDT 24
Peak memory 233172 kb
Host smart-1b81901a-aeba-4072-9f1d-f5246d9ae2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467893345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.467893345
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3229918590
Short name T810
Test name
Test status
Simulation time 10447601948 ps
CPU time 28.93 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:14:39 PM PDT 24
Peak memory 249304 kb
Host smart-2df00c53-eb0b-4482-bb71-1f72402d364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229918590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3229918590
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1279319955
Short name T253
Test name
Test status
Simulation time 299350929 ps
CPU time 4.43 seconds
Started Jul 30 05:14:13 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 224972 kb
Host smart-ed69d0bc-62ee-423f-85cd-9927c412e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279319955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1279319955
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.881492930
Short name T594
Test name
Test status
Simulation time 3768386262 ps
CPU time 19.85 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 252612 kb
Host smart-dc8b0ec0-3f07-496a-a6da-e665d3dc30fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881492930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.881492930
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2463641199
Short name T386
Test name
Test status
Simulation time 1578517474 ps
CPU time 7.85 seconds
Started Jul 30 05:14:12 PM PDT 24
Finished Jul 30 05:14:20 PM PDT 24
Peak memory 221068 kb
Host smart-25fcf366-4a53-4017-9156-f867ac6c5ae0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2463641199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2463641199
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.979914964
Short name T675
Test name
Test status
Simulation time 83879073 ps
CPU time 1.03 seconds
Started Jul 30 05:14:08 PM PDT 24
Finished Jul 30 05:14:09 PM PDT 24
Peak memory 216344 kb
Host smart-8d63d6a7-84ab-4fbc-82af-f6095d32a5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979914964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.979914964
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1886012418
Short name T287
Test name
Test status
Simulation time 7366169521 ps
CPU time 22.75 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:14:33 PM PDT 24
Peak memory 216756 kb
Host smart-567df437-988b-4e35-8b17-8422ec077d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886012418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1886012418
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1170023921
Short name T818
Test name
Test status
Simulation time 1166153338 ps
CPU time 3.08 seconds
Started Jul 30 05:14:09 PM PDT 24
Finished Jul 30 05:14:12 PM PDT 24
Peak memory 216528 kb
Host smart-446714f5-4c13-4e48-8ce8-fa975d9bde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170023921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1170023921
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.133476132
Short name T838
Test name
Test status
Simulation time 45707791 ps
CPU time 1.22 seconds
Started Jul 30 05:14:13 PM PDT 24
Finished Jul 30 05:14:14 PM PDT 24
Peak memory 216580 kb
Host smart-7e59b02d-d1df-4967-94d5-d8132952bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133476132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.133476132
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2721788328
Short name T684
Test name
Test status
Simulation time 136316359 ps
CPU time 0.98 seconds
Started Jul 30 05:14:14 PM PDT 24
Finished Jul 30 05:14:15 PM PDT 24
Peak memory 206388 kb
Host smart-918db51e-2491-4a2b-8cf2-998dda0adf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721788328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2721788328
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.436041829
Short name T211
Test name
Test status
Simulation time 20501392753 ps
CPU time 18.86 seconds
Started Jul 30 05:14:10 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 239700 kb
Host smart-4949402b-b4bd-4fe4-a01f-1388cd732747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436041829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.436041829
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2295459156
Short name T673
Test name
Test status
Simulation time 100317719 ps
CPU time 0.72 seconds
Started Jul 30 05:14:18 PM PDT 24
Finished Jul 30 05:14:19 PM PDT 24
Peak memory 206240 kb
Host smart-247fb6dd-9caf-4a94-8596-5e686f3bae6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295459156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2295459156
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3195055164
Short name T161
Test name
Test status
Simulation time 1102781056 ps
CPU time 9.3 seconds
Started Jul 30 05:14:16 PM PDT 24
Finished Jul 30 05:14:25 PM PDT 24
Peak memory 224900 kb
Host smart-848ae453-9ba8-4574-82ea-ce6869952ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195055164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3195055164
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1998865577
Short name T486
Test name
Test status
Simulation time 104038690 ps
CPU time 0.76 seconds
Started Jul 30 05:14:18 PM PDT 24
Finished Jul 30 05:14:19 PM PDT 24
Peak memory 206448 kb
Host smart-4a4f17e4-2499-4b45-8843-109bbbd7230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998865577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1998865577
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.559022527
Short name T267
Test name
Test status
Simulation time 55923347788 ps
CPU time 239.01 seconds
Started Jul 30 05:14:17 PM PDT 24
Finished Jul 30 05:18:16 PM PDT 24
Peak memory 250352 kb
Host smart-479d3012-0751-4a1e-97f9-d8b22a4f1981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559022527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.559022527
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4270941920
Short name T668
Test name
Test status
Simulation time 3590804739 ps
CPU time 13.1 seconds
Started Jul 30 05:14:15 PM PDT 24
Finished Jul 30 05:14:28 PM PDT 24
Peak memory 217980 kb
Host smart-5c6557ed-b3a1-44aa-b431-c51877b4cde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270941920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4270941920
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1349767870
Short name T280
Test name
Test status
Simulation time 6564240341 ps
CPU time 41.91 seconds
Started Jul 30 05:14:18 PM PDT 24
Finished Jul 30 05:15:00 PM PDT 24
Peak memory 249928 kb
Host smart-8f4704f9-e7e5-4f61-89a6-2f2b7bf330ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349767870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1349767870
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.184891682
Short name T694
Test name
Test status
Simulation time 474785124 ps
CPU time 4.35 seconds
Started Jul 30 05:14:15 PM PDT 24
Finished Jul 30 05:14:20 PM PDT 24
Peak memory 233336 kb
Host smart-0af16b48-86dd-4306-82dc-7a17c381c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184891682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.184891682
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1468541935
Short name T325
Test name
Test status
Simulation time 35742186602 ps
CPU time 81.86 seconds
Started Jul 30 05:14:17 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 250644 kb
Host smart-4bb4adad-5653-414e-ab18-aea79d72fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468541935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1468541935
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2710149939
Short name T721
Test name
Test status
Simulation time 488278918 ps
CPU time 4.22 seconds
Started Jul 30 05:14:13 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 233160 kb
Host smart-ee9ed35c-55d6-4104-acf2-475c0fc5bddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710149939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2710149939
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2950534203
Short name T597
Test name
Test status
Simulation time 3486221443 ps
CPU time 47.24 seconds
Started Jul 30 05:14:15 PM PDT 24
Finished Jul 30 05:15:03 PM PDT 24
Peak memory 235700 kb
Host smart-b7279e1f-f5dd-4392-b2ff-d2abcb676c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950534203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2950534203
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1182672449
Short name T84
Test name
Test status
Simulation time 12868017852 ps
CPU time 30.72 seconds
Started Jul 30 05:14:16 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 233152 kb
Host smart-6e32b1fb-5227-4ac5-8e83-ca4bd07005bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182672449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1182672449
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3184396794
Short name T614
Test name
Test status
Simulation time 3372199210 ps
CPU time 11.97 seconds
Started Jul 30 05:14:14 PM PDT 24
Finished Jul 30 05:14:26 PM PDT 24
Peak memory 233244 kb
Host smart-2d8affe3-7235-4109-be22-2bc997747104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184396794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3184396794
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4185046709
Short name T615
Test name
Test status
Simulation time 626341581 ps
CPU time 7.88 seconds
Started Jul 30 05:14:14 PM PDT 24
Finished Jul 30 05:14:22 PM PDT 24
Peak memory 219304 kb
Host smart-ce0e1ca6-1ca4-4527-8d95-80138d8d850d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185046709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4185046709
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1540399287
Short name T875
Test name
Test status
Simulation time 19802810566 ps
CPU time 149.04 seconds
Started Jul 30 05:14:19 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 249624 kb
Host smart-abdac5c0-abf0-437e-b7c0-38db601797d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540399287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1540399287
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.101386718
Short name T454
Test name
Test status
Simulation time 20431166663 ps
CPU time 51.1 seconds
Started Jul 30 05:14:14 PM PDT 24
Finished Jul 30 05:15:05 PM PDT 24
Peak memory 216676 kb
Host smart-9ff709a5-e68e-4a45-a9ce-e99f2f21a0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101386718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.101386718
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3332172491
Short name T292
Test name
Test status
Simulation time 6225076017 ps
CPU time 16.28 seconds
Started Jul 30 05:14:15 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 216612 kb
Host smart-dbb553d5-d6c3-45f0-91f0-4ed70d0209b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332172491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3332172491
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3211951884
Short name T304
Test name
Test status
Simulation time 27643310 ps
CPU time 1.05 seconds
Started Jul 30 05:14:16 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 208236 kb
Host smart-4d698cc6-143d-41a9-9cba-ac3f0ebe7f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211951884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3211951884
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2924386360
Short name T859
Test name
Test status
Simulation time 88220170 ps
CPU time 0.82 seconds
Started Jul 30 05:14:16 PM PDT 24
Finished Jul 30 05:14:16 PM PDT 24
Peak memory 206360 kb
Host smart-ae0cec13-8eef-4841-95d1-f8abe674a648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924386360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2924386360
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.522846805
Short name T642
Test name
Test status
Simulation time 415024952 ps
CPU time 2.55 seconds
Started Jul 30 05:14:15 PM PDT 24
Finished Jul 30 05:14:18 PM PDT 24
Peak memory 224904 kb
Host smart-1d010d68-066d-4497-834a-e057970dc096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522846805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.522846805
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.58495258
Short name T771
Test name
Test status
Simulation time 36288383 ps
CPU time 0.66 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 206128 kb
Host smart-10691ff9-b6d5-46a7-912c-a2680edfcb86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58495258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.58495258
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3327657287
Short name T77
Test name
Test status
Simulation time 86892564 ps
CPU time 2.38 seconds
Started Jul 30 05:14:17 PM PDT 24
Finished Jul 30 05:14:20 PM PDT 24
Peak memory 233152 kb
Host smart-e9c87e24-f06c-47d4-a225-f719e1c6ad38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327657287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3327657287
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3801197229
Short name T887
Test name
Test status
Simulation time 43668550 ps
CPU time 0.78 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:14:23 PM PDT 24
Peak memory 206824 kb
Host smart-5b4296ec-fa12-4bf8-966b-14ecb69a191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801197229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3801197229
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1009972609
Short name T812
Test name
Test status
Simulation time 19484038770 ps
CPU time 87.68 seconds
Started Jul 30 05:14:25 PM PDT 24
Finished Jul 30 05:15:53 PM PDT 24
Peak memory 254320 kb
Host smart-147099d9-5954-477c-8033-c13736332636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009972609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1009972609
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4140310700
Short name T197
Test name
Test status
Simulation time 11478934360 ps
CPU time 130.58 seconds
Started Jul 30 05:14:22 PM PDT 24
Finished Jul 30 05:16:33 PM PDT 24
Peak memory 255544 kb
Host smart-8782eca4-fb47-4380-80ce-ef7b30110e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140310700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4140310700
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1518250205
Short name T5
Test name
Test status
Simulation time 211122314 ps
CPU time 3.6 seconds
Started Jul 30 05:14:19 PM PDT 24
Finished Jul 30 05:14:22 PM PDT 24
Peak memory 224896 kb
Host smart-900117e4-b822-4ba4-955e-d560f67bcf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518250205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1518250205
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3226648906
Short name T195
Test name
Test status
Simulation time 6766305953 ps
CPU time 67.44 seconds
Started Jul 30 05:14:19 PM PDT 24
Finished Jul 30 05:15:27 PM PDT 24
Peak memory 250864 kb
Host smart-4f04b4e6-3193-48b8-b0cd-349bb4af6e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226648906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3226648906
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1043610421
Short name T959
Test name
Test status
Simulation time 238845164 ps
CPU time 4.07 seconds
Started Jul 30 05:14:18 PM PDT 24
Finished Jul 30 05:14:22 PM PDT 24
Peak memory 233152 kb
Host smart-5fadb662-b666-426b-85f9-389aedbf9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043610421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1043610421
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3503053856
Short name T241
Test name
Test status
Simulation time 12404108602 ps
CPU time 51.73 seconds
Started Jul 30 05:14:19 PM PDT 24
Finished Jul 30 05:15:11 PM PDT 24
Peak memory 233380 kb
Host smart-71c17396-988e-4706-8061-aa8d110ea93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503053856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3503053856
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2477738228
Short name T639
Test name
Test status
Simulation time 2913838696 ps
CPU time 5.68 seconds
Started Jul 30 05:14:21 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 233192 kb
Host smart-597f1bca-bb5f-488f-ab4b-5107a9016458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477738228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2477738228
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.976750794
Short name T501
Test name
Test status
Simulation time 1826250743 ps
CPU time 7.82 seconds
Started Jul 30 05:14:21 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 233160 kb
Host smart-594ba912-45d6-446a-a0da-f56f5974a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976750794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.976750794
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3064508395
Short name T908
Test name
Test status
Simulation time 856185915 ps
CPU time 7.12 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:14:31 PM PDT 24
Peak memory 223076 kb
Host smart-bcc1bfc0-2c12-4ba7-8ed9-49bd5558bdd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064508395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3064508395
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.646037634
Short name T678
Test name
Test status
Simulation time 431191769 ps
CPU time 3.15 seconds
Started Jul 30 05:14:18 PM PDT 24
Finished Jul 30 05:14:21 PM PDT 24
Peak memory 216836 kb
Host smart-941a743a-6cef-4f63-83bf-6153661ed82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646037634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.646037634
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4037546357
Short name T426
Test name
Test status
Simulation time 17889298914 ps
CPU time 11.55 seconds
Started Jul 30 05:14:17 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 216680 kb
Host smart-0fc93706-0b19-47f4-8e7a-0fd275e37642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037546357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4037546357
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3123367075
Short name T430
Test name
Test status
Simulation time 156670573 ps
CPU time 6.4 seconds
Started Jul 30 05:14:21 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 216680 kb
Host smart-07e9673b-182a-4739-90e3-a68de1202a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123367075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3123367075
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1870719369
Short name T733
Test name
Test status
Simulation time 18384883 ps
CPU time 0.72 seconds
Started Jul 30 05:14:19 PM PDT 24
Finished Jul 30 05:14:20 PM PDT 24
Peak memory 206348 kb
Host smart-a2eeef5e-1559-49ae-b872-0b4cf1966a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870719369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1870719369
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2365683136
Short name T246
Test name
Test status
Simulation time 2263833694 ps
CPU time 6.8 seconds
Started Jul 30 05:14:20 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 233380 kb
Host smart-e3959597-00e3-4820-a505-b6592e8e7c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365683136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2365683136
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2608487154
Short name T470
Test name
Test status
Simulation time 11233702 ps
CPU time 0.65 seconds
Started Jul 30 05:14:29 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 205796 kb
Host smart-eedc2bbf-1831-4c9f-956a-1458122d1a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608487154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2608487154
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2431239577
Short name T945
Test name
Test status
Simulation time 153513917 ps
CPU time 2.71 seconds
Started Jul 30 05:14:22 PM PDT 24
Finished Jul 30 05:14:25 PM PDT 24
Peak memory 233132 kb
Host smart-061ec86f-3e53-4131-9a42-b122f583b320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431239577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2431239577
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3863866318
Short name T709
Test name
Test status
Simulation time 34543725 ps
CPU time 0.83 seconds
Started Jul 30 05:14:24 PM PDT 24
Finished Jul 30 05:14:25 PM PDT 24
Peak memory 206892 kb
Host smart-4dd7adba-7f58-46ba-9dca-45e3c44882e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863866318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3863866318
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.635241032
Short name T263
Test name
Test status
Simulation time 38622242328 ps
CPU time 140.29 seconds
Started Jul 30 05:14:27 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 257336 kb
Host smart-b39e03f8-1709-4e33-bb62-792a912f593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635241032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.635241032
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2698265847
Short name T979
Test name
Test status
Simulation time 33479735633 ps
CPU time 146.87 seconds
Started Jul 30 05:14:25 PM PDT 24
Finished Jul 30 05:16:52 PM PDT 24
Peak memory 252236 kb
Host smart-c86f3f9a-b872-4111-8f61-eee1c0124f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698265847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2698265847
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1420944635
Short name T214
Test name
Test status
Simulation time 8680044901 ps
CPU time 113.17 seconds
Started Jul 30 05:14:28 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 267024 kb
Host smart-2520ce65-c7ab-4543-9589-0dc5fc8a58d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420944635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1420944635
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.299548965
Short name T619
Test name
Test status
Simulation time 2348594391 ps
CPU time 13.26 seconds
Started Jul 30 05:14:22 PM PDT 24
Finished Jul 30 05:14:35 PM PDT 24
Peak memory 233176 kb
Host smart-112ac4b5-1923-46ae-b89f-5e4b78d91f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299548965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.299548965
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1865532487
Short name T420
Test name
Test status
Simulation time 12113415363 ps
CPU time 124.83 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:16:28 PM PDT 24
Peak memory 266928 kb
Host smart-cc681a00-3875-4b72-bfda-8242f869c847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865532487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1865532487
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.927125275
Short name T540
Test name
Test status
Simulation time 2714635559 ps
CPU time 7.33 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:14:30 PM PDT 24
Peak memory 224960 kb
Host smart-ec34272a-98f9-473e-9bcb-99c4f99b29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927125275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.927125275
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3492209510
Short name T584
Test name
Test status
Simulation time 10298583939 ps
CPU time 128.16 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:16:31 PM PDT 24
Peak memory 233236 kb
Host smart-2c97eb82-d0fb-47cd-a1ae-a5041e568b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492209510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3492209510
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.288198215
Short name T825
Test name
Test status
Simulation time 5896587663 ps
CPU time 3.36 seconds
Started Jul 30 05:14:23 PM PDT 24
Finished Jul 30 05:14:26 PM PDT 24
Peak memory 225016 kb
Host smart-4a1969eb-b665-46ee-b1b3-cf021896d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288198215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.288198215
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1332687661
Short name T729
Test name
Test status
Simulation time 10739838914 ps
CPU time 18.63 seconds
Started Jul 30 05:14:24 PM PDT 24
Finished Jul 30 05:14:43 PM PDT 24
Peak memory 233176 kb
Host smart-3a2ae391-ac96-43e9-826c-f4fe67be0ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332687661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1332687661
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2907153203
Short name T643
Test name
Test status
Simulation time 306726499 ps
CPU time 3.69 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:14:30 PM PDT 24
Peak memory 223640 kb
Host smart-96e93363-452a-4f98-bef8-1ef4948b6473
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2907153203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2907153203
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2841042836
Short name T129
Test name
Test status
Simulation time 90110638814 ps
CPU time 439.85 seconds
Started Jul 30 05:14:28 PM PDT 24
Finished Jul 30 05:21:48 PM PDT 24
Peak memory 274208 kb
Host smart-7a844031-5dd4-477e-9e37-9fd98a6b1dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841042836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2841042836
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.270685978
Short name T602
Test name
Test status
Simulation time 5816588767 ps
CPU time 27.82 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:14:54 PM PDT 24
Peak memory 216712 kb
Host smart-4280ef4c-102b-4e12-a7f5-3f8c5c932922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270685978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.270685978
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4196595667
Short name T973
Test name
Test status
Simulation time 2051770837 ps
CPU time 9.42 seconds
Started Jul 30 05:14:22 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 216648 kb
Host smart-2ddb137f-e746-4f80-ad02-a1fb5f783dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196595667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4196595667
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3345192240
Short name T647
Test name
Test status
Simulation time 11838891 ps
CPU time 0.84 seconds
Started Jul 30 05:14:27 PM PDT 24
Finished Jul 30 05:14:28 PM PDT 24
Peak memory 207084 kb
Host smart-24a54ff2-98c2-48e1-9787-433016ef42fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345192240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3345192240
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1152970523
Short name T404
Test name
Test status
Simulation time 172282592 ps
CPU time 0.84 seconds
Started Jul 30 05:14:24 PM PDT 24
Finished Jul 30 05:14:25 PM PDT 24
Peak memory 206320 kb
Host smart-ac90abdc-2916-43c9-8608-c772954f7539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152970523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1152970523
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1920448767
Short name T570
Test name
Test status
Simulation time 6399183103 ps
CPU time 24.44 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:14:51 PM PDT 24
Peak memory 233268 kb
Host smart-f85b8a59-b101-4d75-941e-d06c9d1cc662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920448767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1920448767
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3796417564
Short name T885
Test name
Test status
Simulation time 17461738 ps
CPU time 0.7 seconds
Started Jul 30 05:14:30 PM PDT 24
Finished Jul 30 05:14:30 PM PDT 24
Peak memory 205256 kb
Host smart-191db147-969a-4bee-84a6-f8f0a20acfdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796417564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3796417564
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.348155299
Short name T782
Test name
Test status
Simulation time 1139245773 ps
CPU time 5.12 seconds
Started Jul 30 05:14:32 PM PDT 24
Finished Jul 30 05:14:37 PM PDT 24
Peak memory 224920 kb
Host smart-09e15340-1c42-42eb-9ba5-45236a2ec72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348155299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.348155299
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.877772520
Short name T868
Test name
Test status
Simulation time 83101898 ps
CPU time 0.79 seconds
Started Jul 30 05:14:28 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 207028 kb
Host smart-8a887275-b0df-489d-93f5-36ff2f1f6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877772520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.877772520
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.565681166
Short name T382
Test name
Test status
Simulation time 94838033146 ps
CPU time 164.91 seconds
Started Jul 30 05:14:32 PM PDT 24
Finished Jul 30 05:17:17 PM PDT 24
Peak memory 257228 kb
Host smart-f24f4526-0f62-4015-828f-4e909414e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565681166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.565681166
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.648032721
Short name T328
Test name
Test status
Simulation time 1644517165 ps
CPU time 39.16 seconds
Started Jul 30 05:14:32 PM PDT 24
Finished Jul 30 05:15:11 PM PDT 24
Peak memory 241432 kb
Host smart-60a350c0-cb5f-4f2c-8e45-022fc7b22bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648032721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.648032721
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3675194704
Short name T168
Test name
Test status
Simulation time 89523070030 ps
CPU time 214.52 seconds
Started Jul 30 05:14:30 PM PDT 24
Finished Jul 30 05:18:05 PM PDT 24
Peak memory 249612 kb
Host smart-5e73cbd8-6b8e-490e-a8bd-0312ab782f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675194704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3675194704
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.765093520
Short name T268
Test name
Test status
Simulation time 1795225923 ps
CPU time 10.58 seconds
Started Jul 30 05:14:32 PM PDT 24
Finished Jul 30 05:14:42 PM PDT 24
Peak memory 240708 kb
Host smart-40e47970-0fdd-4183-becc-f0a3ecf5118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765093520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.765093520
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2543174569
Short name T39
Test name
Test status
Simulation time 3493879313 ps
CPU time 44.38 seconds
Started Jul 30 05:14:30 PM PDT 24
Finished Jul 30 05:15:14 PM PDT 24
Peak memory 254788 kb
Host smart-03ced867-27e0-45d5-8955-41370ba4b6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543174569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2543174569
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.549243005
Short name T920
Test name
Test status
Simulation time 9588519103 ps
CPU time 13.67 seconds
Started Jul 30 05:14:28 PM PDT 24
Finished Jul 30 05:14:41 PM PDT 24
Peak memory 233120 kb
Host smart-3540a297-295c-495e-96b2-f621152d348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549243005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.549243005
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.843604010
Short name T762
Test name
Test status
Simulation time 1504890238 ps
CPU time 15.52 seconds
Started Jul 30 05:14:29 PM PDT 24
Finished Jul 30 05:14:44 PM PDT 24
Peak memory 224912 kb
Host smart-f7fce451-946e-4516-8753-07c2251a5d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843604010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.843604010
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2417459
Short name T718
Test name
Test status
Simulation time 1085155297 ps
CPU time 4.31 seconds
Started Jul 30 05:14:27 PM PDT 24
Finished Jul 30 05:14:31 PM PDT 24
Peak memory 224880 kb
Host smart-aab34c09-4120-487c-95c2-16a30ec8add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.2417459
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.174179280
Short name T626
Test name
Test status
Simulation time 19060365265 ps
CPU time 14.78 seconds
Started Jul 30 05:14:27 PM PDT 24
Finished Jul 30 05:14:42 PM PDT 24
Peak memory 233176 kb
Host smart-033a19d7-066a-427c-ae9b-5a8515802125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174179280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.174179280
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4263931686
Short name T987
Test name
Test status
Simulation time 3617051583 ps
CPU time 13.41 seconds
Started Jul 30 05:14:31 PM PDT 24
Finished Jul 30 05:14:45 PM PDT 24
Peak memory 222496 kb
Host smart-3ae5d991-7404-4d84-9844-9db5a5e5ca01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4263931686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4263931686
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1560271835
Short name T864
Test name
Test status
Simulation time 123487072 ps
CPU time 0.86 seconds
Started Jul 30 05:14:31 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 206304 kb
Host smart-7f158b34-f249-4614-aadc-b2a818f91266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560271835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1560271835
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4264851667
Short name T943
Test name
Test status
Simulation time 7204330926 ps
CPU time 39.16 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:15:05 PM PDT 24
Peak memory 216780 kb
Host smart-2abcc8bc-e899-4fd7-98c9-3644266261d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264851667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4264851667
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.807714913
Short name T741
Test name
Test status
Simulation time 1684737356 ps
CPU time 3.26 seconds
Started Jul 30 05:14:28 PM PDT 24
Finished Jul 30 05:14:31 PM PDT 24
Peak memory 216580 kb
Host smart-3184a4f2-42bd-4342-a167-6b72d2673778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807714913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.807714913
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1237953656
Short name T924
Test name
Test status
Simulation time 49660466 ps
CPU time 1.49 seconds
Started Jul 30 05:14:27 PM PDT 24
Finished Jul 30 05:14:29 PM PDT 24
Peak memory 216668 kb
Host smart-17a3b717-e8be-4ea8-a6c3-5e1ef2c37116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237953656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1237953656
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.177828926
Short name T368
Test name
Test status
Simulation time 47796820 ps
CPU time 0.83 seconds
Started Jul 30 05:14:26 PM PDT 24
Finished Jul 30 05:14:27 PM PDT 24
Peak memory 206388 kb
Host smart-ff4a61a9-a3a7-48a4-9eb3-076db9b6bd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177828926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.177828926
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2591451396
Short name T319
Test name
Test status
Simulation time 10819689801 ps
CPU time 16.64 seconds
Started Jul 30 05:14:34 PM PDT 24
Finished Jul 30 05:14:51 PM PDT 24
Peak memory 230808 kb
Host smart-1ca70f32-cc7a-4b0a-a9c6-fac45564180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591451396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2591451396
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1413836145
Short name T37
Test name
Test status
Simulation time 14049213 ps
CPU time 0.71 seconds
Started Jul 30 05:14:35 PM PDT 24
Finished Jul 30 05:14:36 PM PDT 24
Peak memory 205852 kb
Host smart-320d0e59-d14e-42b2-aee8-eaa404aa1c83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413836145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1413836145
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3004034319
Short name T972
Test name
Test status
Simulation time 284684489 ps
CPU time 2.51 seconds
Started Jul 30 05:14:36 PM PDT 24
Finished Jul 30 05:14:39 PM PDT 24
Peak memory 224932 kb
Host smart-f720dba7-e537-443a-8509-2878d564afdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004034319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3004034319
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.882883569
Short name T897
Test name
Test status
Simulation time 33329201 ps
CPU time 0.79 seconds
Started Jul 30 05:14:31 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 207324 kb
Host smart-509d9538-6edf-474e-b5bc-e96f0ecd9222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882883569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.882883569
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1076630275
Short name T850
Test name
Test status
Simulation time 65544276476 ps
CPU time 110.86 seconds
Started Jul 30 05:14:37 PM PDT 24
Finished Jul 30 05:16:28 PM PDT 24
Peak memory 241368 kb
Host smart-cafa4151-9a2f-459c-939b-a3417965f486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076630275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1076630275
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3152227039
Short name T255
Test name
Test status
Simulation time 18080779102 ps
CPU time 97.57 seconds
Started Jul 30 05:14:37 PM PDT 24
Finished Jul 30 05:16:14 PM PDT 24
Peak memory 256252 kb
Host smart-41545983-b4f7-4dda-96a9-d7eb9cdeebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152227039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3152227039
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4121849998
Short name T555
Test name
Test status
Simulation time 9235823220 ps
CPU time 60.22 seconds
Started Jul 30 05:14:37 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 256620 kb
Host smart-478f10de-c877-4049-a183-06ca48e1f331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121849998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4121849998
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3867940186
Short name T585
Test name
Test status
Simulation time 7878493625 ps
CPU time 16.86 seconds
Started Jul 30 05:14:36 PM PDT 24
Finished Jul 30 05:14:53 PM PDT 24
Peak memory 249552 kb
Host smart-88d7fa27-8c98-4a51-8008-2cd6dde0166b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867940186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3867940186
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2686239941
Short name T872
Test name
Test status
Simulation time 9142098515 ps
CPU time 36.05 seconds
Started Jul 30 05:14:36 PM PDT 24
Finished Jul 30 05:15:12 PM PDT 24
Peak memory 233080 kb
Host smart-fa714282-edde-4397-80dd-6351661cd8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686239941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2686239941
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.257734309
Short name T705
Test name
Test status
Simulation time 1300812926 ps
CPU time 16.49 seconds
Started Jul 30 05:14:35 PM PDT 24
Finished Jul 30 05:14:52 PM PDT 24
Peak memory 224940 kb
Host smart-728b82f5-3566-462b-b956-3ebc4bb2fb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257734309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.257734309
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.528095822
Short name T551
Test name
Test status
Simulation time 1826714745 ps
CPU time 21.27 seconds
Started Jul 30 05:14:34 PM PDT 24
Finished Jul 30 05:14:55 PM PDT 24
Peak memory 234192 kb
Host smart-df816cd4-17fe-441b-80c0-db6ee1de950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528095822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.528095822
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.580509144
Short name T796
Test name
Test status
Simulation time 11652773856 ps
CPU time 9.79 seconds
Started Jul 30 05:14:35 PM PDT 24
Finished Jul 30 05:14:45 PM PDT 24
Peak memory 233160 kb
Host smart-de62948d-853d-48f4-92ba-89c50143cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580509144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.580509144
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.313734472
Short name T222
Test name
Test status
Simulation time 12439225000 ps
CPU time 10.3 seconds
Started Jul 30 05:14:37 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 224848 kb
Host smart-7beab264-830c-4d16-911f-99bf7725436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313734472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.313734472
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.959665624
Short name T492
Test name
Test status
Simulation time 627245277 ps
CPU time 6.05 seconds
Started Jul 30 05:14:35 PM PDT 24
Finished Jul 30 05:14:41 PM PDT 24
Peak memory 222416 kb
Host smart-884318f3-3462-46b5-ba84-ecd908ba92cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=959665624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.959665624
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1603904724
Short name T855
Test name
Test status
Simulation time 184586403897 ps
CPU time 198.51 seconds
Started Jul 30 05:14:36 PM PDT 24
Finished Jul 30 05:17:54 PM PDT 24
Peak memory 268548 kb
Host smart-a9ffa932-6ee3-44ca-be32-c43b34c04481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603904724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1603904724
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2789296879
Short name T373
Test name
Test status
Simulation time 5109304397 ps
CPU time 28.09 seconds
Started Jul 30 05:14:30 PM PDT 24
Finished Jul 30 05:14:58 PM PDT 24
Peak memory 220792 kb
Host smart-cadc919b-9c1c-47ed-a595-a12df32d346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789296879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2789296879
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.532075202
Short name T310
Test name
Test status
Simulation time 7755341122 ps
CPU time 9.37 seconds
Started Jul 30 05:14:32 PM PDT 24
Finished Jul 30 05:14:41 PM PDT 24
Peak memory 216620 kb
Host smart-dce4780a-51c8-4c8a-8e88-4b98ac66a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532075202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.532075202
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3763185269
Short name T712
Test name
Test status
Simulation time 170669495 ps
CPU time 2.35 seconds
Started Jul 30 05:14:30 PM PDT 24
Finished Jul 30 05:14:32 PM PDT 24
Peak memory 216636 kb
Host smart-5b191516-5cbe-46b1-b55f-d6c553cfc3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763185269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3763185269
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3856074577
Short name T337
Test name
Test status
Simulation time 52043377 ps
CPU time 0.93 seconds
Started Jul 30 05:14:33 PM PDT 24
Finished Jul 30 05:14:34 PM PDT 24
Peak memory 206520 kb
Host smart-a1d622a1-a38d-4fd2-8a8c-cc79f45e97dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856074577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3856074577
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3803563032
Short name T371
Test name
Test status
Simulation time 10063350880 ps
CPU time 15.7 seconds
Started Jul 30 05:14:35 PM PDT 24
Finished Jul 30 05:14:51 PM PDT 24
Peak memory 225000 kb
Host smart-31163de8-9282-4bdc-ad8a-1938c9b931f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803563032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3803563032
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3067451815
Short name T495
Test name
Test status
Simulation time 12100742 ps
CPU time 0.75 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:12:04 PM PDT 24
Peak memory 205328 kb
Host smart-09befe43-77e1-42fc-9dcc-35e213351fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067451815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
067451815
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2159496329
Short name T598
Test name
Test status
Simulation time 882036068 ps
CPU time 3.02 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:11:58 PM PDT 24
Peak memory 224912 kb
Host smart-7935260d-7207-48f9-be53-1cf9e4e508c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159496329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2159496329
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2121423411
Short name T644
Test name
Test status
Simulation time 52751980 ps
CPU time 0.77 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 206992 kb
Host smart-8ab61096-6af7-43da-ab7d-e74696641420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121423411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2121423411
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3492196534
Short name T12
Test name
Test status
Simulation time 327511767091 ps
CPU time 224.3 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:15:47 PM PDT 24
Peak memory 252792 kb
Host smart-387ebde3-9b89-47a1-a378-a6bab4181f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492196534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3492196534
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2417770333
Short name T997
Test name
Test status
Simulation time 11421797734 ps
CPU time 61.85 seconds
Started Jul 30 05:11:59 PM PDT 24
Finished Jul 30 05:13:01 PM PDT 24
Peak memory 237216 kb
Host smart-a00e8b23-7d84-4212-a81b-0d339f5ccf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417770333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2417770333
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1126391892
Short name T471
Test name
Test status
Simulation time 2033077886 ps
CPU time 41.44 seconds
Started Jul 30 05:11:59 PM PDT 24
Finished Jul 30 05:12:41 PM PDT 24
Peak memory 253144 kb
Host smart-100846cf-d8a0-4007-b53a-68d2b2215793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126391892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1126391892
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2642676807
Short name T971
Test name
Test status
Simulation time 4404890956 ps
CPU time 21.82 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 233460 kb
Host smart-8dbce217-62a8-4a34-961c-7ffda95ccb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642676807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2642676807
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2322095715
Short name T230
Test name
Test status
Simulation time 2991754117 ps
CPU time 6.97 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:08 PM PDT 24
Peak memory 233160 kb
Host smart-ed0cb4e1-ce72-4f69-a12c-e0e94ef7a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322095715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2322095715
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1861749794
Short name T572
Test name
Test status
Simulation time 234194111 ps
CPU time 4.94 seconds
Started Jul 30 05:11:54 PM PDT 24
Finished Jul 30 05:12:00 PM PDT 24
Peak memory 224900 kb
Host smart-2fa97ea5-9b76-4d85-bfde-45cccb19275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861749794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1861749794
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2113619304
Short name T238
Test name
Test status
Simulation time 3813348395 ps
CPU time 13.69 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:12:09 PM PDT 24
Peak memory 249528 kb
Host smart-a9d8089e-97a4-4e51-8deb-35844a973702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113619304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2113619304
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2044383700
Short name T820
Test name
Test status
Simulation time 506408001 ps
CPU time 6.49 seconds
Started Jul 30 05:11:54 PM PDT 24
Finished Jul 30 05:12:01 PM PDT 24
Peak memory 233104 kb
Host smart-f41982b9-66db-4df2-a098-f3243303fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044383700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2044383700
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2018385350
Short name T3
Test name
Test status
Simulation time 769545997 ps
CPU time 5.01 seconds
Started Jul 30 05:11:58 PM PDT 24
Finished Jul 30 05:12:03 PM PDT 24
Peak memory 222708 kb
Host smart-5dae6144-3b16-47fd-aff3-c58662f9d2ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2018385350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2018385350
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2257296618
Short name T57
Test name
Test status
Simulation time 161135504 ps
CPU time 1.22 seconds
Started Jul 30 05:12:04 PM PDT 24
Finished Jul 30 05:12:05 PM PDT 24
Peak memory 236904 kb
Host smart-ee94811e-e6db-4562-8c67-70a5bf256274
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257296618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2257296618
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1927946411
Short name T978
Test name
Test status
Simulation time 305436376 ps
CPU time 1.18 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:03 PM PDT 24
Peak memory 208076 kb
Host smart-e0d75bf5-802a-4a09-bec4-fe556829b144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927946411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1927946411
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4045028764
Short name T591
Test name
Test status
Simulation time 50070024171 ps
CPU time 25.45 seconds
Started Jul 30 05:11:54 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 216692 kb
Host smart-64a3e0b3-59b8-4b4b-b20e-46034e0ef264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045028764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4045028764
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.55139753
Short name T75
Test name
Test status
Simulation time 908055162 ps
CPU time 3.98 seconds
Started Jul 30 05:11:57 PM PDT 24
Finished Jul 30 05:12:01 PM PDT 24
Peak memory 216644 kb
Host smart-1cf1883f-916d-442c-9693-4d6f7f4eb023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55139753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.55139753
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3320066766
Short name T631
Test name
Test status
Simulation time 535545852 ps
CPU time 1.42 seconds
Started Jul 30 05:11:54 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 216576 kb
Host smart-4e7b9594-4cad-455a-ba1c-d579a960abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320066766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3320066766
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3158569264
Short name T976
Test name
Test status
Simulation time 75362123 ps
CPU time 0.91 seconds
Started Jul 30 05:11:55 PM PDT 24
Finished Jul 30 05:11:56 PM PDT 24
Peak memory 206244 kb
Host smart-cccfe0fe-20b7-4045-aa17-24e633567d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158569264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3158569264
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2725277778
Short name T809
Test name
Test status
Simulation time 148631559 ps
CPU time 2.77 seconds
Started Jul 30 05:11:57 PM PDT 24
Finished Jul 30 05:12:00 PM PDT 24
Peak memory 224908 kb
Host smart-823ef0c2-ee8d-4377-bf19-e89af82476f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725277778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2725277778
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1450779862
Short name T744
Test name
Test status
Simulation time 23444489 ps
CPU time 0.68 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:14:40 PM PDT 24
Peak memory 205220 kb
Host smart-b96327b3-fe8b-44e3-9a31-e8b21f349720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450779862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1450779862
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2232555220
Short name T64
Test name
Test status
Simulation time 6037793446 ps
CPU time 4.98 seconds
Started Jul 30 05:14:41 PM PDT 24
Finished Jul 30 05:14:46 PM PDT 24
Peak memory 224980 kb
Host smart-798dd614-2c85-42e5-962d-312c7e4388eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232555220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2232555220
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1727061448
Short name T23
Test name
Test status
Simulation time 50076329 ps
CPU time 0.77 seconds
Started Jul 30 05:14:36 PM PDT 24
Finished Jul 30 05:14:36 PM PDT 24
Peak memory 207300 kb
Host smart-cad77b28-ab0b-4980-9ea1-d7a0d2b161a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727061448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1727061448
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1422059983
Short name T623
Test name
Test status
Simulation time 50246652196 ps
CPU time 200.34 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:18:01 PM PDT 24
Peak memory 251248 kb
Host smart-827fee58-3b14-4b16-8c4a-829bb242268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422059983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1422059983
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2563352687
Short name T635
Test name
Test status
Simulation time 22237638774 ps
CPU time 91.56 seconds
Started Jul 30 05:14:41 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 249632 kb
Host smart-172c4401-a6ca-4732-a4cd-9ba5c8827ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563352687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2563352687
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1237706008
Short name T130
Test name
Test status
Simulation time 361303112617 ps
CPU time 197.21 seconds
Started Jul 30 05:14:39 PM PDT 24
Finished Jul 30 05:17:56 PM PDT 24
Peak memory 249652 kb
Host smart-e4a3542c-a4fa-4fb0-8b89-3a8732785d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237706008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1237706008
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4185980425
Short name T748
Test name
Test status
Simulation time 11667293208 ps
CPU time 38.86 seconds
Started Jul 30 05:14:39 PM PDT 24
Finished Jul 30 05:15:18 PM PDT 24
Peak memory 235256 kb
Host smart-26acad98-c5e8-4830-8c26-2090fca5a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185980425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4185980425
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.584913744
Short name T966
Test name
Test status
Simulation time 25568855 ps
CPU time 0.73 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:46 PM PDT 24
Peak memory 215940 kb
Host smart-991a9174-e005-42f9-ab3b-fb30dd7dee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584913744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.584913744
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1967760064
Short name T552
Test name
Test status
Simulation time 1714513464 ps
CPU time 4 seconds
Started Jul 30 05:14:41 PM PDT 24
Finished Jul 30 05:14:45 PM PDT 24
Peak memory 225000 kb
Host smart-ebb804ad-0281-449e-89ef-56b1012d708d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967760064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1967760064
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1919780939
Short name T210
Test name
Test status
Simulation time 635663453 ps
CPU time 6.97 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 224924 kb
Host smart-e27917c4-3542-4594-a0be-dea1be9b615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919780939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1919780939
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2837429350
Short name T901
Test name
Test status
Simulation time 56040285 ps
CPU time 1.91 seconds
Started Jul 30 05:14:43 PM PDT 24
Finished Jul 30 05:14:45 PM PDT 24
Peak memory 223240 kb
Host smart-50d28ca1-a64b-41c9-8575-032353443e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837429350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2837429350
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4290818172
Short name T227
Test name
Test status
Simulation time 1490703768 ps
CPU time 9.1 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:14:50 PM PDT 24
Peak memory 233124 kb
Host smart-5d2860e4-8eef-47b3-bf75-2fe4079ebe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290818172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4290818172
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3517699653
Short name T40
Test name
Test status
Simulation time 222860752 ps
CPU time 3.28 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:14:43 PM PDT 24
Peak memory 220756 kb
Host smart-1f618fda-fc84-4479-b6d3-f3eb80fb80dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3517699653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3517699653
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1013760957
Short name T883
Test name
Test status
Simulation time 177664745 ps
CPU time 1.03 seconds
Started Jul 30 05:14:41 PM PDT 24
Finished Jul 30 05:14:42 PM PDT 24
Peak memory 205912 kb
Host smart-65812e22-f42a-4323-b76a-d02f41bb5454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013760957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1013760957
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3039956749
Short name T284
Test name
Test status
Simulation time 4776162006 ps
CPU time 28.13 seconds
Started Jul 30 05:14:39 PM PDT 24
Finished Jul 30 05:15:07 PM PDT 24
Peak memory 216688 kb
Host smart-bc47eb6d-a17e-4f37-b5d2-3e8500d9d6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039956749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3039956749
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3396608977
Short name T817
Test name
Test status
Simulation time 41490684494 ps
CPU time 25.25 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:15:05 PM PDT 24
Peak memory 216708 kb
Host smart-951d3073-8506-4c66-b570-fb65f6d610b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396608977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3396608977
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.999565095
Short name T434
Test name
Test status
Simulation time 54812386 ps
CPU time 1.04 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:46 PM PDT 24
Peak memory 208060 kb
Host smart-6bd1cea7-71fa-457e-91db-b0d45abcf0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999565095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.999565095
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3990850045
Short name T905
Test name
Test status
Simulation time 104507921 ps
CPU time 0.79 seconds
Started Jul 30 05:14:37 PM PDT 24
Finished Jul 30 05:14:38 PM PDT 24
Peak memory 206328 kb
Host smart-05df0ae5-fc3a-4bb1-9bfc-6f71b5d5c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990850045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3990850045
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.672889534
Short name T447
Test name
Test status
Simulation time 651159370 ps
CPU time 9.3 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:14:49 PM PDT 24
Peak memory 233164 kb
Host smart-b1122790-96e6-488c-b57b-7b2037a651e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672889534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.672889534
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3909719463
Short name T853
Test name
Test status
Simulation time 14488242 ps
CPU time 0.71 seconds
Started Jul 30 05:14:50 PM PDT 24
Finished Jul 30 05:14:51 PM PDT 24
Peak memory 205788 kb
Host smart-bb92167c-95fc-4767-9910-521f502beb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909719463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3909719463
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3805419408
Short name T660
Test name
Test status
Simulation time 61650697 ps
CPU time 2.84 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 224924 kb
Host smart-44377967-cae2-41b5-a9f7-aafdd865862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805419408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3805419408
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1117735059
Short name T456
Test name
Test status
Simulation time 47139171 ps
CPU time 0.79 seconds
Started Jul 30 05:14:40 PM PDT 24
Finished Jul 30 05:14:41 PM PDT 24
Peak memory 205928 kb
Host smart-b14cca87-4fc7-4bfb-95f2-58c9de9ff5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117735059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1117735059
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.262579436
Short name T749
Test name
Test status
Simulation time 1294590581 ps
CPU time 16.45 seconds
Started Jul 30 05:14:51 PM PDT 24
Finished Jul 30 05:15:07 PM PDT 24
Peak memory 224796 kb
Host smart-5b8d497f-5e26-446d-8af7-f3147de8ab81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262579436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.262579436
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3114057396
Short name T258
Test name
Test status
Simulation time 11019099356 ps
CPU time 121.36 seconds
Started Jul 30 05:14:50 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 270624 kb
Host smart-47790188-5498-41c8-89e3-c01d7724bbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114057396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3114057396
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1439058186
Short name T977
Test name
Test status
Simulation time 150230943 ps
CPU time 5.75 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:50 PM PDT 24
Peak memory 224932 kb
Host smart-c28c0dcc-c043-458c-a948-21d48d027742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439058186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1439058186
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2038757327
Short name T158
Test name
Test status
Simulation time 5838578008 ps
CPU time 31.68 seconds
Started Jul 30 05:14:46 PM PDT 24
Finished Jul 30 05:15:18 PM PDT 24
Peak memory 224960 kb
Host smart-76044ae4-435f-4a7c-bba1-cf335b61db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038757327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2038757327
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.54374744
Short name T47
Test name
Test status
Simulation time 5317553475 ps
CPU time 12.65 seconds
Started Jul 30 05:14:46 PM PDT 24
Finished Jul 30 05:14:58 PM PDT 24
Peak memory 229348 kb
Host smart-bf4c8483-6362-4021-b18b-e62a57c20561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54374744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.54374744
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1307094244
Short name T339
Test name
Test status
Simulation time 1577039620 ps
CPU time 8.86 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:53 PM PDT 24
Peak memory 236216 kb
Host smart-654aa87f-ceca-49cd-ab61-1ac8cab60f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307094244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1307094244
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1277624059
Short name T385
Test name
Test status
Simulation time 742817489 ps
CPU time 4.67 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:49 PM PDT 24
Peak memory 233104 kb
Host smart-e76b2b02-e311-47c0-a7a2-fdd343ff9379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277624059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1277624059
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2016641513
Short name T852
Test name
Test status
Simulation time 10038071474 ps
CPU time 14.58 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:59 PM PDT 24
Peak memory 224968 kb
Host smart-3227789b-d8bc-4bc8-a752-026468cb2492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016641513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2016641513
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1423822450
Short name T478
Test name
Test status
Simulation time 2320116835 ps
CPU time 10.44 seconds
Started Jul 30 05:14:45 PM PDT 24
Finished Jul 30 05:14:56 PM PDT 24
Peak memory 222092 kb
Host smart-fb7402fc-e685-4951-984a-5fccd20815d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423822450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1423822450
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2548520266
Short name T357
Test name
Test status
Simulation time 1079692998 ps
CPU time 19.53 seconds
Started Jul 30 05:14:49 PM PDT 24
Finished Jul 30 05:15:09 PM PDT 24
Peak memory 223688 kb
Host smart-dd59026e-047a-49ae-a277-9e31b5900d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548520266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2548520266
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2232832512
Short name T884
Test name
Test status
Simulation time 2346094152 ps
CPU time 5.66 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:50 PM PDT 24
Peak memory 217004 kb
Host smart-070b9abd-3882-44ba-ad9d-bb3f0927cad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232832512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2232832512
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.738571014
Short name T121
Test name
Test status
Simulation time 2291946332 ps
CPU time 7.43 seconds
Started Jul 30 05:14:41 PM PDT 24
Finished Jul 30 05:14:49 PM PDT 24
Peak memory 216724 kb
Host smart-a5cf3ecf-40bf-412b-9831-080c0531b487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738571014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.738571014
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1485436427
Short name T854
Test name
Test status
Simulation time 51734265 ps
CPU time 1.25 seconds
Started Jul 30 05:14:45 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 216680 kb
Host smart-603979f1-e983-46c2-9ae2-99db64e4d6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485436427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1485436427
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2190435760
Short name T379
Test name
Test status
Simulation time 96935574 ps
CPU time 0.82 seconds
Started Jul 30 05:14:46 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 206348 kb
Host smart-800fc169-9882-4b5b-b1e6-b46d26d35044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190435760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2190435760
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1820779470
Short name T392
Test name
Test status
Simulation time 134825689 ps
CPU time 2.23 seconds
Started Jul 30 05:14:44 PM PDT 24
Finished Jul 30 05:14:47 PM PDT 24
Peak memory 224924 kb
Host smart-4485b3e8-bad3-4749-8177-ddac7a6b4602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820779470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1820779470
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2074082331
Short name T565
Test name
Test status
Simulation time 49357204 ps
CPU time 0.69 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:14:55 PM PDT 24
Peak memory 205656 kb
Host smart-862ce11a-2fbe-4af1-9316-6218ad92b4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074082331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2074082331
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1337061343
Short name T351
Test name
Test status
Simulation time 34300578 ps
CPU time 2.38 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:14:56 PM PDT 24
Peak memory 232816 kb
Host smart-763603da-15cc-4912-a1ab-f715a75e30c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337061343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1337061343
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3353788141
Short name T402
Test name
Test status
Simulation time 15882755 ps
CPU time 0.72 seconds
Started Jul 30 05:14:49 PM PDT 24
Finished Jul 30 05:14:50 PM PDT 24
Peak memory 207240 kb
Host smart-88dd7023-9292-47b9-bc6e-84b5a108b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353788141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3353788141
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1267306136
Short name T403
Test name
Test status
Simulation time 32892241897 ps
CPU time 86.31 seconds
Started Jul 30 05:14:53 PM PDT 24
Finished Jul 30 05:16:19 PM PDT 24
Peak memory 251612 kb
Host smart-b5dcd361-89a7-4dbc-a9b9-80099c95d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267306136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1267306136
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1525057229
Short name T840
Test name
Test status
Simulation time 3807298581 ps
CPU time 55.05 seconds
Started Jul 30 05:14:53 PM PDT 24
Finished Jul 30 05:15:48 PM PDT 24
Peak memory 257768 kb
Host smart-1a884060-4ad1-46e1-af29-9a499e13e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525057229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1525057229
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2718556551
Short name T427
Test name
Test status
Simulation time 2161389398 ps
CPU time 17.73 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:15:12 PM PDT 24
Peak memory 241408 kb
Host smart-01874299-4866-4cc4-afda-ff58b0105a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718556551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2718556551
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1799717877
Short name T815
Test name
Test status
Simulation time 2742730438 ps
CPU time 27.62 seconds
Started Jul 30 05:14:57 PM PDT 24
Finished Jul 30 05:15:24 PM PDT 24
Peak memory 224976 kb
Host smart-6de4ba01-8860-4265-bd0a-c6e1428dcf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799717877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1799717877
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1641427899
Short name T578
Test name
Test status
Simulation time 148868325864 ps
CPU time 310.1 seconds
Started Jul 30 05:14:52 PM PDT 24
Finished Jul 30 05:20:02 PM PDT 24
Peak memory 257704 kb
Host smart-579dd665-60b3-4ac1-b88d-5e8ece8e521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641427899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1641427899
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.691139241
Short name T393
Test name
Test status
Simulation time 2068022988 ps
CPU time 6.05 seconds
Started Jul 30 05:14:49 PM PDT 24
Finished Jul 30 05:14:55 PM PDT 24
Peak memory 233064 kb
Host smart-e4aaefd0-c8ca-4739-bc11-781fcb410bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691139241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.691139241
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2478971225
Short name T297
Test name
Test status
Simulation time 843403207 ps
CPU time 3.03 seconds
Started Jul 30 05:14:49 PM PDT 24
Finished Jul 30 05:14:53 PM PDT 24
Peak memory 224868 kb
Host smart-b852b48a-7a29-4b79-9126-c975a4f4f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478971225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2478971225
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4240079665
Short name T321
Test name
Test status
Simulation time 485104896 ps
CPU time 3.64 seconds
Started Jul 30 05:14:49 PM PDT 24
Finished Jul 30 05:14:53 PM PDT 24
Peak memory 233112 kb
Host smart-f424ebb7-ba5e-40af-8330-3a018129d7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240079665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4240079665
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.456188891
Short name T194
Test name
Test status
Simulation time 11183980966 ps
CPU time 31.13 seconds
Started Jul 30 05:14:50 PM PDT 24
Finished Jul 30 05:15:21 PM PDT 24
Peak memory 233368 kb
Host smart-e1bd572c-dfe2-4187-966b-f31856ab4656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456188891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.456188891
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2878910230
Short name T836
Test name
Test status
Simulation time 238755462 ps
CPU time 3.43 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:14:58 PM PDT 24
Peak memory 224052 kb
Host smart-baf43a19-d98c-4936-827b-540f384a2f95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2878910230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2878910230
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1992101736
Short name T148
Test name
Test status
Simulation time 10813179630 ps
CPU time 105.11 seconds
Started Jul 30 05:14:55 PM PDT 24
Finished Jul 30 05:16:41 PM PDT 24
Peak memory 250372 kb
Host smart-eaee6d1d-8292-4b15-bd66-3bb906031589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992101736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1992101736
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2239092707
Short name T984
Test name
Test status
Simulation time 16171271095 ps
CPU time 23.63 seconds
Started Jul 30 05:14:48 PM PDT 24
Finished Jul 30 05:15:12 PM PDT 24
Peak memory 216740 kb
Host smart-fa84545f-28f8-4577-a65f-42a6131e2d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239092707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2239092707
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2700924210
Short name T514
Test name
Test status
Simulation time 6631440830 ps
CPU time 5.64 seconds
Started Jul 30 05:14:47 PM PDT 24
Finished Jul 30 05:14:52 PM PDT 24
Peak memory 216712 kb
Host smart-c584b843-add7-4056-ae69-7d514b07c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700924210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2700924210
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.392575242
Short name T502
Test name
Test status
Simulation time 160533858 ps
CPU time 0.91 seconds
Started Jul 30 05:14:48 PM PDT 24
Finished Jul 30 05:14:49 PM PDT 24
Peak memory 207380 kb
Host smart-e0659231-3fb9-481b-b16b-7be667e05e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392575242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.392575242
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1914179253
Short name T388
Test name
Test status
Simulation time 72166505 ps
CPU time 0.73 seconds
Started Jul 30 05:14:48 PM PDT 24
Finished Jul 30 05:14:49 PM PDT 24
Peak memory 206376 kb
Host smart-ac4d6b17-6644-42eb-a46c-3fd8545f293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914179253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1914179253
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1686898809
Short name T937
Test name
Test status
Simulation time 2726797538 ps
CPU time 7.54 seconds
Started Jul 30 05:14:52 PM PDT 24
Finished Jul 30 05:15:00 PM PDT 24
Peak memory 233164 kb
Host smart-6177d87a-105a-4652-b1cf-ebded07764a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686898809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1686898809
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4249546377
Short name T302
Test name
Test status
Simulation time 49534174 ps
CPU time 0.74 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:15:08 PM PDT 24
Peak memory 205276 kb
Host smart-b5abd8fb-5a55-431f-8aa4-2fabeb9fd013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249546377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4249546377
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1533437524
Short name T242
Test name
Test status
Simulation time 1559796740 ps
CPU time 6.86 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:15:01 PM PDT 24
Peak memory 233124 kb
Host smart-a158ceda-724d-43d3-b3bf-7030b7dda747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533437524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1533437524
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4165905741
Short name T313
Test name
Test status
Simulation time 12390887 ps
CPU time 0.75 seconds
Started Jul 30 05:14:53 PM PDT 24
Finished Jul 30 05:14:54 PM PDT 24
Peak memory 205968 kb
Host smart-1fd289ad-f394-4394-9ba5-6605e8cd089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165905741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4165905741
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.525773984
Short name T480
Test name
Test status
Simulation time 24931806568 ps
CPU time 96.6 seconds
Started Jul 30 05:14:59 PM PDT 24
Finished Jul 30 05:16:36 PM PDT 24
Peak memory 249764 kb
Host smart-8adbab2f-ceee-4edf-98c3-fbf1ff33fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525773984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.525773984
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2463425353
Short name T11
Test name
Test status
Simulation time 33891297266 ps
CPU time 151.33 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:17:26 PM PDT 24
Peak memory 240436 kb
Host smart-9d606e8a-357f-4adb-b2cf-232d1896b492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463425353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2463425353
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3897300477
Short name T415
Test name
Test status
Simulation time 2781345518 ps
CPU time 66.7 seconds
Started Jul 30 05:14:58 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 257376 kb
Host smart-3ddfbc40-6166-419b-9376-66c4617e4298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897300477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3897300477
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4266880164
Short name T269
Test name
Test status
Simulation time 2658733376 ps
CPU time 26.84 seconds
Started Jul 30 05:14:53 PM PDT 24
Finished Jul 30 05:15:20 PM PDT 24
Peak memory 241220 kb
Host smart-9c28c9cc-8653-4c8a-93b6-05745e10385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266880164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4266880164
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2897546996
Short name T536
Test name
Test status
Simulation time 8974044681 ps
CPU time 47.21 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:15:41 PM PDT 24
Peak memory 255496 kb
Host smart-4a723452-5ba7-4133-be66-0d4d23052fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897546996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2897546996
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.145875846
Short name T440
Test name
Test status
Simulation time 1573693053 ps
CPU time 18.02 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:15:12 PM PDT 24
Peak memory 224892 kb
Host smart-0a666648-fbda-43dd-bd7d-0f2b9791c303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145875846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.145875846
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.542294
Short name T670
Test name
Test status
Simulation time 1015100648 ps
CPU time 6.94 seconds
Started Jul 30 05:14:55 PM PDT 24
Finished Jul 30 05:15:03 PM PDT 24
Peak memory 234416 kb
Host smart-9b81d53d-9ae6-4f8b-ae32-f83c15b5fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.542294
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.775465647
Short name T726
Test name
Test status
Simulation time 190256512152 ps
CPU time 26.9 seconds
Started Jul 30 05:14:53 PM PDT 24
Finished Jul 30 05:15:20 PM PDT 24
Peak memory 233160 kb
Host smart-254e243d-2187-4e51-94c3-de70e9b3f202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775465647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.775465647
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1064546883
Short name T1000
Test name
Test status
Simulation time 805311306 ps
CPU time 4.68 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:14:58 PM PDT 24
Peak memory 241296 kb
Host smart-86f24760-6f03-4f3b-ab0f-09452e837086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064546883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1064546883
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2796401613
Short name T770
Test name
Test status
Simulation time 412394974 ps
CPU time 4.24 seconds
Started Jul 30 05:14:55 PM PDT 24
Finished Jul 30 05:15:00 PM PDT 24
Peak memory 223028 kb
Host smart-58044fe1-b91e-4415-97fe-06f8ce04aff8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2796401613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2796401613
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4022068320
Short name T32
Test name
Test status
Simulation time 4064638717 ps
CPU time 39.43 seconds
Started Jul 30 05:14:56 PM PDT 24
Finished Jul 30 05:15:36 PM PDT 24
Peak memory 241436 kb
Host smart-1bc2c0f4-2096-470f-a294-f32e37e5faa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022068320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4022068320
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.890683082
Short name T573
Test name
Test status
Simulation time 58755673 ps
CPU time 0.69 seconds
Started Jul 30 05:14:55 PM PDT 24
Finished Jul 30 05:14:55 PM PDT 24
Peak memory 205952 kb
Host smart-2666c57a-53fa-4537-a71a-8b93ea4e9623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890683082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.890683082
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1959258488
Short name T580
Test name
Test status
Simulation time 408599979 ps
CPU time 3.21 seconds
Started Jul 30 05:14:54 PM PDT 24
Finished Jul 30 05:14:58 PM PDT 24
Peak memory 216616 kb
Host smart-9b22ec23-3d8a-486a-a61c-8607d3fbe262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959258488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1959258488
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4039647058
Short name T563
Test name
Test status
Simulation time 90520927 ps
CPU time 2.11 seconds
Started Jul 30 05:14:56 PM PDT 24
Finished Jul 30 05:14:58 PM PDT 24
Peak memory 216696 kb
Host smart-983fc34b-0ec1-4c76-ab8a-ee73e8af9c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039647058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4039647058
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2202918203
Short name T6
Test name
Test status
Simulation time 38204524 ps
CPU time 0.78 seconds
Started Jul 30 05:14:52 PM PDT 24
Finished Jul 30 05:14:52 PM PDT 24
Peak memory 206352 kb
Host smart-54c08f10-d85b-454b-b81d-c9cd44a4294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202918203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2202918203
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.646955151
Short name T605
Test name
Test status
Simulation time 150980451 ps
CPU time 2.57 seconds
Started Jul 30 05:14:52 PM PDT 24
Finished Jul 30 05:14:55 PM PDT 24
Peak memory 233108 kb
Host smart-7a9f66d3-d79d-435d-a24d-a0dfd42908f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646955151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.646955151
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3130908433
Short name T816
Test name
Test status
Simulation time 11928865 ps
CPU time 0.71 seconds
Started Jul 30 05:15:02 PM PDT 24
Finished Jul 30 05:15:03 PM PDT 24
Peak memory 205228 kb
Host smart-2dd15b87-1783-4f6a-bac4-7e005b3aa6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130908433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3130908433
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3724297756
Short name T708
Test name
Test status
Simulation time 46822108 ps
CPU time 2.13 seconds
Started Jul 30 05:15:04 PM PDT 24
Finished Jul 30 05:15:06 PM PDT 24
Peak memory 224856 kb
Host smart-76a116c3-44ec-4ee2-becd-128aa93785ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724297756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3724297756
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1783316305
Short name T295
Test name
Test status
Simulation time 16079779 ps
CPU time 0.78 seconds
Started Jul 30 05:14:59 PM PDT 24
Finished Jul 30 05:15:00 PM PDT 24
Peak memory 206952 kb
Host smart-1ffefbb1-8c23-4df8-b364-547bdea36127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783316305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1783316305
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.270765907
Short name T429
Test name
Test status
Simulation time 17144466 ps
CPU time 0.81 seconds
Started Jul 30 05:15:05 PM PDT 24
Finished Jul 30 05:15:06 PM PDT 24
Peak memory 216160 kb
Host smart-a1b3da4b-ebc7-4215-9bbf-079b18ec9a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270765907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.270765907
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3367100780
Short name T624
Test name
Test status
Simulation time 11425824476 ps
CPU time 139.77 seconds
Started Jul 30 05:15:02 PM PDT 24
Finished Jul 30 05:17:22 PM PDT 24
Peak memory 250140 kb
Host smart-db5ab66a-3424-4332-8d9f-e19747e6d8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367100780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3367100780
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.103289848
Short name T411
Test name
Test status
Simulation time 13282127960 ps
CPU time 137.16 seconds
Started Jul 30 05:15:04 PM PDT 24
Finished Jul 30 05:17:21 PM PDT 24
Peak memory 249556 kb
Host smart-9c1564da-4d69-4e10-8e46-34519a9e3d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103289848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.103289848
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2365999043
Short name T965
Test name
Test status
Simulation time 8021745093 ps
CPU time 25.99 seconds
Started Jul 30 05:15:02 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 233192 kb
Host smart-1b4771ab-14ed-471c-aff1-01b671a8e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365999043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2365999043
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2399885930
Short name T76
Test name
Test status
Simulation time 4555661048 ps
CPU time 65.39 seconds
Started Jul 30 05:15:04 PM PDT 24
Finished Jul 30 05:16:10 PM PDT 24
Peak memory 265356 kb
Host smart-72e9101c-b1a6-4c7c-9204-e1e4c1968574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399885930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2399885930
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.786484458
Short name T808
Test name
Test status
Simulation time 123293546 ps
CPU time 2.66 seconds
Started Jul 30 05:14:56 PM PDT 24
Finished Jul 30 05:14:59 PM PDT 24
Peak memory 232796 kb
Host smart-29a876db-b84b-4c8b-995e-9bf174cfc3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786484458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.786484458
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1232474098
Short name T299
Test name
Test status
Simulation time 10063056550 ps
CPU time 73.64 seconds
Started Jul 30 05:15:02 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 233100 kb
Host smart-4f512899-ad83-4271-ada3-dd66a1505c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232474098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1232474098
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3827962267
Short name T983
Test name
Test status
Simulation time 6673611151 ps
CPU time 5.36 seconds
Started Jul 30 05:14:57 PM PDT 24
Finished Jul 30 05:15:02 PM PDT 24
Peak memory 224868 kb
Host smart-d84d704c-4fbd-43d9-b6a8-775e0f5a65af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827962267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3827962267
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2296246783
Short name T739
Test name
Test status
Simulation time 392597049 ps
CPU time 7.28 seconds
Started Jul 30 05:14:57 PM PDT 24
Finished Jul 30 05:15:04 PM PDT 24
Peak memory 233204 kb
Host smart-61638de1-24e4-46a1-b076-1b27e4e94958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296246783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2296246783
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1649912670
Short name T138
Test name
Test status
Simulation time 931372776 ps
CPU time 6.23 seconds
Started Jul 30 05:15:03 PM PDT 24
Finished Jul 30 05:15:10 PM PDT 24
Peak memory 220780 kb
Host smart-1f7d4438-6794-40e8-b103-9b65ea08c244
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649912670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1649912670
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1922248304
Short name T904
Test name
Test status
Simulation time 12654695971 ps
CPU time 30.75 seconds
Started Jul 30 05:14:57 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 216752 kb
Host smart-652f8548-81e1-451e-9b57-c3e600d2c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922248304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1922248304
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2814893818
Short name T745
Test name
Test status
Simulation time 2545370673 ps
CPU time 7.57 seconds
Started Jul 30 05:14:56 PM PDT 24
Finished Jul 30 05:15:04 PM PDT 24
Peak memory 216640 kb
Host smart-b72fa7a4-491a-408b-8c5b-8c94157fde79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814893818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2814893818
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2197625644
Short name T285
Test name
Test status
Simulation time 145643697 ps
CPU time 1.32 seconds
Started Jul 30 05:14:55 PM PDT 24
Finished Jul 30 05:14:57 PM PDT 24
Peak memory 216724 kb
Host smart-79649731-0dfc-4790-b235-4a1cff085906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197625644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2197625644
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.387028760
Short name T443
Test name
Test status
Simulation time 450264915 ps
CPU time 0.87 seconds
Started Jul 30 05:14:56 PM PDT 24
Finished Jul 30 05:14:57 PM PDT 24
Peak memory 207292 kb
Host smart-59a7df48-ffd9-4d9a-92af-8c6247841755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387028760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.387028760
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1182558093
Short name T177
Test name
Test status
Simulation time 2410383546 ps
CPU time 7.65 seconds
Started Jul 30 05:15:05 PM PDT 24
Finished Jul 30 05:15:13 PM PDT 24
Peak memory 225180 kb
Host smart-34a9b35a-a823-4b7f-ac0d-13ddd16e3072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182558093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1182558093
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2802933444
Short name T374
Test name
Test status
Simulation time 40543255 ps
CPU time 0.73 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:09 PM PDT 24
Peak memory 205744 kb
Host smart-fe579492-b092-4276-b278-054e21e9c882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802933444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2802933444
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3875920927
Short name T59
Test name
Test status
Simulation time 106301859 ps
CPU time 2.44 seconds
Started Jul 30 05:15:05 PM PDT 24
Finished Jul 30 05:15:07 PM PDT 24
Peak memory 224584 kb
Host smart-18b56b1b-8fc9-4e83-bcec-79b9cfbfc94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875920927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3875920927
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4128779933
Short name T738
Test name
Test status
Simulation time 13481227 ps
CPU time 0.82 seconds
Started Jul 30 05:15:03 PM PDT 24
Finished Jul 30 05:15:04 PM PDT 24
Peak memory 207004 kb
Host smart-ce6bb721-8e9e-498e-8b17-bf6b8b0d0dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128779933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4128779933
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.673771297
Short name T65
Test name
Test status
Simulation time 2764750256 ps
CPU time 17.51 seconds
Started Jul 30 05:15:06 PM PDT 24
Finished Jul 30 05:15:23 PM PDT 24
Peak memory 249572 kb
Host smart-7122acbc-dac5-4d70-8689-d61867451917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673771297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.673771297
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2113138868
Short name T892
Test name
Test status
Simulation time 4630138383 ps
CPU time 59.28 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:16:07 PM PDT 24
Peak memory 256796 kb
Host smart-c6b2e5a0-f90d-408a-831e-c1e7045d2cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113138868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2113138868
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3945151990
Short name T271
Test name
Test status
Simulation time 5509419432 ps
CPU time 18.61 seconds
Started Jul 30 05:15:05 PM PDT 24
Finished Jul 30 05:15:23 PM PDT 24
Peak memory 225024 kb
Host smart-d4d6c18b-9d6e-4445-a19d-d03fa542fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945151990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3945151990
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1627473442
Short name T658
Test name
Test status
Simulation time 10701759985 ps
CPU time 107.38 seconds
Started Jul 30 05:15:04 PM PDT 24
Finished Jul 30 05:16:51 PM PDT 24
Peak memory 255336 kb
Host smart-78edfc75-56d1-494e-a182-f06d9755bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627473442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1627473442
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2472938839
Short name T212
Test name
Test status
Simulation time 5838877872 ps
CPU time 29.64 seconds
Started Jul 30 05:15:02 PM PDT 24
Finished Jul 30 05:15:31 PM PDT 24
Peak memory 225048 kb
Host smart-42796064-73da-4556-a1de-54b4caca95cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472938839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2472938839
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3971240169
Short name T835
Test name
Test status
Simulation time 11048245070 ps
CPU time 49.15 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:15:58 PM PDT 24
Peak memory 241252 kb
Host smart-5d23b30e-1a4d-4da6-846d-fee705a601d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971240169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3971240169
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.566803975
Short name T466
Test name
Test status
Simulation time 34239292 ps
CPU time 2.26 seconds
Started Jul 30 05:15:02 PM PDT 24
Finished Jul 30 05:15:04 PM PDT 24
Peak memory 224788 kb
Host smart-6cdf3e26-d786-4684-ac34-b94164c58f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566803975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.566803975
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2163940720
Short name T994
Test name
Test status
Simulation time 3112762328 ps
CPU time 14.33 seconds
Started Jul 30 05:15:01 PM PDT 24
Finished Jul 30 05:15:15 PM PDT 24
Peak memory 237104 kb
Host smart-642c3296-4556-449f-ac77-ab6e10c0c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163940720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2163940720
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3174348006
Short name T676
Test name
Test status
Simulation time 1479224118 ps
CPU time 9.78 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:15:19 PM PDT 24
Peak memory 223536 kb
Host smart-c5063e50-df3b-43e5-bfa5-3d62c600a22e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3174348006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3174348006
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2870443006
Short name T521
Test name
Test status
Simulation time 9522532658 ps
CPU time 89.24 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:16:38 PM PDT 24
Peak memory 249520 kb
Host smart-e45d95d5-1dc4-4f80-8875-c96dba4d38b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870443006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2870443006
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2750187870
Short name T896
Test name
Test status
Simulation time 2399903802 ps
CPU time 9.58 seconds
Started Jul 30 05:15:03 PM PDT 24
Finished Jul 30 05:15:13 PM PDT 24
Peak memory 220172 kb
Host smart-a1621445-b05e-40b5-8c41-09235b73ee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750187870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2750187870
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1776142055
Short name T784
Test name
Test status
Simulation time 25549082916 ps
CPU time 18.75 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:27 PM PDT 24
Peak memory 216788 kb
Host smart-312a8084-c969-4b9e-801f-c5fe438aea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776142055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1776142055
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1637518282
Short name T332
Test name
Test status
Simulation time 198463578 ps
CPU time 1.21 seconds
Started Jul 30 05:15:03 PM PDT 24
Finished Jul 30 05:15:04 PM PDT 24
Peak memory 208436 kb
Host smart-16149071-54ac-44ab-9b40-7b0f110046c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637518282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1637518282
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.233556164
Short name T948
Test name
Test status
Simulation time 45274742 ps
CPU time 0.75 seconds
Started Jul 30 05:15:04 PM PDT 24
Finished Jul 30 05:15:05 PM PDT 24
Peak memory 206392 kb
Host smart-4b2fc4ed-7204-4a7d-b3b4-0f6e532993ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233556164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.233556164
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1353426497
Short name T826
Test name
Test status
Simulation time 14018286316 ps
CPU time 21.69 seconds
Started Jul 30 05:15:03 PM PDT 24
Finished Jul 30 05:15:25 PM PDT 24
Peak memory 233204 kb
Host smart-71040e66-78f5-4934-8ae7-a1539c222c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353426497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1353426497
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1793751219
Short name T381
Test name
Test status
Simulation time 42994046 ps
CPU time 0.69 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:15:10 PM PDT 24
Peak memory 205748 kb
Host smart-a4888a6f-5eeb-49dd-af12-4c05020af3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793751219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1793751219
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1512548868
Short name T534
Test name
Test status
Simulation time 126814720 ps
CPU time 2.9 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:11 PM PDT 24
Peak memory 233068 kb
Host smart-eeba05b4-5a08-47ec-a0d7-38909c40254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512548868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1512548868
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1027513783
Short name T294
Test name
Test status
Simulation time 55685295 ps
CPU time 0.77 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:09 PM PDT 24
Peak memory 205936 kb
Host smart-7a6104ea-e7cd-468b-a9fb-ed3271e981dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027513783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1027513783
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3859448511
Short name T870
Test name
Test status
Simulation time 163365099273 ps
CPU time 272.33 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:19:41 PM PDT 24
Peak memory 257380 kb
Host smart-886ad5a7-939a-45da-846f-a8e3ae40c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859448511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3859448511
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.773342702
Short name T583
Test name
Test status
Simulation time 12741594936 ps
CPU time 100.81 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 257600 kb
Host smart-1a89ffaf-fe2b-47c2-81c0-a1c9f0615356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773342702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.773342702
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3020954929
Short name T600
Test name
Test status
Simulation time 65690390088 ps
CPU time 49.18 seconds
Started Jul 30 05:15:06 PM PDT 24
Finished Jul 30 05:15:55 PM PDT 24
Peak memory 220016 kb
Host smart-11a5f05a-45ad-4743-a747-51a4160ca2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020954929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3020954929
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1487675182
Short name T993
Test name
Test status
Simulation time 144481489 ps
CPU time 2.78 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:10 PM PDT 24
Peak memory 233140 kb
Host smart-e7f77a8d-5f9e-4d7a-8bb7-3c1ea671a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487675182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1487675182
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2631650856
Short name T1002
Test name
Test status
Simulation time 23756626182 ps
CPU time 108.16 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:16:55 PM PDT 24
Peak memory 249696 kb
Host smart-ca34e2ab-075c-4ef5-8601-ed4aa106a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631650856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2631650856
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.368113508
Short name T929
Test name
Test status
Simulation time 140481613 ps
CPU time 3.35 seconds
Started Jul 30 05:15:06 PM PDT 24
Finished Jul 30 05:15:10 PM PDT 24
Peak memory 224928 kb
Host smart-042a1700-321f-4254-bea0-ff09372effcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368113508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.368113508
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3396259796
Short name T695
Test name
Test status
Simulation time 512960850 ps
CPU time 8.47 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:15:16 PM PDT 24
Peak memory 233108 kb
Host smart-edae65e4-c435-4e39-98dc-925137b22015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396259796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3396259796
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1733357033
Short name T401
Test name
Test status
Simulation time 15395720474 ps
CPU time 24.31 seconds
Started Jul 30 05:15:06 PM PDT 24
Finished Jul 30 05:15:30 PM PDT 24
Peak memory 233180 kb
Host smart-36463331-ef66-4d60-8a08-2e323051c5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733357033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1733357033
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.992652154
Short name T646
Test name
Test status
Simulation time 1346118637 ps
CPU time 9.45 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:15:17 PM PDT 24
Peak memory 233296 kb
Host smart-22dda339-0df7-4dd9-a94c-933174822177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992652154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.992652154
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3191770471
Short name T687
Test name
Test status
Simulation time 215771191 ps
CPU time 4.42 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:15:12 PM PDT 24
Peak memory 222892 kb
Host smart-2331acc6-5325-457c-95ff-094f6f12fc00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3191770471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3191770471
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2180758284
Short name T547
Test name
Test status
Simulation time 8618434846 ps
CPU time 24.17 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:32 PM PDT 24
Peak memory 219020 kb
Host smart-c690cd36-7bc8-4a13-8f64-a65879230e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180758284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2180758284
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1005168045
Short name T481
Test name
Test status
Simulation time 1186572031 ps
CPU time 7.41 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:15 PM PDT 24
Peak memory 216728 kb
Host smart-631d8391-449c-472f-af0c-3f5953f2c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005168045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1005168045
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1086201257
Short name T558
Test name
Test status
Simulation time 243667697 ps
CPU time 1.53 seconds
Started Jul 30 05:15:10 PM PDT 24
Finished Jul 30 05:15:11 PM PDT 24
Peak memory 208464 kb
Host smart-9859068a-050e-495b-bf5f-61504f6bda17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086201257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1086201257
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2408278864
Short name T775
Test name
Test status
Simulation time 61932558 ps
CPU time 0.94 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:15:08 PM PDT 24
Peak memory 206352 kb
Host smart-8eacbea2-79a3-4786-87d5-61f814cad96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408278864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2408278864
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3973725373
Short name T590
Test name
Test status
Simulation time 665351390 ps
CPU time 4.09 seconds
Started Jul 30 05:15:08 PM PDT 24
Finished Jul 30 05:15:12 PM PDT 24
Peak memory 233108 kb
Host smart-e54ee961-70a9-441b-92e1-eca6a6db434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973725373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3973725373
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.105101932
Short name T476
Test name
Test status
Simulation time 11039261 ps
CPU time 0.76 seconds
Started Jul 30 05:15:14 PM PDT 24
Finished Jul 30 05:15:15 PM PDT 24
Peak memory 205256 kb
Host smart-e357408c-93cb-43c5-8752-f6af904d2f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105101932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.105101932
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1200179577
Short name T823
Test name
Test status
Simulation time 4171245840 ps
CPU time 10.48 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:24 PM PDT 24
Peak memory 233112 kb
Host smart-7a1efd71-c802-4225-8c17-5eb4f7389c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200179577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1200179577
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1034306930
Short name T348
Test name
Test status
Simulation time 38722531 ps
CPU time 0.73 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:15:10 PM PDT 24
Peak memory 206924 kb
Host smart-134f5f99-3dd9-4c19-a76e-74c76cc5f00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034306930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1034306930
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3311439946
Short name T876
Test name
Test status
Simulation time 22507027 ps
CPU time 0.76 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:14 PM PDT 24
Peak memory 216156 kb
Host smart-758924ae-96ef-4f55-a6cd-940f795ef4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311439946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3311439946
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2594970549
Short name T566
Test name
Test status
Simulation time 66581935026 ps
CPU time 54.82 seconds
Started Jul 30 05:15:14 PM PDT 24
Finished Jul 30 05:16:09 PM PDT 24
Peak memory 241404 kb
Host smart-4eeb0f14-be85-45f1-8323-910c5b77b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594970549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2594970549
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2482119768
Short name T266
Test name
Test status
Simulation time 23240297166 ps
CPU time 87.78 seconds
Started Jul 30 05:15:17 PM PDT 24
Finished Jul 30 05:16:44 PM PDT 24
Peak memory 254804 kb
Host smart-886714a2-03e7-464a-900e-bee22cdf762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482119768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2482119768
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4209147027
Short name T569
Test name
Test status
Simulation time 3653471387 ps
CPU time 55.9 seconds
Started Jul 30 05:15:16 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 240116 kb
Host smart-59863297-f1b5-4a4e-8026-4f0c13e835c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209147027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4209147027
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2559034844
Short name T596
Test name
Test status
Simulation time 52485629223 ps
CPU time 409.94 seconds
Started Jul 30 05:15:14 PM PDT 24
Finished Jul 30 05:22:04 PM PDT 24
Peak memory 256616 kb
Host smart-ee1a621a-1409-4621-8942-af5557b0cc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559034844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2559034844
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3834675829
Short name T629
Test name
Test status
Simulation time 402073189 ps
CPU time 4.63 seconds
Started Jul 30 05:15:12 PM PDT 24
Finished Jul 30 05:15:17 PM PDT 24
Peak memory 233144 kb
Host smart-c9294f7d-2caf-42be-b090-c5f37429736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834675829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3834675829
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3910617117
Short name T176
Test name
Test status
Simulation time 3752772206 ps
CPU time 39.05 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:15:48 PM PDT 24
Peak memory 240120 kb
Host smart-a218ad24-5691-4a8d-bd7d-600f262342a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910617117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3910617117
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1595894895
Short name T732
Test name
Test status
Simulation time 783600372 ps
CPU time 6.98 seconds
Started Jul 30 05:15:11 PM PDT 24
Finished Jul 30 05:15:18 PM PDT 24
Peak memory 240676 kb
Host smart-f0221eae-bd17-4883-9ec4-b30b86499a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595894895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1595894895
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3904887604
Short name T377
Test name
Test status
Simulation time 7293902513 ps
CPU time 7.53 seconds
Started Jul 30 05:15:10 PM PDT 24
Finished Jul 30 05:15:18 PM PDT 24
Peak memory 225000 kb
Host smart-d6ad19b2-b028-4796-b146-377d5558a9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904887604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3904887604
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3330073337
Short name T136
Test name
Test status
Simulation time 420303255 ps
CPU time 3.77 seconds
Started Jul 30 05:15:25 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 220724 kb
Host smart-282bf7af-af1a-4cae-a4a5-1cefa9162e24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3330073337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3330073337
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3773805624
Short name T46
Test name
Test status
Simulation time 48162255040 ps
CPU time 475.17 seconds
Started Jul 30 05:15:15 PM PDT 24
Finished Jul 30 05:23:10 PM PDT 24
Peak memory 273316 kb
Host smart-70a8a731-b74e-4533-9641-5b8e571c5df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773805624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3773805624
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3998869841
Short name T282
Test name
Test status
Simulation time 645100557 ps
CPU time 3.44 seconds
Started Jul 30 05:15:10 PM PDT 24
Finished Jul 30 05:15:14 PM PDT 24
Peak memory 216936 kb
Host smart-2de80425-18a4-4777-9c02-a1ccb9442826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998869841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3998869841
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1569978960
Short name T465
Test name
Test status
Simulation time 26912263232 ps
CPU time 10.62 seconds
Started Jul 30 05:15:10 PM PDT 24
Finished Jul 30 05:15:21 PM PDT 24
Peak memory 216724 kb
Host smart-e15786c9-cf37-49d1-a557-662624dade99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569978960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1569978960
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.426862729
Short name T902
Test name
Test status
Simulation time 334279660 ps
CPU time 0.92 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:14 PM PDT 24
Peak memory 207032 kb
Host smart-5e70323a-2f2c-42a3-85c7-0fb08bf9f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426862729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.426862729
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4228343611
Short name T118
Test name
Test status
Simulation time 41659431 ps
CPU time 0.72 seconds
Started Jul 30 05:15:07 PM PDT 24
Finished Jul 30 05:15:08 PM PDT 24
Peak memory 206412 kb
Host smart-6d9bfafb-fe47-425b-96f7-7247809f60ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228343611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4228343611
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3226402621
Short name T232
Test name
Test status
Simulation time 1968984716 ps
CPU time 15.78 seconds
Started Jul 30 05:15:09 PM PDT 24
Finished Jul 30 05:15:25 PM PDT 24
Peak memory 241144 kb
Host smart-464e7ca0-684f-4fd3-a1d5-9d928a6ec00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226402621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3226402621
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2735844521
Short name T778
Test name
Test status
Simulation time 43628288 ps
CPU time 0.79 seconds
Started Jul 30 05:15:19 PM PDT 24
Finished Jul 30 05:15:20 PM PDT 24
Peak memory 205288 kb
Host smart-8e0421f3-4226-46ef-8c45-d57d1935f0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735844521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2735844521
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1532708329
Short name T103
Test name
Test status
Simulation time 36539208 ps
CPU time 2.62 seconds
Started Jul 30 05:15:17 PM PDT 24
Finished Jul 30 05:15:20 PM PDT 24
Peak memory 233024 kb
Host smart-e627d7e8-714a-4861-9e5b-220db2a6fae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532708329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1532708329
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4078820123
Short name T669
Test name
Test status
Simulation time 201490894 ps
CPU time 0.78 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:13 PM PDT 24
Peak memory 206952 kb
Host smart-ddefeac8-4fb7-491d-a61b-825bebd908e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078820123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4078820123
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1333083875
Short name T713
Test name
Test status
Simulation time 28429118489 ps
CPU time 104.35 seconds
Started Jul 30 05:15:18 PM PDT 24
Finished Jul 30 05:17:02 PM PDT 24
Peak memory 249480 kb
Host smart-95401b5f-9646-4200-82e4-326463e230bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333083875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1333083875
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.533097946
Short name T472
Test name
Test status
Simulation time 30707200779 ps
CPU time 305.45 seconds
Started Jul 30 05:15:18 PM PDT 24
Finished Jul 30 05:20:23 PM PDT 24
Peak memory 257236 kb
Host smart-af72240d-bf3d-4e30-8407-c06d2da188a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533097946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.533097946
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2290869765
Short name T491
Test name
Test status
Simulation time 29087373845 ps
CPU time 72.68 seconds
Started Jul 30 05:15:19 PM PDT 24
Finished Jul 30 05:16:31 PM PDT 24
Peak memory 249616 kb
Host smart-b9a7bc8b-8aca-48ec-97dc-ce9542e67028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290869765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2290869765
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2385906109
Short name T630
Test name
Test status
Simulation time 941581472 ps
CPU time 18.45 seconds
Started Jul 30 05:15:19 PM PDT 24
Finished Jul 30 05:15:37 PM PDT 24
Peak memory 233116 kb
Host smart-13b66f65-1196-4b30-a584-df2ab9670a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385906109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2385906109
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.139034594
Short name T102
Test name
Test status
Simulation time 39721254250 ps
CPU time 87.13 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:16:50 PM PDT 24
Peak memory 238064 kb
Host smart-66548270-3f6e-46ca-97ed-261ff153d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139034594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.139034594
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2678674321
Short name T4
Test name
Test status
Simulation time 913609639 ps
CPU time 5.98 seconds
Started Jul 30 05:15:19 PM PDT 24
Finished Jul 30 05:15:25 PM PDT 24
Peak memory 233100 kb
Host smart-4d8ab843-561f-44f3-bc79-3c8f6839a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678674321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2678674321
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1281108893
Short name T798
Test name
Test status
Simulation time 757923041 ps
CPU time 6.3 seconds
Started Jul 30 05:15:22 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 241084 kb
Host smart-9e1df395-525c-4902-858c-62bf2a8fc114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281108893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1281108893
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1957203169
Short name T356
Test name
Test status
Simulation time 220427683 ps
CPU time 5.56 seconds
Started Jul 30 05:15:14 PM PDT 24
Finished Jul 30 05:15:20 PM PDT 24
Peak memory 233084 kb
Host smart-92e04dfa-d4e8-429c-96e8-73bba711f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957203169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1957203169
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3295227895
Short name T489
Test name
Test status
Simulation time 2114302762 ps
CPU time 7.28 seconds
Started Jul 30 05:15:14 PM PDT 24
Finished Jul 30 05:15:21 PM PDT 24
Peak memory 224856 kb
Host smart-0b427c33-318a-4917-9ba2-b79d7ea3b997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295227895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3295227895
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2846482482
Short name T81
Test name
Test status
Simulation time 361662098 ps
CPU time 3.89 seconds
Started Jul 30 05:15:18 PM PDT 24
Finished Jul 30 05:15:22 PM PDT 24
Peak memory 222940 kb
Host smart-a08e64a0-25f6-434a-8e02-fbb83d5eb22a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2846482482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2846482482
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.155402052
Short name T526
Test name
Test status
Simulation time 2026628851 ps
CPU time 27.1 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:40 PM PDT 24
Peak memory 220296 kb
Host smart-84cca362-7a67-4e0b-a0fc-12eca768f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155402052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.155402052
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3945061414
Short name T437
Test name
Test status
Simulation time 977872847 ps
CPU time 5.93 seconds
Started Jul 30 05:15:15 PM PDT 24
Finished Jul 30 05:15:21 PM PDT 24
Peak memory 216680 kb
Host smart-ccf52907-69cb-48d1-b3c5-406f25757694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945061414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3945061414
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2876818574
Short name T557
Test name
Test status
Simulation time 15415945 ps
CPU time 0.69 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:14 PM PDT 24
Peak memory 206008 kb
Host smart-2e2a37cf-5ea5-46e0-96bf-47a2ff46d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876818574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2876818574
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3568048446
Short name T653
Test name
Test status
Simulation time 108491821 ps
CPU time 0.79 seconds
Started Jul 30 05:15:13 PM PDT 24
Finished Jul 30 05:15:14 PM PDT 24
Peak memory 206324 kb
Host smart-8748cdc2-7d10-4047-a08c-a8af219f7871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568048446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3568048446
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1550530483
Short name T120
Test name
Test status
Simulation time 12510520873 ps
CPU time 16.18 seconds
Started Jul 30 05:15:19 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 249608 kb
Host smart-d57bb71e-6492-4e4e-9832-ea8286f75108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550530483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1550530483
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2696863181
Short name T803
Test name
Test status
Simulation time 13809602 ps
CPU time 0.74 seconds
Started Jul 30 05:15:22 PM PDT 24
Finished Jul 30 05:15:23 PM PDT 24
Peak memory 205232 kb
Host smart-0eba344f-23c5-470d-b925-bffb8b019c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696863181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2696863181
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3802752867
Short name T225
Test name
Test status
Simulation time 3727319557 ps
CPU time 16.09 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 233124 kb
Host smart-12e49902-cdfe-4f66-b226-c18eef2fc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802752867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3802752867
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2546282677
Short name T774
Test name
Test status
Simulation time 77747416 ps
CPU time 0.8 seconds
Started Jul 30 05:15:22 PM PDT 24
Finished Jul 30 05:15:23 PM PDT 24
Peak memory 207328 kb
Host smart-0ecda158-4018-489a-8191-0f75b9ea4748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546282677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2546282677
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.326262501
Short name T234
Test name
Test status
Simulation time 569663511 ps
CPU time 14.32 seconds
Started Jul 30 05:15:25 PM PDT 24
Finished Jul 30 05:15:40 PM PDT 24
Peak memory 241352 kb
Host smart-dca88ff4-2ada-4ccd-819a-178c9a29b833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326262501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.326262501
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1418191570
Short name T485
Test name
Test status
Simulation time 16394362633 ps
CPU time 140.32 seconds
Started Jul 30 05:15:21 PM PDT 24
Finished Jul 30 05:17:42 PM PDT 24
Peak memory 249648 kb
Host smart-44779d4a-71f8-4193-a949-ed53bc013a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418191570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1418191570
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1590088765
Short name T278
Test name
Test status
Simulation time 4218142379 ps
CPU time 12.89 seconds
Started Jul 30 05:15:24 PM PDT 24
Finished Jul 30 05:15:37 PM PDT 24
Peak memory 224800 kb
Host smart-606752cd-f2b8-4573-922f-a42afd39d66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590088765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1590088765
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2232770101
Short name T851
Test name
Test status
Simulation time 1830569273 ps
CPU time 28.1 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:15:51 PM PDT 24
Peak memory 249528 kb
Host smart-3a15813f-f961-4d03-8f94-610432a94d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232770101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2232770101
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.510031238
Short name T793
Test name
Test status
Simulation time 4796065898 ps
CPU time 85.35 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 264172 kb
Host smart-d431e596-d521-4b51-ae1e-2995a4104f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510031238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.510031238
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.125568066
Short name T847
Test name
Test status
Simulation time 94158394 ps
CPU time 3.52 seconds
Started Jul 30 05:15:22 PM PDT 24
Finished Jul 30 05:15:26 PM PDT 24
Peak memory 233112 kb
Host smart-c971e424-11d8-43ec-a222-5b7652edb8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125568066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.125568066
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3756115113
Short name T218
Test name
Test status
Simulation time 850348918 ps
CPU time 6.47 seconds
Started Jul 30 05:15:24 PM PDT 24
Finished Jul 30 05:15:31 PM PDT 24
Peak memory 233132 kb
Host smart-121cc9bb-1865-43c6-9368-699edc1041ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756115113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3756115113
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1584210026
Short name T2
Test name
Test status
Simulation time 4958544402 ps
CPU time 11.3 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:15:34 PM PDT 24
Peak memory 237416 kb
Host smart-93f6200b-6853-4c09-8716-7b52d4e38f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584210026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1584210026
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1732776666
Short name T220
Test name
Test status
Simulation time 10633204140 ps
CPU time 16.74 seconds
Started Jul 30 05:15:25 PM PDT 24
Finished Jul 30 05:15:42 PM PDT 24
Peak memory 233188 kb
Host smart-ca14c8c7-2a23-48e7-8615-83050233b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732776666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1732776666
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.113130568
Short name T418
Test name
Test status
Simulation time 655150956 ps
CPU time 5.75 seconds
Started Jul 30 05:15:24 PM PDT 24
Finished Jul 30 05:15:30 PM PDT 24
Peak memory 223584 kb
Host smart-9c9caf94-214c-41a5-9019-e8142be35b11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113130568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.113130568
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.781896399
Short name T735
Test name
Test status
Simulation time 55329541 ps
CPU time 0.74 seconds
Started Jul 30 05:15:20 PM PDT 24
Finished Jul 30 05:15:21 PM PDT 24
Peak memory 206108 kb
Host smart-08b6958e-51b8-4832-85b0-d9d75cd74a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781896399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.781896399
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3516856684
Short name T650
Test name
Test status
Simulation time 12875570129 ps
CPU time 3.93 seconds
Started Jul 30 05:15:17 PM PDT 24
Finished Jul 30 05:15:21 PM PDT 24
Peak memory 216824 kb
Host smart-33ffa597-a13f-49f6-a7c0-845bb9d22864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516856684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3516856684
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3068338245
Short name T951
Test name
Test status
Simulation time 83775835 ps
CPU time 0.89 seconds
Started Jul 30 05:15:21 PM PDT 24
Finished Jul 30 05:15:22 PM PDT 24
Peak memory 208276 kb
Host smart-76f20564-40c4-4f88-af26-69dac74bb7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068338245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3068338245
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3175240824
Short name T880
Test name
Test status
Simulation time 30465278 ps
CPU time 0.73 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:15:24 PM PDT 24
Peak memory 206360 kb
Host smart-69cab127-e0dc-46e4-9f1f-c9ed59cbbdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175240824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3175240824
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.383907851
Short name T845
Test name
Test status
Simulation time 862587732 ps
CPU time 4.83 seconds
Started Jul 30 05:15:25 PM PDT 24
Finished Jul 30 05:15:29 PM PDT 24
Peak memory 224860 kb
Host smart-e19aa2f5-1521-4186-8a1c-7ab47e5cd5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383907851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.383907851
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4232062670
Short name T715
Test name
Test status
Simulation time 39613761 ps
CPU time 0.73 seconds
Started Jul 30 05:12:02 PM PDT 24
Finished Jul 30 05:12:03 PM PDT 24
Peak memory 205252 kb
Host smart-5c11c611-04ff-4400-a545-00d387d0cdee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232062670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
232062670
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.109531217
Short name T925
Test name
Test status
Simulation time 58479542 ps
CPU time 2.6 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:04 PM PDT 24
Peak memory 233096 kb
Host smart-4582b875-d026-47d8-947f-ab11d78e6730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109531217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.109531217
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1468323255
Short name T962
Test name
Test status
Simulation time 56738629 ps
CPU time 0.77 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:02 PM PDT 24
Peak memory 206252 kb
Host smart-1463c1ef-37b1-48fc-84e5-5a65c913ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468323255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1468323255
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2805742832
Short name T688
Test name
Test status
Simulation time 35157204863 ps
CPU time 62.56 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:13:10 PM PDT 24
Peak memory 249764 kb
Host smart-89bfce77-61f8-4284-88e9-a1d5558df855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805742832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2805742832
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3395826627
Short name T254
Test name
Test status
Simulation time 710256054809 ps
CPU time 407.43 seconds
Started Jul 30 05:12:04 PM PDT 24
Finished Jul 30 05:18:52 PM PDT 24
Peak memory 273176 kb
Host smart-7be685b6-d2dc-4ed2-bc0e-ec78f1c75b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395826627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3395826627
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3062613295
Short name T44
Test name
Test status
Simulation time 5004991960 ps
CPU time 103.88 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:13:47 PM PDT 24
Peak memory 265284 kb
Host smart-8b85638e-4268-4627-86c8-09440607cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062613295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3062613295
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1381956797
Short name T303
Test name
Test status
Simulation time 4262111192 ps
CPU time 13.43 seconds
Started Jul 30 05:12:02 PM PDT 24
Finished Jul 30 05:12:16 PM PDT 24
Peak memory 233176 kb
Host smart-9b863d0a-504d-4051-9cee-0cf625c9ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381956797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1381956797
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.771589156
Short name T216
Test name
Test status
Simulation time 808272165628 ps
CPU time 375.63 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:18:23 PM PDT 24
Peak memory 265940 kb
Host smart-0c9eafbe-9765-435b-a4bb-812a1da8fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771589156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
771589156
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3422720800
Short name T452
Test name
Test status
Simulation time 2478917201 ps
CPU time 24.68 seconds
Started Jul 30 05:12:00 PM PDT 24
Finished Jul 30 05:12:25 PM PDT 24
Peak memory 220224 kb
Host smart-d0168b4f-07f2-4dc5-b753-79c8d7932d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422720800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3422720800
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3523184964
Short name T384
Test name
Test status
Simulation time 4803410020 ps
CPU time 36.53 seconds
Started Jul 30 05:12:00 PM PDT 24
Finished Jul 30 05:12:36 PM PDT 24
Peak memory 233228 kb
Host smart-836987fe-25fa-44c6-bda4-74649e8f22ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523184964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3523184964
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2729757467
Short name T346
Test name
Test status
Simulation time 465723497 ps
CPU time 7.96 seconds
Started Jul 30 05:11:58 PM PDT 24
Finished Jul 30 05:12:06 PM PDT 24
Peak memory 233068 kb
Host smart-4793fc0e-f96c-4ec9-8144-a48f16dcfce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729757467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2729757467
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.81998275
Short name T122
Test name
Test status
Simulation time 30608859609 ps
CPU time 15.16 seconds
Started Jul 30 05:12:02 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 233164 kb
Host smart-75dcfb2c-e318-45a8-ab34-cf4dc2aa2053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81998275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.81998275
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.22049621
Short name T824
Test name
Test status
Simulation time 416860748 ps
CPU time 4.21 seconds
Started Jul 30 05:12:06 PM PDT 24
Finished Jul 30 05:12:10 PM PDT 24
Peak memory 223560 kb
Host smart-7b7a0198-09a2-41e1-9ea8-499e15c114e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=22049621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.22049621
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.154555603
Short name T754
Test name
Test status
Simulation time 1241356052 ps
CPU time 17.7 seconds
Started Jul 30 05:11:58 PM PDT 24
Finished Jul 30 05:12:16 PM PDT 24
Peak memory 220752 kb
Host smart-877310d5-09ef-4fdf-be38-821a03de4a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154555603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.154555603
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2723745427
Short name T482
Test name
Test status
Simulation time 1721768536 ps
CPU time 3.21 seconds
Started Jul 30 05:12:00 PM PDT 24
Finished Jul 30 05:12:03 PM PDT 24
Peak memory 216588 kb
Host smart-c6b2acd6-219a-4af2-94ef-2e0b9c54ea24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723745427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2723745427
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3622070545
Short name T568
Test name
Test status
Simulation time 259806591 ps
CPU time 4.97 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:06 PM PDT 24
Peak memory 216636 kb
Host smart-e9037244-a786-4513-b573-7749a0ea3a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622070545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3622070545
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.928381929
Short name T842
Test name
Test status
Simulation time 70148119 ps
CPU time 0.8 seconds
Started Jul 30 05:11:59 PM PDT 24
Finished Jul 30 05:12:00 PM PDT 24
Peak memory 206236 kb
Host smart-1f84f371-edba-4952-a9f6-6ed60b3b4d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928381929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.928381929
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1027688124
Short name T768
Test name
Test status
Simulation time 1833401159 ps
CPU time 7.66 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:12:10 PM PDT 24
Peak memory 233148 kb
Host smart-ffab1698-cbcb-48b1-9cf6-ac9ba65e0423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027688124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1027688124
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1725307706
Short name T696
Test name
Test status
Simulation time 87212193 ps
CPU time 0.7 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:12:08 PM PDT 24
Peak memory 205824 kb
Host smart-beb525a7-c25e-4ac5-91cd-13c66e8d7365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725307706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
725307706
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1939089367
Short name T436
Test name
Test status
Simulation time 66163481 ps
CPU time 2.7 seconds
Started Jul 30 05:12:06 PM PDT 24
Finished Jul 30 05:12:08 PM PDT 24
Peak memory 233120 kb
Host smart-4d0545d5-23c1-475a-b9e4-e5852fb18a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939089367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1939089367
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.985870086
Short name T499
Test name
Test status
Simulation time 21691386 ps
CPU time 0.83 seconds
Started Jul 30 05:12:04 PM PDT 24
Finished Jul 30 05:12:05 PM PDT 24
Peak memory 207308 kb
Host smart-28634820-d62d-464c-877b-2368e6f53966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985870086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.985870086
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1725907340
Short name T957
Test name
Test status
Simulation time 14099230048 ps
CPU time 80.4 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:13:26 PM PDT 24
Peak memory 262560 kb
Host smart-01ad757f-a395-44d3-8a0d-b8f0d7b7eee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725907340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1725907340
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3198735261
Short name T575
Test name
Test status
Simulation time 16727464117 ps
CPU time 129.61 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:14:15 PM PDT 24
Peak memory 270080 kb
Host smart-be8078d2-c8eb-43b2-b708-3760d981c0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198735261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3198735261
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2359819723
Short name T419
Test name
Test status
Simulation time 14437019936 ps
CPU time 113.27 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:13:56 PM PDT 24
Peak memory 263904 kb
Host smart-4ab6fa16-2c66-44f4-979f-7a1ed3928cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359819723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2359819723
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2759984535
Short name T510
Test name
Test status
Simulation time 833305837 ps
CPU time 4.57 seconds
Started Jul 30 05:12:04 PM PDT 24
Finished Jul 30 05:12:09 PM PDT 24
Peak memory 224844 kb
Host smart-80584fef-bfce-4a0d-aebf-e47b502faf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759984535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2759984535
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2433163390
Short name T790
Test name
Test status
Simulation time 16119222023 ps
CPU time 97.36 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:13:44 PM PDT 24
Peak memory 237696 kb
Host smart-b166372d-7241-4d64-b9b6-625d6bb66bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433163390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2433163390
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1091688399
Short name T907
Test name
Test status
Simulation time 173116714 ps
CPU time 3.9 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:09 PM PDT 24
Peak memory 224916 kb
Host smart-bb84c06e-edc5-499f-99c5-8d6b9de12380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091688399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1091688399
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2127811615
Short name T352
Test name
Test status
Simulation time 4243178350 ps
CPU time 20.25 seconds
Started Jul 30 05:12:04 PM PDT 24
Finished Jul 30 05:12:24 PM PDT 24
Peak memory 240736 kb
Host smart-7575e028-2642-4c38-bf36-8168dd4b0602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127811615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2127811615
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3718732587
Short name T448
Test name
Test status
Simulation time 718434136 ps
CPU time 3.62 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:09 PM PDT 24
Peak memory 233116 kb
Host smart-e916a15b-f453-4ef4-b61c-d6b6e3a31900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718732587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3718732587
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2941413800
Short name T188
Test name
Test status
Simulation time 459647933 ps
CPU time 3.83 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:12:07 PM PDT 24
Peak memory 235052 kb
Host smart-7523b19a-7142-4e4e-a9e4-eeb7a2a8d32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941413800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2941413800
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2087983691
Short name T365
Test name
Test status
Simulation time 3630762513 ps
CPU time 14.16 seconds
Started Jul 30 05:12:06 PM PDT 24
Finished Jul 30 05:12:21 PM PDT 24
Peak memory 219228 kb
Host smart-17aec0f4-f727-4809-a0c4-11c751421e0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087983691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2087983691
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1047340963
Short name T213
Test name
Test status
Simulation time 27436009616 ps
CPU time 236.34 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:16:03 PM PDT 24
Peak memory 273672 kb
Host smart-7544862a-84e4-43a8-8ad4-f436f309c9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047340963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1047340963
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2104213556
Short name T727
Test name
Test status
Simulation time 36051034282 ps
CPU time 49.85 seconds
Started Jul 30 05:12:03 PM PDT 24
Finished Jul 30 05:12:53 PM PDT 24
Peak memory 216820 kb
Host smart-e20c67f6-fef9-43c3-8a87-29e0a281794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104213556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2104213556
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1191214113
Short name T444
Test name
Test status
Simulation time 1052862936 ps
CPU time 2.95 seconds
Started Jul 30 05:12:02 PM PDT 24
Finished Jul 30 05:12:05 PM PDT 24
Peak memory 216676 kb
Host smart-11a455a8-e221-4056-b5dd-e083ba818a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191214113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1191214113
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3129160196
Short name T366
Test name
Test status
Simulation time 313848225 ps
CPU time 2.06 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:07 PM PDT 24
Peak memory 216648 kb
Host smart-0d96c7e2-df55-4813-9a39-562fff554421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129160196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3129160196
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1964274155
Short name T903
Test name
Test status
Simulation time 35447335 ps
CPU time 0.91 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:06 PM PDT 24
Peak memory 206348 kb
Host smart-3cd863e6-7f94-48f7-b267-da03061b5973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964274155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1964274155
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3566142755
Short name T667
Test name
Test status
Simulation time 66597844 ps
CPU time 2.63 seconds
Started Jul 30 05:12:01 PM PDT 24
Finished Jul 30 05:12:03 PM PDT 24
Peak memory 232812 kb
Host smart-86b9e80d-c2a5-4801-888b-08925d69d56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566142755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3566142755
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3017820239
Short name T752
Test name
Test status
Simulation time 13159948 ps
CPU time 0.74 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:12:08 PM PDT 24
Peak memory 206068 kb
Host smart-d8cfefe0-92b2-4e27-944e-d8f6c52be99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017820239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
017820239
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.359635612
Short name T894
Test name
Test status
Simulation time 5122259544 ps
CPU time 18.79 seconds
Started Jul 30 05:12:08 PM PDT 24
Finished Jul 30 05:12:27 PM PDT 24
Peak memory 224992 kb
Host smart-3e861fa1-573b-48cf-a3e0-119ee66a20ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359635612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.359635612
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3430302688
Short name T599
Test name
Test status
Simulation time 40241910 ps
CPU time 0.79 seconds
Started Jul 30 05:12:08 PM PDT 24
Finished Jul 30 05:12:09 PM PDT 24
Peak memory 207000 kb
Host smart-6838b9ad-3b5d-4fad-98d3-07126b892ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430302688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3430302688
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1863050633
Short name T717
Test name
Test status
Simulation time 21422890615 ps
CPU time 77.49 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:13:23 PM PDT 24
Peak memory 249568 kb
Host smart-4e88c2b0-6011-41c9-99eb-ce5b93ad972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863050633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1863050633
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3922617650
Short name T806
Test name
Test status
Simulation time 44097982796 ps
CPU time 237.95 seconds
Started Jul 30 05:12:09 PM PDT 24
Finished Jul 30 05:16:07 PM PDT 24
Peak memory 257820 kb
Host smart-36841d5a-7ed7-428f-ac91-96fd5cde60f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922617650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3922617650
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2492707750
Short name T766
Test name
Test status
Simulation time 11709087236 ps
CPU time 33.64 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:39 PM PDT 24
Peak memory 235452 kb
Host smart-aeca2550-c730-467c-b91b-33142f5edee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492707750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2492707750
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3337839968
Short name T125
Test name
Test status
Simulation time 699146075 ps
CPU time 8.24 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:14 PM PDT 24
Peak memory 224828 kb
Host smart-aee49887-6d91-4f31-b979-7fa6e466c46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337839968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3337839968
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2127322774
Short name T259
Test name
Test status
Simulation time 597603230864 ps
CPU time 388.41 seconds
Started Jul 30 05:12:09 PM PDT 24
Finished Jul 30 05:18:38 PM PDT 24
Peak memory 270736 kb
Host smart-e9d59d19-5da0-4d94-9171-c07f0834b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127322774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2127322774
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2213438443
Short name T421
Test name
Test status
Simulation time 2772864548 ps
CPU time 7.23 seconds
Started Jul 30 05:12:08 PM PDT 24
Finished Jul 30 05:12:16 PM PDT 24
Peak memory 224976 kb
Host smart-2b49ed81-e554-40ef-bc4f-abc122022fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213438443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2213438443
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1364227668
Short name T654
Test name
Test status
Simulation time 39360838534 ps
CPU time 94.7 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:13:42 PM PDT 24
Peak memory 233156 kb
Host smart-2edba4b9-799f-4d6c-9232-cb603ff130b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364227668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1364227668
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2348608861
Short name T946
Test name
Test status
Simulation time 7510710278 ps
CPU time 6.39 seconds
Started Jul 30 05:12:05 PM PDT 24
Finished Jul 30 05:12:12 PM PDT 24
Peak memory 233240 kb
Host smart-115e7617-8fe1-4416-ae11-1e74ddedef0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348608861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2348608861
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2018137777
Short name T877
Test name
Test status
Simulation time 512242989 ps
CPU time 6.88 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:12:14 PM PDT 24
Peak memory 240920 kb
Host smart-b2460ae4-14cc-4a1a-b744-4f98edf68ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018137777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2018137777
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2068013505
Short name T648
Test name
Test status
Simulation time 264088370 ps
CPU time 5.24 seconds
Started Jul 30 05:12:04 PM PDT 24
Finished Jul 30 05:12:10 PM PDT 24
Peak memory 223016 kb
Host smart-f066069c-4c44-4d57-a446-2274346328ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2068013505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2068013505
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2052257275
Short name T528
Test name
Test status
Simulation time 17339230697 ps
CPU time 126.08 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:14:14 PM PDT 24
Peak memory 270472 kb
Host smart-85134063-a0a9-486d-b55a-d0cd65d6fe25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052257275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2052257275
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1399999921
Short name T703
Test name
Test status
Simulation time 629792559 ps
CPU time 4.41 seconds
Started Jul 30 05:12:06 PM PDT 24
Finished Jul 30 05:12:10 PM PDT 24
Peak memory 216792 kb
Host smart-b691a735-35e5-43cd-80a9-16caba755cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399999921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1399999921
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2905301955
Short name T697
Test name
Test status
Simulation time 1281136973 ps
CPU time 2.73 seconds
Started Jul 30 05:12:09 PM PDT 24
Finished Jul 30 05:12:11 PM PDT 24
Peak memory 216676 kb
Host smart-805a67e4-af3f-44c3-86cf-8307dcb73cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905301955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2905301955
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3988045191
Short name T477
Test name
Test status
Simulation time 128365367 ps
CPU time 1.56 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:12:09 PM PDT 24
Peak memory 216596 kb
Host smart-d42be8ce-4000-402a-8da6-f37b1fd46fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988045191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3988045191
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3653702011
Short name T649
Test name
Test status
Simulation time 57392845 ps
CPU time 0.73 seconds
Started Jul 30 05:12:06 PM PDT 24
Finished Jul 30 05:12:07 PM PDT 24
Peak memory 206352 kb
Host smart-517cac43-f2b4-40bd-add7-f99ec183dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653702011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3653702011
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1437369701
Short name T849
Test name
Test status
Simulation time 352094791 ps
CPU time 3.07 seconds
Started Jul 30 05:12:08 PM PDT 24
Finished Jul 30 05:12:11 PM PDT 24
Peak memory 224836 kb
Host smart-1f3b8201-0cbc-4852-9b12-61fe6f7b5c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437369701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1437369701
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2400422662
Short name T360
Test name
Test status
Simulation time 14515915 ps
CPU time 0.7 seconds
Started Jul 30 05:12:09 PM PDT 24
Finished Jul 30 05:12:10 PM PDT 24
Peak memory 205808 kb
Host smart-6b2f6cf7-a4a8-449a-b17d-f722aebe18d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400422662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
400422662
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2189202454
Short name T539
Test name
Test status
Simulation time 968206952 ps
CPU time 6.11 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 224876 kb
Host smart-d6599b6c-3d7d-4cab-adb3-f39e1ad709bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189202454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2189202454
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2950251585
Short name T291
Test name
Test status
Simulation time 60861396 ps
CPU time 0.79 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:12:08 PM PDT 24
Peak memory 207136 kb
Host smart-f8914e5a-df5d-44b7-adb6-e46d76d8054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950251585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2950251585
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1623104009
Short name T262
Test name
Test status
Simulation time 2861728459 ps
CPU time 29.56 seconds
Started Jul 30 05:12:10 PM PDT 24
Finished Jul 30 05:12:40 PM PDT 24
Peak memory 241040 kb
Host smart-9fa500cc-cfe7-4d9f-83ab-1fd66454594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623104009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1623104009
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1002282942
Short name T256
Test name
Test status
Simulation time 12019517569 ps
CPU time 84.19 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:13:39 PM PDT 24
Peak memory 251016 kb
Host smart-b71ca4d0-9a4b-4d60-9160-89da5d2e9459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002282942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1002282942
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2200664497
Short name T128
Test name
Test status
Simulation time 8729304744 ps
CPU time 39.74 seconds
Started Jul 30 05:12:10 PM PDT 24
Finished Jul 30 05:12:49 PM PDT 24
Peak memory 251752 kb
Host smart-38ea514c-b1ea-4dee-beef-61cf18552947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200664497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2200664497
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3986043479
Short name T873
Test name
Test status
Simulation time 158873776 ps
CPU time 2.65 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:12:14 PM PDT 24
Peak memory 233084 kb
Host smart-cb6f96d8-81f3-4d9c-9946-749fde4a6f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986043479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3986043479
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3235849026
Short name T181
Test name
Test status
Simulation time 15848006597 ps
CPU time 112.49 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:14:03 PM PDT 24
Peak memory 250824 kb
Host smart-cc3173d1-3b3a-4281-b7ac-aced06b1f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235849026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3235849026
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1214867673
Short name T975
Test name
Test status
Simulation time 174200407 ps
CPU time 2.18 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:12:14 PM PDT 24
Peak memory 218904 kb
Host smart-dca9464d-1d90-484a-ad20-1ace5dd35e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214867673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1214867673
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2486118077
Short name T82
Test name
Test status
Simulation time 43658896599 ps
CPU time 120.28 seconds
Started Jul 30 05:12:16 PM PDT 24
Finished Jul 30 05:14:17 PM PDT 24
Peak memory 241160 kb
Host smart-0697d285-4b7d-47fb-8f5e-4d9c1071ec55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486118077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2486118077
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3752948104
Short name T985
Test name
Test status
Simulation time 866678176 ps
CPU time 3.36 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 224972 kb
Host smart-9ce59655-1281-4329-8447-b0b4a05c3ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752948104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3752948104
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.735873268
Short name T828
Test name
Test status
Simulation time 1372707892 ps
CPU time 5.65 seconds
Started Jul 30 05:12:13 PM PDT 24
Finished Jul 30 05:12:19 PM PDT 24
Peak memory 233100 kb
Host smart-635dcfc6-61b1-4d1f-9da3-efebb1ac8fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735873268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.735873268
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.506941515
Short name T848
Test name
Test status
Simulation time 837102746 ps
CPU time 3.64 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:12:15 PM PDT 24
Peak memory 220744 kb
Host smart-dd13c8b1-034b-46cb-bc23-3e7e71b2503b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=506941515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.506941515
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.201720994
Short name T869
Test name
Test status
Simulation time 10018775648 ps
CPU time 76.57 seconds
Started Jul 30 05:12:10 PM PDT 24
Finished Jul 30 05:13:27 PM PDT 24
Peak memory 253220 kb
Host smart-84c2a3b0-bdbb-4c38-82aa-6d2493321ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201720994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.201720994
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2271384554
Short name T609
Test name
Test status
Simulation time 2341180822 ps
CPU time 13.21 seconds
Started Jul 30 05:12:06 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 220232 kb
Host smart-e720c2b6-ccc5-430d-b1d9-33a1d731ccf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271384554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2271384554
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3795973211
Short name T814
Test name
Test status
Simulation time 1006431094 ps
CPU time 7.57 seconds
Started Jul 30 05:12:07 PM PDT 24
Finished Jul 30 05:12:15 PM PDT 24
Peak memory 216720 kb
Host smart-198370f7-8f7c-4516-a2b6-d05901913b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795973211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3795973211
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.491813889
Short name T604
Test name
Test status
Simulation time 554019229 ps
CPU time 10.38 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:26 PM PDT 24
Peak memory 216688 kb
Host smart-5dddc654-7ef9-4013-8160-483a28b1afce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491813889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.491813889
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.49292781
Short name T931
Test name
Test status
Simulation time 286519478 ps
CPU time 0.85 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:12:12 PM PDT 24
Peak memory 206380 kb
Host smart-bb6fdaf8-b86d-49f6-8713-f5302424180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49292781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.49292781
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.394975635
Short name T980
Test name
Test status
Simulation time 149011045 ps
CPU time 2.24 seconds
Started Jul 30 05:12:10 PM PDT 24
Finished Jul 30 05:12:13 PM PDT 24
Peak memory 224556 kb
Host smart-9922f6df-ee13-4816-988b-e1904c387ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394975635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.394975635
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2019149954
Short name T698
Test name
Test status
Simulation time 98816092 ps
CPU time 0.75 seconds
Started Jul 30 05:12:18 PM PDT 24
Finished Jul 30 05:12:19 PM PDT 24
Peak memory 205876 kb
Host smart-9a7aef42-33cc-44c9-807c-35f5a1429271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019149954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
019149954
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2520666507
Short name T323
Test name
Test status
Simulation time 577145950 ps
CPU time 2.79 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 224924 kb
Host smart-9f882f32-a0ad-4706-a9b9-81f795c74a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520666507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2520666507
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1604343699
Short name T333
Test name
Test status
Simulation time 47167272 ps
CPU time 0.8 seconds
Started Jul 30 05:12:09 PM PDT 24
Finished Jul 30 05:12:10 PM PDT 24
Peak memory 207356 kb
Host smart-fa0764bd-fc36-46df-9ec9-a5617c4860f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604343699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1604343699
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.861299839
Short name T201
Test name
Test status
Simulation time 3484726525 ps
CPU time 79.53 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:13:35 PM PDT 24
Peak memory 250140 kb
Host smart-48a13744-92a8-4128-88b0-4f558066783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861299839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.861299839
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3217512749
Short name T35
Test name
Test status
Simulation time 7842912099 ps
CPU time 34.87 seconds
Started Jul 30 05:12:19 PM PDT 24
Finished Jul 30 05:12:54 PM PDT 24
Peak memory 250596 kb
Host smart-26c071aa-6133-47a5-bd65-4213fb16ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217512749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3217512749
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.837767812
Short name T906
Test name
Test status
Simulation time 2391797157 ps
CPU time 28.33 seconds
Started Jul 30 05:12:17 PM PDT 24
Finished Jul 30 05:12:45 PM PDT 24
Peak memory 225052 kb
Host smart-a697490f-0f43-407f-8b15-8e2a166df33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837767812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
837767812
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2944979800
Short name T742
Test name
Test status
Simulation time 227681994 ps
CPU time 3.2 seconds
Started Jul 30 05:12:16 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 233148 kb
Host smart-06367dbe-296a-4013-aab0-d66a515d5f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944979800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2944979800
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2796051292
Short name T249
Test name
Test status
Simulation time 10206024596 ps
CPU time 89.62 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:13:45 PM PDT 24
Peak memory 252392 kb
Host smart-90c41b3f-5f91-4002-b02d-67a08c30f726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796051292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2796051292
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3377782655
Short name T473
Test name
Test status
Simulation time 444936934 ps
CPU time 8.94 seconds
Started Jul 30 05:12:17 PM PDT 24
Finished Jul 30 05:12:26 PM PDT 24
Peak memory 224956 kb
Host smart-6d20bf1c-ad69-45e5-9bfb-b444fd80a458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377782655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3377782655
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1188740876
Short name T226
Test name
Test status
Simulation time 5725037165 ps
CPU time 25.26 seconds
Started Jul 30 05:12:16 PM PDT 24
Finished Jul 30 05:12:41 PM PDT 24
Peak memory 233180 kb
Host smart-05440435-acec-474c-b0d3-48a93d9d5ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188740876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1188740876
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.288287348
Short name T662
Test name
Test status
Simulation time 133408392 ps
CPU time 2.36 seconds
Started Jul 30 05:12:14 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 224820 kb
Host smart-ff9b35fb-6483-4e6e-8b45-1bf7c286b903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288287348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
288287348
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3262432029
Short name T608
Test name
Test status
Simulation time 763089040 ps
CPU time 4.31 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 241212 kb
Host smart-73837e9b-d15f-481b-ad26-c979752005ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262432029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3262432029
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3011226967
Short name T458
Test name
Test status
Simulation time 195832607 ps
CPU time 3.93 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:20 PM PDT 24
Peak memory 219080 kb
Host smart-1a29f927-fe1b-41bc-8c21-3da3e010b144
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3011226967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3011226967
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1157476809
Short name T146
Test name
Test status
Simulation time 238575081 ps
CPU time 1.18 seconds
Started Jul 30 05:12:16 PM PDT 24
Finished Jul 30 05:12:17 PM PDT 24
Peak memory 207328 kb
Host smart-9265bdf9-9a61-4f77-8edf-907151a06dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157476809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1157476809
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1407577779
Short name T940
Test name
Test status
Simulation time 6618214164 ps
CPU time 17.3 seconds
Started Jul 30 05:12:12 PM PDT 24
Finished Jul 30 05:12:29 PM PDT 24
Peak memory 216756 kb
Host smart-49b0b20b-b035-47c5-bdbb-6ec4d0476a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407577779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1407577779
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1747010626
Short name T911
Test name
Test status
Simulation time 789766438 ps
CPU time 4.8 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:12:16 PM PDT 24
Peak memory 216656 kb
Host smart-f47ffcef-1cfb-4089-8924-1be859c6f874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747010626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1747010626
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.275233851
Short name T936
Test name
Test status
Simulation time 187792874 ps
CPU time 2.15 seconds
Started Jul 30 05:12:13 PM PDT 24
Finished Jul 30 05:12:15 PM PDT 24
Peak memory 216672 kb
Host smart-f935aaa3-4fec-44ff-9d5c-6a2da8949936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275233851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.275233851
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.631804245
Short name T290
Test name
Test status
Simulation time 134335462 ps
CPU time 1.06 seconds
Started Jul 30 05:12:11 PM PDT 24
Finished Jul 30 05:12:12 PM PDT 24
Peak memory 207376 kb
Host smart-93b69f23-3ab5-43e2-8efd-411cb7e124ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631804245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.631804245
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1286504650
Short name T690
Test name
Test status
Simulation time 2650421427 ps
CPU time 10.53 seconds
Started Jul 30 05:12:15 PM PDT 24
Finished Jul 30 05:12:25 PM PDT 24
Peak memory 224960 kb
Host smart-f96c8b61-3974-48e9-afab-feefff0b037f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286504650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1286504650
Directory /workspace/9.spi_device_upload/latest
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