Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2856964	1			T1	150		T2	3556		T3	1
all_values[1]	2856964	1			T1	150		T2	3556		T3	1
all_values[2]	2856964	1			T1	150		T2	3556		T3	1
all_values[3]	2856964	1			T1	150		T2	3556		T3	1
all_values[4]	2856964	1			T1	150		T2	3556		T3	1
all_values[5]	2856964	1			T1	150		T2	3556		T3	1
all_values[6]	2856964	1			T1	150		T2	3556		T3	1
all_values[7]	2856964	1			T1	150		T2	3556		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22691033

1

T1

1200

T2

28448

T3

8

auto[1]

164679

1

T7

22868

T12

129

T32

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22828936

1

T1

1200

T2

28448

T3

8

auto[1]

26776

1

T7

164

T8

125

T12

92

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2843540	1			T1	150		T2	3556		T3	1
all_values[0]	auto[0]	auto[1]	12937	1			T7	57		T8	70		T12	3
all_values[0]	auto[1]	auto[0]	297	1			T7	3		T12	12		T16	1
all_values[0]	auto[1]	auto[1]	190	1			T7	1		T12	5		T16	1
all_values[1]	auto[0]	auto[0]	2810243	1			T1	150		T2	3556		T3	1
all_values[1]	auto[0]	auto[1]	8094	1			T7	1		T8	34		T12	4
all_values[1]	auto[1]	auto[0]	38276	1			T7	4514		T12	12		T16	3
all_values[1]	auto[1]	auto[1]	351	1			T7	55		T12	5		T32	1
all_values[2]	auto[0]	auto[0]	2848847	1			T1	150		T2	3556		T3	1
all_values[2]	auto[0]	auto[1]	3068	1			T7	3		T8	21		T12	4
all_values[2]	auto[1]	auto[0]	4836	1			T7	4550		T12	3		T32	2
all_values[2]	auto[1]	auto[1]	213	1			T7	21		T12	5		T32	2
all_values[3]	auto[0]	auto[0]	2817233	1			T1	150		T2	3556		T3	1
all_values[3]	auto[0]	auto[1]	182	1			T7	2		T12	6		T143	1
all_values[3]	auto[1]	auto[0]	39342	1			T7	4566		T12	6		T32	1
all_values[3]	auto[1]	auto[1]	207	1			T7	6		T12	9		T16	2
all_values[4]	auto[0]	auto[0]	2850808	1			T1	150		T2	3556		T3	1
all_values[4]	auto[0]	auto[1]	220	1			T12	4		T142	1		T32	2
all_values[4]	auto[1]	auto[0]	5740	1			T7	4569		T12	14		T17	5
all_values[4]	auto[1]	auto[1]	196	1			T7	3		T12	7		T32	1
all_values[5]	auto[0]	auto[0]	2850821	1			T1	150		T2	3556		T3	1
all_values[5]	auto[0]	auto[1]	184	1			T7	2		T12	6		T32	1
all_values[5]	auto[1]	auto[0]	5776	1			T7	4570		T12	15		T32	2
all_values[5]	auto[1]	auto[1]	183	1			T7	3		T12	5		T16	2
all_values[6]	auto[0]	auto[0]	2821793	1			T1	150		T2	3556		T3	1
all_values[6]	auto[0]	auto[1]	206	1			T7	5		T12	7		T32	2
all_values[6]	auto[1]	auto[0]	34790	1			T7	3		T12	6		T32	2
all_values[6]	auto[1]	auto[1]	175	1			T12	7		T16	2		T17	4
all_values[7]	auto[0]	auto[0]	2822674	1			T1	150		T2	3556		T3	1
all_values[7]	auto[0]	auto[1]	183	1			T7	4		T12	6		T16	3
all_values[7]	auto[1]	auto[0]	33920	1			T7	3		T12	9		T32	2
all_values[7]	auto[1]	auto[1]	187	1			T7	1		T12	9		T16	1