Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33142	1			T1	23		T2	31		T3	8
auto[SpiFlashAddrCfg]	7846	1			T1	15		T2	11		T5	1
auto[SpiFlashAddr3b]	9234	1			T1	20		T2	19		T4	2
auto[SpiFlashAddr4b]	7690	1			T1	2		T2	19		T7	23

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33352

1

T1

28

T2

46

T3

8

auto[1]

24560

1

T1

32

T2

34

T7

50

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31093

1

T1

30

T2

44

T3

8

auto[1]

26819

1

T1

30

T2

36

T4

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37823	1			T1	29		T2	42		T3	8
values[1]	1144	1			T1	2		T2	3		T7	5
values[2]	1459	1			T1	1		T2	1		T4	2
values[3]	1560	1			T1	10		T2	4		T5	1
values[4]	1544	1			T1	1		T2	1		T7	4
values[5]	1489	1			T2	2		T7	3		T8	3
values[6]	1555	1			T1	1		T2	3		T7	3
values[7]	1441	1			T2	3		T7	5		T8	9
values[8]	9897	1			T1	16		T2	21		T7	24

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31842

1

T2

80

T3

8

T10

4

auto[1]

26070

1

T1

60

T4

2

T5

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54679

1

T1

55

T2

70

T3

8

write

3233

1

T1

5

T2

10

T7

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19530

1

T1

28

T2

43

T3

8

valids[0x1]

38382

1

T1

32

T2

37

T7

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1616	1			T1	2		T2	3		T7	1
internal_process_ops[0x5a]	1640	1			T1	4		T2	2		T7	1
internal_process_ops[0x05]	19110	1			T2	2		T7	23		T8	141
internal_process_ops[0x35]	1503	1			T1	2		T2	5		T7	2
internal_process_ops[0x15]	1610	1			T1	4		T2	3		T7	2
internal_process_ops[0x03]	1072	1			T1	1		T2	3		T7	1
internal_process_ops[0x0b]	1102	1			T2	1		T7	1		T8	1
internal_process_ops[0x3b]	1143	1			T1	1		T2	4		T7	4
internal_process_ops[0x6b]	1042	1			T2	4		T4	2		T7	1
internal_process_ops[0xbb]	1089	1			T2	4		T5	1		T7	3
internal_process_ops[0xeb]	1019	1			T2	3		T7	1		T8	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56376

1

T1

57

T2

74

T3

8

auto[1]

1536

1

T1

3

T2

6

T8

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55614

1

T1

55

T2

71

T3

8

auto[1]

2298

1

T1

5

T2

9

T7

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10784

1

T2

19

T3

8

T14

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6677

1

T2

8

T24

10

T38

69

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2181

1

T2

4

T10

4

T13

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1950

1

T2

6

T24

10

T38

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2600

1

T2

8

T14

4

T38

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2176

1

T2

8

T23

4

T24

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2105

1

T2

7

T13

8

T14

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1850

1

T2

10

T23

2

T24

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

132

1

T2

2

T38

3

T39

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

93

1

T38

2

T39

2

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T46

1

T16

3

T66

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

97

1

T2

2

T38

3

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T32

1

T46

1

T159

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

100

1

T2

1

T39

2

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T46

2

T47

2

T48

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T47

3

T50

2

T16

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

120

1

T2

1

T39

3

T49

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

90

1

T2

2

T39

4

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T39

1

T46

1

T49

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

76

1

T39

2

T16

1

T56

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T2

1

T32

2

T159

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T2

1

T38

1

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T38

1

T39

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

81

1

T24

2

T32

1

T49

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9175

1

T1

15

T7

40

T8

87

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5723

1

T1

5

T7

22

T8

131

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1446

1

T1

5

T5

1

T7

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1386

1

T1

9

T7

11

T8

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1862

1

T1

5

T4

2

T7

4

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1848

1

T1

14

T7

5

T8

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1497

1

T1

1

T7

9

T8

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1419

1

T1

1

T7

10

T8

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

91

1

T40

3

T30

2

T160

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T8

1

T34

1

T62

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T1

1

T34

2

T32

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T1

2

T34

1

T30

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

127

1

T1

1

T8

1

T34

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

121

1

T34

2

T30

3

T32

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

133

1

T7

2

T8

1

T40

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T34

1

T30

1

T97

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T7

1

T8

1

T30

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T1

1

T8

3

T30

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T34

2

T63

1

T64

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T8

3

T30

1

T97

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

131

1

T7

4

T8

2

T34

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

113

1

T8

4

T34

1

T32

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

108

1

T34

3

T30

1

T32

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

125

1

T34

2

T30

1

T32

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3963	1			T2	13		T3	8		T14	4
auto[0]	values[0]	valids[0x1]	16366	1			T2	29		T14	10		T24	10
auto[0]	values[1]	valids[0x1]	590	1			T2	3		T38	5		T45	2
auto[0]	values[2]	valids[0x0]	568	1			T2	1		T38	5		T39	8
auto[0]	values[2]	valids[0x1]	298	1			T13	8		T39	5		T46	2
auto[0]	values[3]	valids[0x0]	619	1			T2	4		T10	2		T24	2
auto[0]	values[3]	valids[0x1]	303	1			T38	2		T70	6		T45	2
auto[0]	values[4]	valids[0x0]	573	1			T2	1		T38	4		T44	2
auto[0]	values[4]	valids[0x1]	302	1			T38	3		T39	5		T46	2
auto[0]	values[5]	valids[0x0]	529	1			T2	2		T24	2		T41	2
auto[0]	values[5]	valids[0x1]	317	1			T38	1		T39	1		T46	1
auto[0]	values[6]	valids[0x0]	548	1			T2	3		T13	4		T14	2
auto[0]	values[6]	valids[0x1]	324	1			T38	1		T32	5		T46	3
auto[0]	values[7]	valids[0x0]	531	1			T2	3		T38	2		T45	2
auto[0]	values[7]	valids[0x1]	318	1			T24	2		T38	1		T44	4
auto[0]	values[8]	valids[0x0]	3577	1			T2	16		T23	2		T24	6
auto[0]	values[8]	valids[0x1]	2116	1			T2	5		T10	2		T14	4
auto[1]	values[0]	valids[0x0]	3888	1			T1	11		T7	25		T8	47
auto[1]	values[0]	valids[0x1]	13606	1			T1	18		T7	39		T8	193
auto[1]	values[1]	valids[0x1]	554	1			T1	2		T7	5		T8	8
auto[1]	values[2]	valids[0x0]	337	1			T1	1		T4	2		T7	3
auto[1]	values[2]	valids[0x1]	256	1			T7	3		T8	3		T34	5
auto[1]	values[3]	valids[0x0]	391	1			T1	5		T5	1		T7	7
auto[1]	values[3]	valids[0x1]	247	1			T1	5		T7	1		T34	5
auto[1]	values[4]	valids[0x0]	381	1			T7	1		T8	9		T34	4
auto[1]	values[4]	valids[0x1]	288	1			T1	1		T7	3		T8	4
auto[1]	values[5]	valids[0x0]	377	1			T7	3		T8	2		T34	6
auto[1]	values[5]	valids[0x1]	266	1			T8	1		T34	4		T40	4
auto[1]	values[6]	valids[0x0]	409	1			T1	1		T8	5		T34	5
auto[1]	values[6]	valids[0x1]	274	1			T7	3		T8	5		T34	8
auto[1]	values[7]	valids[0x0]	344	1			T7	2		T8	2		T34	6
auto[1]	values[7]	valids[0x1]	248	1			T7	3		T8	7		T34	3
auto[1]	values[8]	valids[0x0]	2495	1			T1	10		T7	17		T8	21
auto[1]	values[8]	valids[0x1]	1709	1			T1	6		T7	7		T8	16