Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3379264

1

T1

1151

T2

7414

T3

5629

auto[1]

25492

1

T1

26

T2

41

T7

22

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

915727

1

T1

144

T2

199

T3

5629

auto[1]

2489029

1

T1

1033

T2

7256

T7

1279

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	621548	1			T1	299		T2	4239		T3	1398
auto[524288:1048575]	372998	1			T1	7		T2	18		T5	3
auto[1048576:1572863]	406320	1			T1	16		T2	19		T3	5
auto[1572864:2097151]	360562	1			T1	526		T2	8		T3	1232
auto[2097152:2621439]	419904	1			T1	288		T3	143		T7	9
auto[2621440:3145727]	399565	1			T2	671		T3	668		T7	2
auto[3145728:3670015]	407266	1			T1	34		T2	2500		T3	820
auto[3670016:4194303]	416593	1			T1	7		T3	1363		T7	949

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2524565

1

T1

1173

T2

7447

T3

91

auto[1]

880191

1

T1

4

T2

8

T3

5538

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2928693

1

T1

1153

T2

4903

T3

5629

auto[1]

476063

1

T1

24

T2

2552

T7

1279

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	180031	1			T1	24		T2	66		T3	1398
auto[0]	auto[0]	auto[0:524287]	auto[1]	369264	1			T1	256		T2	4141		T7	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	93229	1			T5	3		T8	10		T13	2576
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	222415	1			T8	433		T34	4143		T39	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	102185	1			T1	6		T2	19		T3	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	237440	1			T1	4		T7	1		T8	359
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	86780	1			T1	14		T3	1232		T4	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	226107	1			T1	512		T8	971		T38	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	127620	1			T1	24		T3	143		T7	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	230130	1			T1	256		T7	1		T8	1538
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	117824	1			T2	28		T3	668		T7	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	229967	1			T2	640		T8	772		T38	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92798	1			T1	26		T3	820		T7	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	259040	1			T1	5		T7	1		T38	2915
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	100456	1			T1	7		T3	1363		T8	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	232690	1			T8	256		T38	768		T34	2507
auto[0]	auto[1]	auto[0:524287]	auto[0]	1647	1			T1	9		T2	17		T7	8
auto[0]	auto[1]	auto[0:524287]	auto[1]	67485	1			T2	3		T7	1		T8	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	795	1			T1	2		T2	12		T8	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	53285	1			T30	130		T32	512		T46	131
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	691	1			T1	6		T34	19		T40	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	62514	1			T34	256		T30	1209		T32	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1322	1			T2	3		T38	1		T39	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43345	1			T38	5		T32	129		T97	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	885	1			T8	2		T34	14		T39	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	57974	1			T8	1		T48	2629		T214	861
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	696	1			T7	1		T8	1		T38	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	48000	1			T8	3		T38	2641		T39	128
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1104	1			T2	16		T7	4		T8	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	51103	1			T2	2469		T7	306		T38	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	3857	1			T34	17		T39	4		T32	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	76585	1			T7	949		T34	3217		T30	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	466	1			T1	3		T2	6		T7	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2059	1			T7	1		T8	73		T38	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	418	1			T1	5		T8	3		T34	20
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2013	1			T8	16		T32	11		T48	12
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	309	1			T7	1		T8	1		T38	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2379	1			T7	4		T8	2		T38	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	363	1			T8	1		T38	1		T30	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1854	1			T8	5		T38	5		T30	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	413	1			T1	8		T7	1		T8	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2406	1			T7	2		T8	1		T38	12
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	324	1			T2	3		T8	1		T38	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2220	1			T8	14		T38	12		T32	53
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	421	1			T1	3		T7	1		T38	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2333	1			T7	1		T38	20		T32	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	350	1			T34	6		T39	6		T40	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2389	1			T39	23		T32	14		T50	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	91	1			T1	7		T2	6		T7	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	505	1			T7	8		T8	3		T46	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	96	1			T2	6		T39	3		T16	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	747	1			T16	2		T64	3		T179	32
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	107	1			T49	1		T207	3		T55	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	695	1			T160	9		T208	13		T19	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	105	1			T2	5		T32	1		T97	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	686	1			T207	42		T218	22		T22	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	84	1			T8	1		T34	5		T39	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	392	1			T8	3		T48	17		T214	13
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	85	1			T38	1		T34	9		T32	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	449	1			T38	13		T32	15		T55	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	88	1			T2	12		T7	1		T34	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	379	1			T2	3		T48	4		T17	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	87	1			T34	9		T97	3		T56	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	179	1			T56	2		T19	1		T84	33

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2034268	1			T1	1134		T2	4894		T3	91
auto[0]	auto[0]	auto[1]	873708	1			T3	5538		T4	162		T5	1
auto[0]	auto[1]	auto[0]	465444	1			T1	17		T2	2520		T7	1269
auto[0]	auto[1]	auto[1]	5844	1			T46	1		T48	1		T93	14
auto[1]	auto[0]	auto[0]	20218	1			T1	16		T2	6		T7	12
auto[1]	auto[0]	auto[1]	499	1			T1	3		T2	3		T8	5
auto[1]	auto[1]	auto[0]	4635	1			T1	6		T2	27		T7	10
auto[1]	auto[1]	auto[1]	140	1			T1	1		T2	5		T38	1