Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2856964	1			T1	150		T2	3556		T3	1
all_pins[1]	2856964	1			T1	150		T2	3556		T3	1
all_pins[2]	2856964	1			T1	150		T2	3556		T3	1
all_pins[3]	2856964	1			T1	150		T2	3556		T3	1
all_pins[4]	2856964	1			T1	150		T2	3556		T3	1
all_pins[5]	2856964	1			T1	150		T2	3556		T3	1
all_pins[6]	2856964	1			T1	150		T2	3556		T3	1
all_pins[7]	2856964	1			T1	150		T2	3556		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22818766	1			T1	1200		T2	28448		T3	8
values[0x1]	36946	1			T7	623		T12	52		T32	4
transitions[0x0=>0x1]	36350	1			T7	600		T12	35		T32	4
transitions[0x1=>0x0]	36359	1			T7	600		T12	35		T32	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2856774	1			T1	150		T2	3556		T3	1
all_pins[0]	values[0x1]	190	1			T7	1		T12	5		T16	1
all_pins[0]	transitions[0x0=>0x1]	144	1			T7	1		T12	2		T16	1
all_pins[0]	transitions[0x1=>0x0]	326	1			T7	60		T12	2		T32	1
all_pins[1]	values[0x0]	2856592	1			T1	150		T2	3556		T3	1
all_pins[1]	values[0x1]	372	1			T7	60		T12	5		T32	1
all_pins[1]	transitions[0x0=>0x1]	315	1			T7	43		T12	5		T32	1
all_pins[1]	transitions[0x1=>0x0]	157	1			T7	5		T12	5		T32	2
all_pins[2]	values[0x0]	2856750	1			T1	150		T2	3556		T3	1
all_pins[2]	values[0x1]	214	1			T7	22		T12	5		T32	2
all_pins[2]	transitions[0x0=>0x1]	170	1			T7	18		T12	2		T32	2
all_pins[2]	transitions[0x1=>0x0]	163	1			T7	2		T12	6		T16	2
all_pins[3]	values[0x0]	2856757	1			T1	150		T2	3556		T3	1
all_pins[3]	values[0x1]	207	1			T7	6		T12	9		T16	2
all_pins[3]	transitions[0x0=>0x1]	150	1			T7	5		T12	3		T16	1
all_pins[3]	transitions[0x1=>0x0]	139	1			T7	2		T12	1		T32	1
all_pins[4]	values[0x0]	2856768	1			T1	150		T2	3556		T3	1
all_pins[4]	values[0x1]	196	1			T7	3		T12	7		T32	1
all_pins[4]	transitions[0x0=>0x1]	150	1			T7	2		T12	5		T32	1
all_pins[4]	transitions[0x1=>0x0]	893	1			T7	529		T12	3		T16	1
all_pins[5]	values[0x0]	2856025	1			T1	150		T2	3556		T3	1
all_pins[5]	values[0x1]	939	1			T7	530		T12	5		T16	2
all_pins[5]	transitions[0x0=>0x1]	673	1			T7	530		T12	4		T16	2
all_pins[5]	transitions[0x1=>0x0]	34375	1			T12	6		T16	2		T17	2
all_pins[6]	values[0x0]	2822323	1			T1	150		T2	3556		T3	1
all_pins[6]	values[0x1]	34641	1			T12	7		T16	2		T17	4
all_pins[6]	transitions[0x0=>0x1]	34603	1			T12	5		T16	2		T17	3
all_pins[6]	transitions[0x1=>0x0]	149	1			T7	1		T12	7		T16	1
all_pins[7]	values[0x0]	2856777	1			T1	150		T2	3556		T3	1
all_pins[7]	values[0x1]	187	1			T7	1		T12	9		T16	1
all_pins[7]	transitions[0x0=>0x1]	145	1			T7	1		T12	9		T17	2
all_pins[7]	transitions[0x1=>0x0]	157	1			T7	1		T12	5		T16	1