Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18505

1

T2

46

T3

8

T10

4

auto[1]

13337

1

T2

34

T23

6

T24

26

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3484	1			T2	40		T3	8		T38	95
values[1]	3888	1			T39	60		T41	4		T47	40
values[2]	4387	1			T51	4		T38	74		T96	16
values[3]	3415	1			T23	6		T39	20		T46	44
values[4]	3616	1			T204	4		T39	20		T32	52
values[5]	3816	1			T13	12		T14	20		T39	20
values[6]	4615	1			T2	20		T10	4		T38	44
values[7]	4621	1			T2	20		T24	26		T39	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4209	1			T3	8		T10	4		T51	4
values[1]	4250	1			T2	20		T13	12		T45	20
values[2]	3776	1			T2	20		T39	20		T32	24
values[3]	5092	1			T14	20		T23	6		T38	49
values[4]	3464	1			T39	20		T32	29		T47	20
values[5]	3538	1			T96	16		T70	14		T44	30
values[6]	3751	1			T38	97		T46	41		T159	39
values[7]	3762	1			T2	40		T24	26		T38	42

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	258	1			T3	8		T46	17		T49	14
auto[0]	values[0]	values[1]	267	1			T2	13		T45	20		T19	29
auto[0]	values[0]	values[2]	148	1			T157	10		T219	15		T220	11
auto[0]	values[0]	values[3]	428	1			T32	13		T48	14		T16	7
auto[0]	values[0]	values[4]	313	1			T182	11		T22	9		T221	8
auto[0]	values[0]	values[5]	268	1			T39	33		T222	6		T49	14
auto[0]	values[0]	values[6]	264	1			T38	24		T84	13		T126	35
auto[0]	values[0]	values[7]	174	1			T2	12		T38	11		T186	11
auto[0]	values[1]	values[0]	356	1			T50	8		T55	15		T202	16
auto[0]	values[1]	values[1]	322	1			T16	8		T187	6		T19	11
auto[0]	values[1]	values[2]	153	1			T39	17		T22	12		T126	9
auto[0]	values[1]	values[3]	161	1			T39	21		T17	13		T56	12
auto[0]	values[1]	values[4]	169	1			T47	15		T17	9		T184	8
auto[0]	values[1]	values[5]	226	1			T16	13		T22	12		T190	10
auto[0]	values[1]	values[6]	283	1			T16	17		T55	18		T171	9
auto[0]	values[1]	values[7]	323	1			T41	4		T47	10		T66	15
auto[0]	values[2]	values[0]	345	1			T51	4		T38	18		T16	167
auto[0]	values[2]	values[1]	275	1			T203	14		T171	19		T223	22
auto[0]	values[2]	values[2]	432	1			T193	20		T50	14		T176	10
auto[0]	values[2]	values[3]	329	1			T38	43		T184	15		T35	13
auto[0]	values[2]	values[4]	266	1			T55	14		T224	2		T17	13
auto[0]	values[2]	values[5]	275	1			T96	16		T70	14		T44	30
auto[0]	values[2]	values[6]	290	1			T46	33		T159	39		T47	7
auto[0]	values[2]	values[7]	282	1			T32	27		T46	13		T56	10
auto[0]	values[3]	values[0]	273	1			T225	12		T19	9		T157	20
auto[0]	values[3]	values[1]	181	1			T202	9		T226	2		T227	6
auto[0]	values[3]	values[2]	334	1			T202	15		T170	16		T56	15
auto[0]	values[3]	values[3]	364	1			T39	14		T16	15		T182	10
auto[0]	values[3]	values[4]	306	1			T202	7		T126	12		T136	50
auto[0]	values[3]	values[5]	117	1			T202	11		T183	13		T195	6
auto[0]	values[3]	values[6]	374	1			T186	10		T228	26		T229	4
auto[0]	values[3]	values[7]	127	1			T46	7		T230	6		T19	19
auto[0]	values[4]	values[0]	370	1			T46	8		T172	64		T35	15
auto[0]	values[4]	values[1]	212	1			T46	11		T136	16		T231	8
auto[0]	values[4]	values[2]	170	1			T32	17		T46	10		T50	12
auto[0]	values[4]	values[3]	513	1			T32	10		T16	17		T55	10
auto[0]	values[4]	values[4]	163	1			T196	10		T17	10		T84	10
auto[0]	values[4]	values[5]	213	1			T204	4		T39	7		T136	30
auto[0]	values[4]	values[6]	245	1			T157	15		T190	12		T35	17
auto[0]	values[4]	values[7]	306	1			T56	7		T182	11		T184	14
auto[0]	values[5]	values[0]	545	1			T17	20		T176	14		T35	12
auto[0]	values[5]	values[1]	398	1			T13	12		T47	12		T16	17
auto[0]	values[5]	values[2]	240	1			T171	15		T232	4		T191	12
auto[0]	values[5]	values[3]	364	1			T14	20		T233	14		T56	31
auto[0]	values[5]	values[4]	180	1			T39	12		T32	22		T16	23
auto[0]	values[5]	values[5]	245	1			T49	11		T176	6		T234	20
auto[0]	values[5]	values[6]	231	1			T49	13		T182	10		T235	10
auto[0]	values[5]	values[7]	345	1			T46	12		T202	16		T126	12
auto[0]	values[6]	values[0]	176	1			T10	4		T17	10		T56	7
auto[0]	values[6]	values[1]	391	1			T206	22		T236	2		T55	12
auto[0]	values[6]	values[2]	370	1			T2	11		T237	2		T65	14
auto[0]	values[6]	values[3]	490	1			T39	10		T49	7		T171	12
auto[0]	values[6]	values[4]	185	1			T238	12		T184	14		T185	12
auto[0]	values[6]	values[5]	301	1			T98	6		T47	7		T239	12
auto[0]	values[6]	values[6]	178	1			T38	8		T49	11		T126	12
auto[0]	values[6]	values[7]	242	1			T47	24		T49	9		T202	8
auto[0]	values[7]	values[0]	326	1			T47	10		T93	8		T56	14
auto[0]	values[7]	values[1]	323	1			T66	10		T186	10		T35	11
auto[0]	values[7]	values[2]	239	1			T48	28		T179	45		T184	11
auto[0]	values[7]	values[3]	321	1			T46	11		T240	4		T17	14
auto[0]	values[7]	values[4]	442	1			T16	9		T241	14		T126	22
auto[0]	values[7]	values[5]	402	1			T39	14		T242	2		T126	18
auto[0]	values[7]	values[6]	307	1			T49	49		T243	20		T56	14
auto[0]	values[7]	values[7]	389	1			T2	10		T19	37		T136	9
auto[1]	values[0]	values[0]	135	1			T46	6		T49	6		T176	12
auto[1]	values[0]	values[1]	149	1			T2	7		T19	5		T22	11
auto[1]	values[0]	values[2]	76	1			T157	13		T219	5		T220	9
auto[1]	values[0]	values[3]	411	1			T32	16		T48	24		T16	18
auto[1]	values[0]	values[4]	154	1			T174	18		T182	29		T22	15
auto[1]	values[0]	values[5]	79	1			T39	27		T49	12		T202	10
auto[1]	values[0]	values[6]	181	1			T38	29		T84	7		T126	15
auto[1]	values[0]	values[7]	179	1			T2	8		T38	31		T186	9
auto[1]	values[1]	values[0]	365	1			T50	14		T55	9		T202	6
auto[1]	values[1]	values[1]	232	1			T16	17		T19	12		T244	14
auto[1]	values[1]	values[2]	181	1			T39	3		T22	10		T126	12
auto[1]	values[1]	values[3]	211	1			T39	19		T17	7		T56	8
auto[1]	values[1]	values[4]	113	1			T47	5		T17	11		T184	12
auto[1]	values[1]	values[5]	349	1			T16	8		T22	8		T190	103
auto[1]	values[1]	values[6]	184	1			T16	3		T55	6		T171	11
auto[1]	values[1]	values[7]	260	1			T47	10		T66	5		T19	8
auto[1]	values[2]	values[0]	151	1			T38	7		T16	9		T55	4
auto[1]	values[2]	values[1]	361	1			T171	7		T211	8		T136	7
auto[1]	values[2]	values[2]	234	1			T50	6		T176	51		T35	11
auto[1]	values[2]	values[3]	179	1			T38	6		T184	5		T35	8
auto[1]	values[2]	values[4]	252	1			T55	11		T17	8		T56	10
auto[1]	values[2]	values[5]	212	1			T56	8		T22	5		T126	8
auto[1]	values[2]	values[6]	320	1			T46	8		T47	13		T48	29
auto[1]	values[2]	values[7]	184	1			T32	10		T46	7		T56	10
auto[1]	values[3]	values[0]	214	1			T19	11		T157	4		T126	5
auto[1]	values[3]	values[1]	124	1			T202	11		T211	8		T215	10
auto[1]	values[3]	values[2]	155	1			T202	5		T56	16		T211	6
auto[1]	values[3]	values[3]	157	1			T23	6		T39	6		T16	8
auto[1]	values[3]	values[4]	175	1			T202	30		T126	8		T136	9
auto[1]	values[3]	values[5]	205	1			T202	11		T183	7		T195	14
auto[1]	values[3]	values[6]	171	1			T186	10		T35	53		T195	33
auto[1]	values[3]	values[7]	138	1			T46	37		T19	1		T182	8
auto[1]	values[4]	values[0]	163	1			T46	12		T35	5		T215	10
auto[1]	values[4]	values[1]	316	1			T46	9		T136	4		T183	6
auto[1]	values[4]	values[2]	117	1			T32	7		T46	10		T50	10
auto[1]	values[4]	values[3]	211	1			T32	18		T16	73		T55	11
auto[1]	values[4]	values[4]	154	1			T17	10		T84	55		T35	12
auto[1]	values[4]	values[5]	167	1			T39	13		T136	10		T183	7
auto[1]	values[4]	values[6]	137	1			T157	7		T190	8		T35	3
auto[1]	values[4]	values[7]	159	1			T56	14		T182	9		T184	6
auto[1]	values[5]	values[0]	145	1			T17	14		T176	16		T35	8
auto[1]	values[5]	values[1]	204	1			T47	8		T16	3		T179	8
auto[1]	values[5]	values[2]	122	1			T171	6		T19	15		T182	9
auto[1]	values[5]	values[3]	109	1			T56	6		T245	4		T184	8
auto[1]	values[5]	values[4]	97	1			T39	8		T32	7		T16	17
auto[1]	values[5]	values[5]	136	1			T49	9		T176	17		T157	15
auto[1]	values[5]	values[6]	322	1			T49	25		T182	13		T246	95
auto[1]	values[5]	values[7]	133	1			T46	8		T202	10		T126	8
auto[1]	values[6]	values[0]	147	1			T17	10		T56	17		T186	6
auto[1]	values[6]	values[1]	142	1			T55	10		T182	6		T22	10
auto[1]	values[6]	values[2]	647	1			T2	9		T69	16		T202	18
auto[1]	values[6]	values[3]	487	1			T39	10		T49	13		T171	8
auto[1]	values[6]	values[4]	202	1			T184	6		T185	8		T215	31
auto[1]	values[6]	values[5]	215	1			T47	13		T55	9		T56	22
auto[1]	values[6]	values[6]	153	1			T38	36		T49	10		T126	11
auto[1]	values[6]	values[7]	289	1			T47	16		T49	59		T202	12
auto[1]	values[7]	values[0]	240	1			T47	10		T56	6		T19	6
auto[1]	values[7]	values[1]	353	1			T66	10		T186	10		T35	12
auto[1]	values[7]	values[2]	158	1			T48	48		T179	13		T184	9
auto[1]	values[7]	values[3]	357	1			T46	10		T17	8		T219	9
auto[1]	values[7]	values[4]	293	1			T16	51		T126	4		T35	8
auto[1]	values[7]	values[5]	128	1			T39	6		T126	5		T190	21
auto[1]	values[7]	values[6]	111	1			T49	12		T56	13		T84	10
auto[1]	values[7]	values[7]	232	1			T2	10		T24	26		T19	19