Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	469	1			T2	4		T13	2		T51	2
auto[ReadAddrCrossIntoMailbox]	295	1			T13	2		T39	1		T32	1
auto[ReadAddrCrossOutOfMailbox]	323	1			T2	1		T38	1		T70	8
auto[ReadAddrCrossAllMailbox]	248	1			T2	2		T10	2		T13	2
auto[ReadAddrOutsideMailbox]	3559	1			T2	12		T10	2		T13	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T2

8

T10

2

T13

6

auto[1]

2469

1

T2

11

T10

2

T13

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	827	1			T2	3		T10	2		T13	8
read_ops[0x0b]	851	1			T2	1		T14	4		T38	3
read_ops[0x3b]	860	1			T2	4		T38	5		T96	2
read_ops[0x6b]	799	1			T2	4		T51	2		T38	5
read_ops[0xbb]	809	1			T2	4		T10	2		T13	4
read_ops[0xeb]	748	1			T2	3		T24	6		T38	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T70	1		T46	1		T230	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T38	1		T70	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T13	1		T32	1		T46	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T13	1		T16	1		T56	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T70	1		T46	1		T242	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T70	1		T39	1		T242	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T10	1		T13	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T10	1		T13	1		T230	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T13	2		T24	1		T38	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T2	3		T13	2		T24	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T96	1		T46	1		T17	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T96	1		T39	1		T46	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T46	2		T47	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T16	1		T55	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T47	1		T49	1		T55	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T35	2		T227	1		T211	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T49	1		T182	1		T22	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T186	1		T184	1		T22	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T14	2		T45	1		T44	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T2	1		T14	2		T38	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T96	1		T39	1		T19	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T2	1		T96	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T22	1		T35	1		T185	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T39	1		T48	1		T50	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T19	3		T84	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T39	2		T55	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T70	1		T39	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T38	1		T70	1		T47	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T38	1		T45	1		T39	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T2	3		T38	3		T45	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T2	1		T51	1		T32	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T51	1		T47	1		T48	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T47	1		T56	1		T247	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T55	2		T19	1		T247	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T2	1		T38	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T16	1		T182	1		T84	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T55	1		T184	1		T126	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T56	1		T182	1		T22	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T2	1		T38	3		T45	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T2	1		T38	1		T45	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T2	2		T13	1		T32	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T13	1		T230	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T49	1		T56	1		T182	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T49	1		T16	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T70	3		T39	1		T66	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T70	3		T47	1		T19	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T2	1		T46	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T66	1		T56	1		T19	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T2	1		T10	1		T13	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T10	1		T13	1		T23	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T38	1		T96	2		T46	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T96	2		T39	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T47	1		T48	1		T179	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T47	1		T50	1		T55	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T48	1		T55	1		T179	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T49	1		T16	2		T56	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T2	1		T202	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T56	1		T19	4		T182	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T24	3		T45	3		T32	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	266	1			T2	2		T24	3		T38	1