Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3484	1			T3	8		T39	40		T32	24
values[1]	4032	1			T2	40		T10	4		T38	33
values[2]	3996	1			T70	14		T45	20		T39	20
values[3]	4480	1			T13	12		T14	20		T23	6
values[4]	3511	1			T2	20		T51	4		T39	20
values[5]	4491	1			T38	25		T39	20		T46	40
values[6]	3741	1			T2	20		T38	44		T39	20
values[7]	4107	1			T24	26		T38	42		T44	30

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3738	1			T2	20		T10	4		T38	69
values[1]	3251	1			T70	14		T39	40		T46	20
values[2]	4175	1			T2	40		T51	4		T39	20
values[3]	3217	1			T39	20		T32	66		T46	87
values[4]	5238	1			T24	26		T39	20		T41	4
values[5]	3758	1			T3	8		T13	12		T38	33
values[6]	3905	1			T23	6		T38	20		T96	16
values[7]	4560	1			T2	20		T14	20		T38	91

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31120

1

T2

74

T3

8

T10

4

auto[1]

722

1

T2

6

T24

2

T38

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	273	1			T17	20		T186	15		T176	60
auto[0]	values[0]	values[1]	348	1			T47	19		T184	20		T84	49
auto[0]	values[0]	values[2]	548	1			T32	24		T182	37		T176	20
auto[0]	values[0]	values[3]	381	1			T182	19		T197	31		T126	21
auto[0]	values[0]	values[4]	532	1			T39	17		T186	19		T248	14
auto[0]	values[0]	values[5]	346	1			T3	8		T46	21		T49	20
auto[0]	values[0]	values[6]	293	1			T50	20		T228	26		T182	20
auto[0]	values[0]	values[7]	675	1			T39	19		T172	64		T182	20
auto[0]	values[1]	values[0]	602	1			T2	19		T10	4		T204	4
auto[0]	values[1]	values[1]	429	1			T16	21		T182	46		T176	30
auto[0]	values[1]	values[2]	543	1			T2	19		T249	56		T35	97
auto[0]	values[1]	values[3]	393	1			T84	18		T250	14		T22	23
auto[0]	values[1]	values[4]	744	1			T16	20		T56	35		T232	4
auto[0]	values[1]	values[5]	343	1			T38	33		T39	20		T202	20
auto[0]	values[1]	values[6]	363	1			T202	39		T17	20		T22	26
auto[0]	values[1]	values[7]	517	1			T39	17		T243	20		T22	20
auto[0]	values[2]	values[0]	543	1			T48	33		T216	20		T184	20
auto[0]	values[2]	values[1]	327	1			T70	14		T171	20		T179	32
auto[0]	values[2]	values[2]	578	1			T39	20		T193	20		T202	33
auto[0]	values[2]	values[3]	450	1			T47	34		T48	38		T202	22
auto[0]	values[2]	values[4]	486	1			T50	22		T237	2		T16	20
auto[0]	values[2]	values[5]	262	1			T126	21		T185	16		T251	12
auto[0]	values[2]	values[6]	469	1			T45	20		T55	20		T196	10
auto[0]	values[2]	values[7]	781	1			T16	20		T198	20		T22	19
auto[0]	values[3]	values[0]	386	1			T55	21		T202	24		T19	19
auto[0]	values[3]	values[1]	361	1			T126	21		T35	18		T219	20
auto[0]	values[3]	values[2]	377	1			T35	23		T185	20		T252	10
auto[0]	values[3]	values[3]	537	1			T46	67		T49	18		T65	14
auto[0]	values[3]	values[4]	759	1			T41	4		T47	16		T202	20
auto[0]	values[3]	values[5]	445	1			T13	12		T202	25		T17	20
auto[0]	values[3]	values[6]	744	1			T23	6		T38	20		T96	16
auto[0]	values[3]	values[7]	787	1			T14	20		T38	47		T39	20
auto[0]	values[4]	values[0]	428	1			T253	16		T182	40		T254	16
auto[0]	values[4]	values[1]	299	1			T39	20		T46	20		T16	48
auto[0]	values[4]	values[2]	448	1			T51	4		T186	20		T226	2
auto[0]	values[4]	values[3]	317	1			T32	29		T216	20		T211	39
auto[0]	values[4]	values[4]	442	1			T46	20		T47	18		T48	55
auto[0]	values[4]	values[5]	788	1			T32	28		T93	8		T69	14
auto[0]	values[4]	values[6]	254	1			T175	8		T182	18		T255	2
auto[0]	values[4]	values[7]	466	1			T2	18		T47	40		T230	6
auto[0]	values[5]	values[0]	412	1			T38	25		T46	20		T199	8
auto[0]	values[5]	values[1]	559	1			T187	6		T245	4		T182	21
auto[0]	values[5]	values[2]	670	1			T49	60		T56	26		T19	20
auto[0]	values[5]	values[3]	496	1			T49	20		T241	14		T19	23
auto[0]	values[5]	values[4]	729	1			T233	14		T48	20		T50	20
auto[0]	values[5]	values[5]	706	1			T46	20		T159	39		T16	172
auto[0]	values[5]	values[6]	507	1			T39	19		T17	21		T19	31
auto[0]	values[5]	values[7]	295	1			T56	20		T191	12		T256	2
auto[0]	values[6]	values[0]	457	1			T38	41		T17	65		T56	20
auto[0]	values[6]	values[1]	514	1			T49	45		T17	21		T257	4
auto[0]	values[6]	values[2]	479	1			T2	18		T171	25		T19	17
auto[0]	values[6]	values[3]	284	1			T32	37		T171	21		T126	25
auto[0]	values[6]	values[4]	680	1			T32	28		T56	24		T174	18
auto[0]	values[6]	values[5]	421	1			T202	20		T56	29		T22	20
auto[0]	values[6]	values[6]	326	1			T39	18		T98	6		T47	20
auto[0]	values[6]	values[7]	489	1			T16	130		T56	20		T178	6
auto[0]	values[7]	values[0]	557	1			T206	22		T55	45		T194	14
auto[0]	values[7]	values[1]	326	1			T39	20		T242	2		T66	20
auto[0]	values[7]	values[2]	434	1			T16	20		T170	16		T19	49
auto[0]	values[7]	values[3]	284	1			T39	19		T46	20		T236	2
auto[0]	values[7]	values[4]	749	1			T24	24		T16	24		T55	23
auto[0]	values[7]	values[5]	352	1			T55	23		T66	20		T224	2
auto[0]	values[7]	values[6]	867	1			T44	30		T46	40		T17	20
auto[0]	values[7]	values[7]	463	1			T38	41		T190	20		T136	20
auto[1]	values[0]	values[0]	10	1			T186	5		T176	1		T157	1
auto[1]	values[0]	values[1]	11	1			T47	1		T84	5		T219	2
auto[1]	values[0]	values[2]	14	1			T182	3		T176	3		T35	2
auto[1]	values[0]	values[3]	10	1			T182	1		T37	1		T258	1
auto[1]	values[0]	values[4]	18	1			T39	3		T186	1		T157	3
auto[1]	values[0]	values[5]	5	1			T49	1		T259	2		T260	2
auto[1]	values[0]	values[6]	9	1			T84	1		T185	1		T261	3
auto[1]	values[0]	values[7]	11	1			T39	1		T211	2		T215	1
auto[1]	values[1]	values[0]	20	1			T2	1		T49	1		T56	4
auto[1]	values[1]	values[1]	9	1			T211	3		T138	4		T140	1
auto[1]	values[1]	values[2]	14	1			T2	1		T35	3		T246	3
auto[1]	values[1]	values[3]	10	1			T84	2		T211	4		T262	3
auto[1]	values[1]	values[4]	16	1			T56	2		T84	1		T180	2
auto[1]	values[1]	values[5]	8	1			T56	1		T181	4		T263	1
auto[1]	values[1]	values[6]	12	1			T202	1		T22	4		T264	1
auto[1]	values[1]	values[7]	9	1			T39	3		T126	1		T265	1
auto[1]	values[2]	values[0]	6	1			T48	2		T126	1		T266	1
auto[1]	values[2]	values[1]	2	1			T267	1		T268	1		-	-
auto[1]	values[2]	values[2]	25	1			T202	4		T19	2		T157	1
auto[1]	values[2]	values[3]	12	1			T47	6		T269	3		T270	2
auto[1]	values[2]	values[4]	10	1			T35	7		T271	1		T140	1
auto[1]	values[2]	values[5]	14	1			T185	4		T251	4		T189	3
auto[1]	values[2]	values[6]	11	1			T272	2		T273	1		T274	4
auto[1]	values[2]	values[7]	20	1			T198	4		T22	1		T136	3
auto[1]	values[3]	values[0]	7	1			T202	2		T19	1		T185	1
auto[1]	values[3]	values[1]	12	1			T126	2		T35	2		T183	1
auto[1]	values[3]	values[2]	5	1			T275	2		T272	1		T268	2
auto[1]	values[3]	values[3]	14	1			T49	2		T19	2		T271	2
auto[1]	values[3]	values[4]	24	1			T47	4		T202	2		T182	1
auto[1]	values[3]	values[5]	8	1			T202	1		T185	2		T276	3
auto[1]	values[3]	values[6]	6	1			T55	1		T220	1		T276	2
auto[1]	values[3]	values[7]	8	1			T38	2		T49	1		T277	1
auto[1]	values[4]	values[0]	3	1			T276	2		T278	1		-	-
auto[1]	values[4]	values[1]	3	1			T181	1		T262	2		-	-
auto[1]	values[4]	values[2]	14	1			T195	1		T271	1		T275	2
auto[1]	values[4]	values[3]	5	1			T211	1		T138	1		T275	1
auto[1]	values[4]	values[4]	8	1			T47	2		T48	1		T16	1
auto[1]	values[4]	values[5]	15	1			T32	1		T69	2		T190	2
auto[1]	values[4]	values[6]	10	1			T182	2		T255	2		T190	5
auto[1]	values[4]	values[7]	11	1			T2	2		T211	2		T272	1
auto[1]	values[5]	values[0]	10	1			T276	1		T180	1		T279	4
auto[1]	values[5]	values[1]	22	1			T182	2		T277	4		T220	2
auto[1]	values[5]	values[2]	9	1			T49	1		T56	1		T195	1
auto[1]	values[5]	values[3]	14	1			T19	1		T184	2		T22	2
auto[1]	values[5]	values[4]	18	1			T50	2		T17	1		T56	2
auto[1]	values[5]	values[5]	23	1			T16	4		T22	1		T190	4
auto[1]	values[5]	values[6]	12	1			T39	1		T19	1		T35	1
auto[1]	values[5]	values[7]	9	1			T180	3		T280	1		T281	3
auto[1]	values[6]	values[0]	13	1			T38	3		T17	1		T136	1
auto[1]	values[6]	values[1]	22	1			T49	1		T17	1		T37	1
auto[1]	values[6]	values[2]	11	1			T2	2		T171	1		T19	3
auto[1]	values[6]	values[3]	7	1			T126	1		T183	1		T277	1
auto[1]	values[6]	values[4]	9	1			T179	2		T195	1		T282	1
auto[1]	values[6]	values[5]	11	1			T56	2		T190	1		T195	1
auto[1]	values[6]	values[6]	6	1			T39	2		T176	1		T185	1
auto[1]	values[6]	values[7]	12	1			T215	1		T266	1		T283	1
auto[1]	values[7]	values[0]	11	1			T55	1		T271	1		T180	2
auto[1]	values[7]	values[1]	7	1			T17	3		T136	1		T183	3
auto[1]	values[7]	values[2]	6	1			T19	1		T182	2		T284	2
auto[1]	values[7]	values[3]	3	1			T39	1		T19	1		T261	1
auto[1]	values[7]	values[4]	14	1			T24	2		T16	1		T55	1
auto[1]	values[7]	values[5]	11	1			T55	3		T279	1		T285	2
auto[1]	values[7]	values[6]	16	1			T46	1		T56	1		T84	1
auto[1]	values[7]	values[7]	7	1			T38	1		T183	1		T286	1