Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	833	1			T7	10		T12	25		T32	4
all_values[1]	833	1			T7	10		T12	25		T32	4
all_values[2]	833	1			T7	10		T12	25		T32	4
all_values[3]	833	1			T7	10		T12	25		T32	4
all_values[4]	833	1			T7	10		T12	25		T32	4
all_values[5]	833	1			T7	10		T12	25		T32	4
all_values[6]	833	1			T7	10		T12	25		T32	4
all_values[7]	833	1			T7	10		T12	25		T32	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3560

1

T7

42

T12

96

T32

26

auto[1]

3104

1

T7

38

T12

104

T32

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2690

1

T7

34

T12

79

T32

15

auto[1]

3974

1

T7

46

T12

121

T32

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3804

1

T7

46

T12

119

T32

22

auto[1]

2860

1

T7

34

T12

81

T32

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	162	1			T7	5		T12	7		T32	1
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T12	1		T32	2		T16	3
all_values[0]	auto[0]	auto[1]	auto[0]	158	1			T7	2		T12	5		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T12	1		T19	3		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	196	1			T7	2		T12	6		T32	1
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T7	1		T12	5		T16	2
all_values[1]	auto[0]	auto[0]	auto[0]	182	1			T7	4		T12	4		T32	3
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T12	5		T17	1		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T7	2		T12	8		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	82	1			T7	2		T12	1		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	192	1			T7	2		T12	4		T32	1
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T12	3		T16	1		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	195	1			T7	1		T12	10		T16	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T12	1		T17	1		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	132	1			T12	1		T16	3		T17	6
all_values[2]	auto[0]	auto[1]	auto[1]	87	1			T7	1		T12	2		T32	1
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T7	3		T12	6		T32	2
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T7	5		T12	5		T32	1
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T7	1		T12	5		T32	1
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T12	1		T32	1		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	155	1			T12	4		T32	1		T16	1
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T7	4		T12	8		T17	2
all_values[3]	auto[1]	auto[0]	auto[1]	192	1			T7	2		T12	5		T32	1
all_values[3]	auto[1]	auto[1]	auto[1]	166	1			T7	3		T12	2		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T7	2		T12	2		T16	1
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T12	2		T32	2		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	136	1			T7	5		T12	4		T17	1
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T7	1		T12	5		T16	2
all_values[4]	auto[1]	auto[0]	auto[1]	204	1			T7	1		T12	6		T32	2
all_values[4]	auto[1]	auto[1]	auto[1]	162	1			T7	1		T12	6		T16	1
all_values[5]	auto[0]	auto[0]	auto[0]	236	1			T7	1		T12	6		T32	2
all_values[5]	auto[0]	auto[1]	auto[0]	230	1			T7	4		T12	8		T32	1
all_values[5]	auto[1]	auto[0]	auto[1]	208	1			T7	3		T12	4		T32	1
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T7	2		T12	7		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	156	1			T7	4		T12	3		T32	1
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T7	1		T12	3		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	159	1			T7	1		T12	5		T32	1
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T12	5		T17	4		T18	1
all_values[6]	auto[1]	auto[0]	auto[1]	213	1			T7	3		T12	5		T32	1
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T7	1		T12	4		T16	2
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T12	2		T32	3		T17	3
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T7	3		T12	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	160	1			T7	2		T12	5		T32	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T12	3		T17	1		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	202	1			T7	4		T12	6		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	152	1			T7	1		T12	7		T16	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal