Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1893

1

T7

11

T8

5

T25

16

auto[1]

1938

1

T7

11

T8

4

T25

21

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2178

1

T7

22

T8

7

T27

4

auto[1]

1653

1

T8

2

T25

37

T26

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3007

1

T7

14

T8

7

T25

37

auto[1]

824

1

T7

8

T8

2

T30

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	765	1			T7	3		T8	1		T25	4
valid[1]	790	1			T7	3		T8	1		T25	9
valid[2]	782	1			T7	3		T25	10		T26	1
valid[3]	719	1			T7	8		T8	6		T25	4
valid[4]	775	1			T7	5		T8	1		T25	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	125	1			T7	2		T8	1		T32	2
auto[0]	auto[0]	valid[0]	auto[1]	156	1			T25	2		T26	2		T33	4
auto[0]	auto[0]	valid[1]	auto[0]	149	1			T7	1		T27	1		T30	1
auto[0]	auto[0]	valid[1]	auto[1]	152	1			T25	3		T26	1		T33	1
auto[0]	auto[0]	valid[2]	auto[0]	133	1			T32	3		T90	1		T50	3
auto[0]	auto[0]	valid[2]	auto[1]	176	1			T25	3		T26	1		T32	1
auto[0]	auto[0]	valid[3]	auto[0]	124	1			T7	3		T29	1		T30	1
auto[0]	auto[0]	valid[3]	auto[1]	147	1			T8	1		T25	1		T26	2
auto[0]	auto[0]	valid[4]	auto[0]	129	1			T7	1		T8	1		T49	1
auto[0]	auto[0]	valid[4]	auto[1]	166	1			T25	7		T89	1		T91	3
auto[0]	auto[1]	valid[0]	auto[0]	134	1			T7	1		T52	1		T50	2
auto[0]	auto[1]	valid[0]	auto[1]	189	1			T25	2		T26	2		T32	2
auto[0]	auto[1]	valid[1]	auto[0]	130	1			T8	1		T27	1		T32	1
auto[0]	auto[1]	valid[1]	auto[1]	191	1			T25	6		T33	3		T89	3
auto[0]	auto[1]	valid[2]	auto[0]	142	1			T7	1		T27	1		T30	3
auto[0]	auto[1]	valid[2]	auto[1]	168	1			T25	7		T32	1		T33	1
auto[0]	auto[1]	valid[3]	auto[0]	142	1			T7	3		T8	2		T30	1
auto[0]	auto[1]	valid[3]	auto[1]	149	1			T8	1		T25	3		T26	1
auto[0]	auto[1]	valid[4]	auto[0]	146	1			T7	2		T27	1		T30	1
auto[0]	auto[1]	valid[4]	auto[1]	159	1			T25	3		T26	1		T33	1
auto[1]	auto[0]	valid[0]	auto[0]	90	1			T30	2		T52	1		T90	1
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T7	2		T92	2		T303	1
auto[1]	auto[0]	valid[2]	auto[0]	88	1			T7	2		T303	1		T214	1
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T8	2		T30	1		T32	3
auto[1]	auto[0]	valid[4]	auto[0]	93	1			T30	2		T32	1		T50	1
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T92	1		T16	1		T55	1
auto[1]	auto[1]	valid[1]	auto[0]	84	1			T90	1		T50	1		T214	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T90	1		T313	2		T56	2
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T7	2		T90	1		T92	2
auto[1]	auto[1]	valid[4]	auto[0]	82	1			T7	2		T30	3		T32	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal