Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53908

1

T7

490

T8

144

T27

178

auto[1]

18037

1

T8

35

T25

462

T26

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52289

1

T7

335

T8

127

T25

462

auto[1]

19656

1

T7

155

T8

52

T27

47

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36921	1			T7	243		T8	103		T25	245
others[1]	6047	1			T7	37		T8	9		T25	37
others[2]	6060	1			T7	54		T8	17		T25	26
others[3]	6993	1			T7	45		T8	14		T25	47
interest[1]	3994	1			T7	34		T8	8		T25	27
interest[4]	24175	1			T7	163		T8	66		T25	154
interest[64]	11930	1			T7	77		T8	28		T25	80

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17446	1			T7	170		T8	48		T27	65
auto[0]	auto[0]	others[1]	2891	1			T7	26		T8	6		T27	11
auto[0]	auto[0]	others[2]	2882	1			T7	35		T8	10		T27	7
auto[0]	auto[0]	others[3]	3315	1			T7	33		T8	7		T27	14
auto[0]	auto[0]	interest[1]	1927	1			T7	21		T8	6		T27	8
auto[0]	auto[0]	interest[4]	11403	1			T7	112		T8	27		T27	42
auto[0]	auto[0]	interest[64]	5791	1			T7	50		T8	15		T27	26
auto[0]	auto[1]	others[0]	9371	1			T8	24		T25	245		T26	10
auto[0]	auto[1]	others[1]	1479	1			T8	2		T25	37		T32	1
auto[0]	auto[1]	others[2]	1527	1			T8	4		T25	26		T27	2
auto[0]	auto[1]	others[3]	1768	1			T8	1		T25	47		T27	1
auto[0]	auto[1]	interest[1]	1016	1			T25	27		T27	1		T32	1
auto[0]	auto[1]	interest[4]	6304	1			T8	19		T25	154		T26	10
auto[0]	auto[1]	interest[64]	2876	1			T8	4		T25	80		T32	7
auto[1]	auto[0]	others[0]	10104	1			T7	73		T8	31		T27	26
auto[1]	auto[0]	others[1]	1677	1			T7	11		T8	1		T27	3
auto[1]	auto[0]	others[2]	1651	1			T7	19		T8	3		T27	3
auto[1]	auto[0]	others[3]	1910	1			T7	12		T8	6		T27	1
auto[1]	auto[0]	interest[1]	1051	1			T7	13		T8	2		T27	5
auto[1]	auto[0]	interest[4]	6468	1			T7	51		T8	20		T27	16
auto[1]	auto[0]	interest[64]	3263	1			T7	27		T8	9		T27	9

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal