Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2700061	1			T1	1		T3	1		T4	60476
all_values[1]	2700061	1			T1	1		T3	1		T4	60476
all_values[2]	2700061	1			T1	1		T3	1		T4	60476
all_values[3]	2700061	1			T1	1		T3	1		T4	60476
all_values[4]	2700061	1			T1	1		T3	1		T4	60476
all_values[5]	2700061	1			T1	1		T3	1		T4	60476
all_values[6]	2700061	1			T1	1		T3	1		T4	60476
all_values[7]	2700061	1			T1	1		T3	1		T4	60476

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20454342

1

T1

8

T3

8

T4

483808

auto[1]

1146146

1

T14

47

T15

12242

T56

4854

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21573524

1

T1

8

T3

8

T4

483308

auto[1]

26964

1

T4

500

T6

1

T11

195

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2620951	1			T1	1		T3	1		T4	60253
all_values[0]	auto[0]	auto[1]	11949	1			T4	223		T11	79		T26	124
all_values[0]	auto[1]	auto[0]	66353	1			T15	2924		T56	2		T19	5
all_values[0]	auto[1]	auto[1]	808	1			T14	1		T15	135		T56	1
all_values[1]	auto[0]	auto[0]	2504382	1			T1	1		T3	1		T4	60272
all_values[1]	auto[0]	auto[1]	7951	1			T4	204		T11	79		T26	120
all_values[1]	auto[1]	auto[0]	186871	1			T14	3		T15	2935		T56	4
all_values[1]	auto[1]	auto[1]	857	1			T14	1		T15	125		T56	1
all_values[2]	auto[0]	auto[0]	2544169	1			T1	1		T3	1		T4	60403
all_values[2]	auto[0]	auto[1]	3043	1			T4	73		T11	37		T26	42
all_values[2]	auto[1]	auto[0]	152490	1			T14	5		T15	2986		T56	4
all_values[2]	auto[1]	auto[1]	359	1			T14	3		T15	73		T18	1
all_values[3]	auto[0]	auto[0]	2581535	1			T1	1		T3	1		T4	60476
all_values[3]	auto[0]	auto[1]	216	1			T14	5		T56	3		T18	1
all_values[3]	auto[1]	auto[0]	118123	1			T14	3		T15	3060		T18	1
all_values[3]	auto[1]	auto[1]	187	1			T56	6		T18	3		T19	1
all_values[4]	auto[0]	auto[0]	2492287	1			T1	1		T3	1		T4	60476
all_values[4]	auto[0]	auto[1]	221	1			T6	1		T14	2		T15	3
all_values[4]	auto[1]	auto[0]	207364	1			T14	6		T56	2		T18	3
all_values[4]	auto[1]	auto[1]	189	1			T14	1		T15	1		T56	1
all_values[5]	auto[0]	auto[0]	2531218	1			T1	1		T3	1		T4	60476
all_values[5]	auto[0]	auto[1]	163	1			T14	2		T15	1		T56	3
all_values[5]	auto[1]	auto[0]	168483	1			T14	5		T56	2413		T19	7
all_values[5]	auto[1]	auto[1]	197	1			T14	5		T15	1		T56	1
all_values[6]	auto[0]	auto[0]	2587050	1			T1	1		T3	1		T4	60476
all_values[6]	auto[0]	auto[1]	198	1			T14	1		T15	3		T56	1
all_values[6]	auto[1]	auto[0]	112602	1			T14	7		T56	2413		T19	4
all_values[6]	auto[1]	auto[1]	211	1			T14	3		T15	1		T56	2
all_values[7]	auto[0]	auto[0]	2568809	1			T1	1		T3	1		T4	60476
all_values[7]	auto[0]	auto[1]	200	1			T14	3		T56	3		T19	2
all_values[7]	auto[1]	auto[0]	130837	1			T14	3		T15	1		T56	4
all_values[7]	auto[1]	auto[1]	215	1			T14	1		T19	4		T20	4