Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34045	1			T4	181		T8	4		T11	74
auto[SpiFlashAddrCfg]	7663	1			T3	2		T4	58		T6	3
auto[SpiFlashAddr3b]	9042	1			T3	2		T4	99		T6	2
auto[SpiFlashAddr4b]	7464	1			T3	2		T4	45		T7	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33464

1

T3

6

T4

204

T6

5

auto[1]

24750

1

T4

179

T11

84

T29

269

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31547

1

T3

4

T4

233

T6

2

auto[1]

26667

1

T3

2

T4

150

T6

3

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38823	1			T3	2		T4	213		T6	2
values[1]	1096	1			T4	10		T11	1		T37	2
values[2]	1456	1			T4	6		T11	8		T37	2
values[3]	1381	1			T4	14		T11	4		T29	3
values[4]	1421	1			T4	21		T11	4		T37	2
values[5]	1398	1			T4	14		T6	2		T10	2
values[6]	1446	1			T4	10		T7	2		T11	8
values[7]	1430	1			T4	16		T7	1		T11	8
values[8]	9763	1			T3	4		T4	79		T6	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32401

1

T3

6

T4

244

T8

4

auto[1]

25813

1

T4

139

T6

5

T7

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54990

1

T3

6

T4

351

T6

5

write

3224

1

T4

32

T10

4

T11

20

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18747

1

T3

2

T4

159

T6

3

valids[0x1]

39467

1

T3

4

T4

224

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1548	1			T4	11		T11	4		T29	8
internal_process_ops[0x5a]	1572	1			T4	9		T11	4		T29	8
internal_process_ops[0x05]	20711	1			T4	59		T11	16		T29	221
internal_process_ops[0x35]	1496	1			T4	18		T11	5		T29	4
internal_process_ops[0x15]	1513	1			T4	10		T11	11		T37	4
internal_process_ops[0x03]	1087	1			T3	2		T4	10		T6	2
internal_process_ops[0x0b]	1066	1			T4	4		T7	2		T10	2
internal_process_ops[0x3b]	1030	1			T4	12		T6	1		T7	2
internal_process_ops[0x6b]	1061	1			T3	2		T4	9		T6	2
internal_process_ops[0xbb]	1061	1			T4	8		T7	1		T11	4
internal_process_ops[0xeb]	1101	1			T4	12		T11	9		T29	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56630

1

T3

6

T4

367

T6

5

auto[1]

1584

1

T4

16

T11

15

T29

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55972

1

T3

6

T4

363

T6

5

auto[1]

2242

1

T4

20

T11

8

T29

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10682

1

T4

74

T8

4

T11

41

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7147

1

T4

30

T11

26

T29

204

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2122

1

T3

2

T4

16

T11

16

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1879

1

T4

19

T11

12

T29

21

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2607

1

T3

2

T4

29

T10

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2332

1

T4

29

T11

17

T29

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2093

1

T3

2

T4

15

T11

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1838

1

T4

12

T11

13

T29

19

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T11

2

T29

2

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

83

1

T4

1

T11

2

T13

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

105

1

T13

2

T34

2

T30

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T11

3

T13

2

T34

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T29

1

T13

3

T34

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

102

1

T29

2

T13

3

T34

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

105

1

T13

1

T34

1

T35

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

113

1

T4

2

T11

8

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

105

1

T10

4

T13

3

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

114

1

T4

2

T29

1

T38

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

103

1

T4

5

T11

1

T13

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

107

1

T4

2

T11

1

T29

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

112

1

T29

2

T13

2

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

82

1

T4

5

T13

1

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

114

1

T11

2

T29

1

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

122

1

T4

3

T11

1

T29

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9786

1

T4

31

T33

386

T26

61

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5662

1

T4

41

T33

117

T26

28

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1428

1

T4

11

T6

3

T7

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1422

1

T4

5

T33

22

T26

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1726

1

T4

12

T6

2

T7

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1560

1

T4

17

T33

20

T26

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1416

1

T4

5

T7

1

T33

35

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1290

1

T4

5

T33

24

T26

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

76

1

T33

2

T26

1

T15

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T26

1

T15

2

T145

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

97

1

T4

4

T26

1

T146

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

94

1

T33

1

T26

4

T14

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T4

2

T33

4

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

94

1

T4

1

T33

2

T146

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T4

2

T33

2

T26

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

85

1

T33

2

T26

1

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T33

4

T26

2

T146

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T146

4

T14

2

T15

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T4

3

T33

5

T26

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T33

3

T26

1

T147

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T33

5

T26

2

T15

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

82

1

T26

1

T148

3

T149

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

94

1

T32

1

T146

3

T14

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T33

2

T32

1

T14

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3945	1			T4	39		T8	4		T11	30
auto[0]	values[0]	valids[0x1]	16955	1			T3	2		T4	88		T10	4
auto[0]	values[1]	valids[0x1]	550	1			T4	8		T11	1		T37	2
auto[0]	values[2]	valids[0x0]	604	1			T4	2		T11	3		T37	2
auto[0]	values[2]	valids[0x1]	325	1			T4	4		T11	5		T29	2
auto[0]	values[3]	valids[0x0]	499	1			T4	8		T11	3		T29	3
auto[0]	values[3]	valids[0x1]	325	1			T4	6		T11	1		T13	11
auto[0]	values[4]	valids[0x0]	526	1			T4	5		T37	2		T29	2
auto[0]	values[4]	valids[0x1]	325	1			T4	6		T11	4		T29	1
auto[0]	values[5]	valids[0x0]	559	1			T4	5		T11	11		T29	1
auto[0]	values[5]	valids[0x1]	272	1			T4	1		T10	2		T11	5
auto[0]	values[6]	valids[0x0]	521	1			T4	8		T11	4		T29	3
auto[0]	values[6]	valids[0x1]	340	1			T4	2		T11	4		T13	4
auto[0]	values[7]	valids[0x0]	534	1			T4	7		T11	7		T29	3
auto[0]	values[7]	valids[0x1]	320	1			T4	3		T11	1		T29	3
auto[0]	values[8]	valids[0x0]	3605	1			T3	2		T4	37		T11	26
auto[0]	values[8]	valids[0x1]	2196	1			T3	2		T4	15		T11	15
auto[1]	values[0]	valids[0x0]	3532	1			T4	26		T33	57		T26	36
auto[1]	values[0]	valids[0x1]	14391	1			T4	60		T6	2		T7	2
auto[1]	values[1]	valids[0x1]	546	1			T4	2		T33	8		T26	8
auto[1]	values[2]	valids[0x0]	319	1			T33	1		T26	4		T32	1
auto[1]	values[2]	valids[0x1]	208	1			T33	2		T26	1		T32	3
auto[1]	values[3]	valids[0x0]	348	1			T33	4		T26	3		T32	2
auto[1]	values[3]	valids[0x1]	209	1			T33	7		T26	5		T146	1
auto[1]	values[4]	valids[0x0]	352	1			T4	5		T33	7		T26	3
auto[1]	values[4]	valids[0x1]	218	1			T4	5		T33	5		T26	1
auto[1]	values[5]	valids[0x0]	346	1			T4	7		T6	2		T33	8
auto[1]	values[5]	valids[0x1]	221	1			T4	1		T32	1		T14	2
auto[1]	values[6]	valids[0x0]	380	1			T7	2		T33	5		T26	7
auto[1]	values[6]	valids[0x1]	205	1			T33	4		T26	2		T32	2
auto[1]	values[7]	valids[0x0]	334	1			T4	3		T7	1		T33	6
auto[1]	values[7]	valids[0x1]	242	1			T4	3		T33	6		T26	1
auto[1]	values[8]	valids[0x0]	2343	1			T4	7		T6	1		T33	39
auto[1]	values[8]	valids[0x1]	1619	1			T4	20		T33	31		T26	16