Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3527718

1

T1

134

T3

1

T4

27045

auto[1]

29437

1

T4

43

T11

9

T29

216

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147268

1

T1

134

T3

1

T4

97

auto[1]

2409887

1

T4

26991

T11

13004

T37

1024

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	612831	1			T1	2		T3	1		T4	1037
auto[524288:1048575]	438976	1			T4	259		T8	2449		T10	377
auto[1048576:1572863]	393846	1			T4	3174		T6	100		T8	2550
auto[1572864:2097151]	403219	1			T1	129		T4	465		T6	14
auto[2097152:2621439]	490362	1			T1	2		T4	5940		T8	976
auto[2621440:3145727]	427788	1			T4	8449		T6	2		T8	969
auto[3145728:3670015]	381922	1			T1	1		T4	7745		T7	167
auto[3670016:4194303]	408211	1			T4	19		T7	120		T8	992

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443897

1

T1

9

T3

1

T4

27088

auto[1]

1113258

1

T1

125

T6

126

T7

543

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3062936

1

T1

134

T3

1

T4

21583

auto[1]

494219

1

T4

5505

T8

2699

T11

3034

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	207153	1			T1	2		T3	1		T4	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	342685	1			T4	770		T11	1437		T37	1024
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	140254	1			T4	2		T8	1193		T10	377
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	221205	1			T4	256		T11	262		T29	2745
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	131499	1			T4	6		T6	100		T8	2550
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	203441	1			T4	3164		T11	682		T29	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	123591	1			T1	129		T4	15		T6	14
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222507	1			T4	137		T11	2942		T29	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	166028	1			T1	2		T4	11		T8	976
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	258729	1			T4	5926		T29	2		T33	129
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	160534	1			T4	11		T6	2		T8	969
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	207041	1			T4	3502		T11	4391		T33	2932
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95689	1			T1	1		T4	12		T7	167
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	222585	1			T4	7724		T11	256		T29	3099
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	108523	1			T4	4		T7	120		T8	992
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	227360	1			T4	3		T29	5		T33	1955
auto[0]	auto[1]	auto[0:524287]	auto[0]	934	1			T4	2		T26	4		T32	14
auto[0]	auto[1]	auto[0:524287]	auto[1]	57595	1			T4	260		T29	243		T26	133
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2543	1			T4	1		T8	1256		T33	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71239	1			T33	2569		T13	129		T34	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	479	1			T11	1		T33	1		T13	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54719	1			T13	599		T35	3566		T146	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2411	1			T4	4		T8	1441		T33	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	50221	1			T4	300		T29	256		T33	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	530	1			T4	1		T29	1		T33	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	61242	1			T33	1		T13	5415		T39	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1023	1			T4	5		T29	1		T33	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	56886	1			T4	4921		T33	512		T39	758
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1021	1			T4	1		T8	2		T29	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	59469	1			T4	5		T29	1		T33	516
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1356	1			T33	2		T26	2		T32	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	67226	1			T11	3033		T33	1		T32	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	497	1			T4	2		T29	3		T33	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	3547	1			T4	1		T29	19		T33	92
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	350	1			T11	4		T29	2		T33	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2375	1			T11	1		T29	9		T33	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	350	1			T4	2		T11	3		T33	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2839	1			T4	2		T33	32		T13	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	399	1			T4	3		T29	1		T33	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3181	1			T4	2		T33	25		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	343	1			T4	1		T29	2		T33	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2780	1			T4	1		T29	55		T33	54
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	339	1			T4	5		T11	1		T33	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1521	1			T4	4		T33	75		T26	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	365	1			T4	2		T33	2		T13	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2087	1			T4	1		T33	15		T13	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	359	1			T4	3		T29	5		T33	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2780	1			T4	9		T29	96		T33	24
auto[1]	auto[1]	auto[0:524287]	auto[0]	104	1			T26	2		T146	1		T175	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	316	1			T26	1		T146	11		T175	23
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	82	1			T33	1		T13	1		T146	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	928	1			T33	50		T13	12		T146	14
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	80	1			T35	3		T20	1		T69	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	439	1			T35	89		T20	27		T69	26
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	140	1			T4	1		T33	1		T80	10
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	769	1			T4	3		T33	11		T145	69
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	72	1			T33	1		T80	19		T182	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	638	1			T33	2		T80	256		T182	36
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	46	1			T4	1		T62	1		T166	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	398	1			T62	3		T166	4		T70	33
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	92	1			T29	1		T26	1		T148	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	614	1			T29	23		T148	2		T173	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	82	1			T33	1		T30	3		T15	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	525	1			T33	3		T30	22		T15	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1932294	1			T1	9		T3	1		T4	21545
auto[0]	auto[0]	auto[1]	1106530	1			T1	125		T6	126		T7	543
auto[0]	auto[1]	auto[0]	482738	1			T4	5500		T8	10		T11	3034
auto[0]	auto[1]	auto[1]	6156	1			T8	2689		T33	2		T35	3
auto[1]	auto[0]	auto[0]	23655	1			T4	38		T11	9		T29	186
auto[1]	auto[0]	auto[1]	457	1			T29	6		T33	7		T26	1
auto[1]	auto[1]	auto[0]	5210	1			T4	5		T29	23		T33	69
auto[1]	auto[1]	auto[1]	115	1			T29	1		T33	1		T35	1