Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2700061	1			T1	1		T3	1		T4	60476
all_pins[1]	2700061	1			T1	1		T3	1		T4	60476
all_pins[2]	2700061	1			T1	1		T3	1		T4	60476
all_pins[3]	2700061	1			T1	1		T3	1		T4	60476
all_pins[4]	2700061	1			T1	1		T3	1		T4	60476
all_pins[5]	2700061	1			T1	1		T3	1		T4	60476
all_pins[6]	2700061	1			T1	1		T3	1		T4	60476
all_pins[7]	2700061	1			T1	1		T3	1		T4	60476

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21482703	1			T1	8		T3	8		T4	483808
values[0x1]	117785	1			T14	15		T15	351		T56	2754
transitions[0x0=>0x1]	115226	1			T14	10		T15	149		T56	2369
transitions[0x1=>0x0]	115237	1			T14	10		T15	149		T56	2369

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2699186	1			T1	1		T3	1		T4	60476
all_pins[0]	values[0x1]	875	1			T14	1		T15	143		T56	1
all_pins[0]	transitions[0x0=>0x1]	485	1			T14	1		T15	16		T56	1
all_pins[0]	transitions[0x1=>0x0]	542	1			T14	1		T15	3		T56	1
all_pins[1]	values[0x0]	2699129	1			T1	1		T3	1		T4	60476
all_pins[1]	values[0x1]	932	1			T14	1		T15	130		T56	1
all_pins[1]	transitions[0x0=>0x1]	758	1			T15	55		T56	1		T19	1
all_pins[1]	transitions[0x1=>0x0]	198	1			T14	2		T19	5		T20	2
all_pins[2]	values[0x0]	2699689	1			T1	1		T3	1		T4	60476
all_pins[2]	values[0x1]	372	1			T14	3		T15	75		T18	1
all_pins[2]	transitions[0x0=>0x1]	340	1			T14	3		T15	75		T18	1
all_pins[2]	transitions[0x1=>0x0]	155	1			T56	6		T18	3		T131	2
all_pins[3]	values[0x0]	2699874	1			T1	1		T3	1		T4	60476
all_pins[3]	values[0x1]	187	1			T56	6		T18	3		T19	1
all_pins[3]	transitions[0x0=>0x1]	138	1			T56	5		T18	2		T19	1
all_pins[3]	transitions[0x1=>0x0]	140	1			T14	1		T15	1		T19	1
all_pins[4]	values[0x0]	2699872	1			T1	1		T3	1		T4	60476
all_pins[4]	values[0x1]	189	1			T14	1		T15	1		T56	1
all_pins[4]	transitions[0x0=>0x1]	152	1			T15	1		T56	1		T18	1
all_pins[4]	transitions[0x1=>0x0]	2819	1			T14	4		T15	1		T56	391
all_pins[5]	values[0x0]	2697205	1			T1	1		T3	1		T4	60476
all_pins[5]	values[0x1]	2856	1			T14	5		T15	1		T56	391
all_pins[5]	transitions[0x0=>0x1]	1090	1			T14	3		T15	1		T56	7
all_pins[5]	transitions[0x1=>0x0]	110393	1			T14	1		T15	1		T56	1970
all_pins[6]	values[0x0]	2587902	1			T1	1		T3	1		T4	60476
all_pins[6]	values[0x1]	112159	1			T14	3		T15	1		T56	2354
all_pins[6]	transitions[0x0=>0x1]	112100	1			T14	2		T15	1		T56	2354
all_pins[6]	transitions[0x1=>0x0]	156	1			T19	4		T20	4		T21	2
all_pins[7]	values[0x0]	2699846	1			T1	1		T3	1		T4	60476
all_pins[7]	values[0x1]	215	1			T14	1		T19	4		T20	4
all_pins[7]	transitions[0x0=>0x1]	163	1			T14	1		T19	2		T20	1
all_pins[7]	transitions[0x1=>0x0]	834	1			T14	1		T15	143		T56	1