Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18334

1

T3

6

T4

142

T8

4

auto[1]

14067

1

T4

102

T11

84

T29

269

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3712	1			T4	91		T29	47		T13	41
values[1]	3860	1			T4	42		T10	6		T11	40
values[2]	3830	1			T11	22		T29	20		T13	20
values[3]	5105	1			T3	6		T4	51		T11	20
values[4]	3467	1			T4	40		T8	4		T11	63
values[5]	3698	1			T37	16		T29	51		T46	8
values[6]	4760	1			T11	23		T12	6		T29	20
values[7]	3969	1			T4	20		T11	21		T29	47

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3663	1			T4	20		T8	4		T37	16
values[1]	4007	1			T4	25		T11	20		T29	51
values[2]	4097	1			T4	40		T11	20		T12	6
values[3]	3684	1			T10	6		T11	23		T34	109
values[4]	3705	1			T4	47		T11	41		T13	78
values[5]	4275	1			T3	6		T11	41		T29	196
values[6]	4654	1			T4	41		T11	22		T29	20
values[7]	4316	1			T4	71		T11	22		T29	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	385	1			T29	9		T35	88		T40	9
auto[0]	values[0]	values[1]	230	1			T4	14		T13	13		T18	15
auto[0]	values[0]	values[2]	272	1			T207	4		T199	10		T185	11
auto[0]	values[0]	values[3]	235	1			T40	13		T182	16		T208	4
auto[0]	values[0]	values[4]	336	1			T4	5		T40	15		T166	9
auto[0]	values[0]	values[5]	149	1			T13	12		T34	8		T64	14
auto[0]	values[0]	values[6]	242	1			T4	29		T38	14		T41	12
auto[0]	values[0]	values[7]	153	1			T177	13		T209	4		T196	15
auto[0]	values[1]	values[0]	255	1			T13	11		T98	10		T80	12
auto[0]	values[1]	values[1]	139	1			T13	13		T34	12		T40	16
auto[0]	values[1]	values[2]	382	1			T11	15		T175	12		T41	8
auto[0]	values[1]	values[3]	265	1			T10	6		T174	19		T173	12
auto[0]	values[1]	values[4]	291	1			T4	18		T38	30		T62	15
auto[0]	values[1]	values[5]	268	1			T11	12		T29	8		T13	30
auto[0]	values[1]	values[6]	334	1			T29	17		T13	25		T39	56
auto[0]	values[1]	values[7]	231	1			T4	10		T35	11		T191	10
auto[0]	values[2]	values[0]	240	1			T41	9		T210	2		T21	10
auto[0]	values[2]	values[1]	519	1			T175	14		T177	7		T211	6
auto[0]	values[2]	values[2]	288	1			T39	7		T212	10		T80	15
auto[0]	values[2]	values[3]	245	1			T35	13		T66	11		T182	14
auto[0]	values[2]	values[4]	196	1			T13	9		T30	17		T41	11
auto[0]	values[2]	values[5]	251	1			T38	38		T169	12		T189	13
auto[0]	values[2]	values[6]	248	1			T11	12		T30	11		T41	10
auto[0]	values[2]	values[7]	221	1			T29	12		T34	7		T40	10
auto[0]	values[3]	values[0]	337	1			T29	11		T34	20		T30	22
auto[0]	values[3]	values[1]	268	1			T11	14		T40	7		T169	11
auto[0]	values[3]	values[2]	379	1			T4	9		T13	6		T62	9
auto[0]	values[3]	values[3]	473	1			T34	78		T35	18		T175	31
auto[0]	values[3]	values[4]	408	1			T35	11		T41	7		T177	18
auto[0]	values[3]	values[5]	419	1			T3	6		T29	7		T13	100
auto[0]	values[3]	values[6]	298	1			T34	87		T40	27		T205	12
auto[0]	values[3]	values[7]	318	1			T4	27		T185	68		T81	11
auto[0]	values[4]	values[0]	159	1			T8	4		T62	14		T19	13
auto[0]	values[4]	values[1]	209	1			T175	19		T213	6		T169	13
auto[0]	values[4]	values[2]	150	1			T4	10		T30	8		T41	15
auto[0]	values[4]	values[3]	264	1			T80	9		T185	8		T177	15
auto[0]	values[4]	values[4]	275	1			T11	8		T35	15		T68	13
auto[0]	values[4]	values[5]	264	1			T11	8		T38	9		T173	7
auto[0]	values[4]	values[6]	377	1			T13	11		T166	17		T214	16
auto[0]	values[4]	values[7]	383	1			T4	9		T11	10		T193	22
auto[0]	values[5]	values[0]	251	1			T37	16		T35	11		T78	13
auto[0]	values[5]	values[1]	346	1			T29	9		T175	17		T41	11
auto[0]	values[5]	values[2]	234	1			T34	13		T30	35		T173	9
auto[0]	values[5]	values[3]	151	1			T41	26		T66	28		T185	9
auto[0]	values[5]	values[4]	211	1			T34	9		T30	14		T40	8
auto[0]	values[5]	values[5]	228	1			T62	30		T177	12		T196	42
auto[0]	values[5]	values[6]	190	1			T35	11		T215	16		T216	8
auto[0]	values[5]	values[7]	297	1			T173	8		T62	26		T78	13
auto[0]	values[6]	values[0]	271	1			T13	8		T38	13		T41	10
auto[0]	values[6]	values[1]	512	1			T38	18		T175	25		T173	22
auto[0]	values[6]	values[2]	313	1			T12	6		T13	6		T35	18
auto[0]	values[6]	values[3]	321	1			T11	9		T30	66		T175	21
auto[0]	values[6]	values[4]	242	1			T35	9		T39	13		T217	8
auto[0]	values[6]	values[5]	338	1			T13	30		T34	12		T30	14
auto[0]	values[6]	values[6]	345	1			T35	33		T174	19		T177	16
auto[0]	values[6]	values[7]	370	1			T29	14		T38	21		T169	12
auto[0]	values[7]	values[0]	251	1			T4	11		T13	57		T190	13
auto[0]	values[7]	values[1]	216	1			T66	10		T166	13		T185	18
auto[0]	values[7]	values[2]	265	1			T166	18		T200	16		T218	10
auto[0]	values[7]	values[3]	139	1			T34	9		T219	2		T186	8
auto[0]	values[7]	values[4]	281	1			T11	17		T13	34		T35	12
auto[0]	values[7]	values[5]	259	1			T29	40		T40	12		T81	8
auto[0]	values[7]	values[6]	307	1			T13	96		T186	13		T220	63
auto[0]	values[7]	values[7]	640	1			T175	7		T169	8		T19	133
auto[1]	values[0]	values[0]	294	1			T29	38		T35	13		T40	20
auto[1]	values[0]	values[1]	188	1			T4	11		T13	8		T18	84
auto[1]	values[0]	values[2]	225	1			T185	29		T177	5		T19	7
auto[1]	values[0]	values[3]	156	1			T40	7		T182	4		T221	7
auto[1]	values[0]	values[4]	135	1			T4	20		T40	7		T166	13
auto[1]	values[0]	values[5]	448	1			T13	8		T34	17		T166	30
auto[1]	values[0]	values[6]	187	1			T4	12		T38	8		T41	15
auto[1]	values[0]	values[7]	77	1			T177	7		T196	5		T144	5
auto[1]	values[1]	values[0]	169	1			T13	10		T80	8		T169	8
auto[1]	values[1]	values[1]	106	1			T13	7		T34	8		T40	4
auto[1]	values[1]	values[2]	252	1			T11	5		T175	8		T41	12
auto[1]	values[1]	values[3]	145	1			T174	5		T173	8		T138	12
auto[1]	values[1]	values[4]	154	1			T4	4		T38	14		T62	5
auto[1]	values[1]	values[5]	252	1			T11	8		T29	56		T13	30
auto[1]	values[1]	values[6]	329	1			T29	3		T13	27		T39	11
auto[1]	values[1]	values[7]	288	1			T4	10		T35	70		T191	10
auto[1]	values[2]	values[0]	118	1			T41	11		T63	12		T21	15
auto[1]	values[2]	values[1]	179	1			T175	7		T177	24		T19	10
auto[1]	values[2]	values[2]	156	1			T39	13		T80	5		T81	14
auto[1]	values[2]	values[3]	284	1			T35	32		T66	9		T182	18
auto[1]	values[2]	values[4]	161	1			T13	11		T30	3		T41	9
auto[1]	values[2]	values[5]	197	1			T38	23		T169	8		T189	7
auto[1]	values[2]	values[6]	319	1			T11	10		T30	10		T41	10
auto[1]	values[2]	values[7]	208	1			T29	8		T34	18		T40	10
auto[1]	values[3]	values[0]	272	1			T29	31		T34	4		T30	8
auto[1]	values[3]	values[1]	185	1			T11	6		T40	70		T169	16
auto[1]	values[3]	values[2]	240	1			T4	11		T13	14		T62	11
auto[1]	values[3]	values[3]	268	1			T34	10		T35	91		T175	5
auto[1]	values[3]	values[4]	379	1			T35	9		T41	13		T177	7
auto[1]	values[3]	values[5]	270	1			T29	78		T13	19		T80	10
auto[1]	values[3]	values[6]	395	1			T34	19		T40	20		T82	22
auto[1]	values[3]	values[7]	196	1			T4	4		T185	7		T81	9
auto[1]	values[4]	values[0]	201	1			T62	39		T19	109		T222	14
auto[1]	values[4]	values[1]	235	1			T175	10		T169	7		T203	24
auto[1]	values[4]	values[2]	141	1			T4	10		T30	12		T41	8
auto[1]	values[4]	values[3]	205	1			T80	11		T185	12		T177	14
auto[1]	values[4]	values[4]	70	1			T11	12		T35	5		T144	8
auto[1]	values[4]	values[5]	150	1			T11	13		T38	15		T173	18
auto[1]	values[4]	values[6]	183	1			T13	9		T166	3		T178	7
auto[1]	values[4]	values[7]	201	1			T4	11		T11	12		T166	20
auto[1]	values[5]	values[0]	118	1			T35	9		T78	7		T170	13
auto[1]	values[5]	values[1]	147	1			T29	42		T175	3		T41	9
auto[1]	values[5]	values[2]	319	1			T34	7		T30	10		T173	11
auto[1]	values[5]	values[3]	149	1			T41	14		T66	10		T185	35
auto[1]	values[5]	values[4]	173	1			T34	11		T30	6		T40	12
auto[1]	values[5]	values[5]	236	1			T46	8		T62	11		T177	8
auto[1]	values[5]	values[6]	352	1			T35	14		T221	9		T223	21
auto[1]	values[5]	values[7]	296	1			T173	12		T62	9		T224	8
auto[1]	values[6]	values[0]	219	1			T13	12		T38	7		T41	10
auto[1]	values[6]	values[1]	355	1			T38	5		T175	5		T173	11
auto[1]	values[6]	values[2]	264	1			T13	14		T35	2		T175	9
auto[1]	values[6]	values[3]	260	1			T11	14		T30	10		T175	11
auto[1]	values[6]	values[4]	139	1			T35	11		T39	16		T205	9
auto[1]	values[6]	values[5]	268	1			T13	56		T34	8		T30	21
auto[1]	values[6]	values[6]	350	1			T35	8		T174	10		T61	2
auto[1]	values[6]	values[7]	193	1			T29	6		T38	6		T169	8
auto[1]	values[7]	values[0]	123	1			T4	9		T13	4		T190	7
auto[1]	values[7]	values[1]	173	1			T66	40		T166	7		T185	5
auto[1]	values[7]	values[2]	217	1			T166	26		T200	4		T218	10
auto[1]	values[7]	values[3]	124	1			T34	12		T186	12		T182	30
auto[1]	values[7]	values[4]	254	1			T11	4		T13	24		T35	8
auto[1]	values[7]	values[5]	278	1			T29	7		T40	8		T81	12
auto[1]	values[7]	values[6]	198	1			T13	2		T186	7		T225	12
auto[1]	values[7]	values[7]	244	1			T175	45		T169	21		T19	7