Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	460	1			T4	3		T11	6		T29	2
auto[ReadAddrCrossIntoMailbox]	269	1			T4	2		T11	4		T29	2
auto[ReadAddrCrossOutOfMailbox]	282	1			T11	2		T29	5		T13	6
auto[ReadAddrCrossAllMailbox]	194	1			T11	1		T13	5		T34	2
auto[ReadAddrOutsideMailbox]	3718	1			T3	4		T4	39		T10	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2499

1

T3

2

T4

24

T10

1

auto[1]

2424

1

T3

2

T4

20

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	843	1			T3	2		T4	7		T11	5
read_ops[0x0b]	820	1			T4	3		T10	2		T11	8
read_ops[0x3b]	795	1			T4	7		T11	7		T37	2
read_ops[0x6b]	788	1			T3	2		T4	9		T11	5
read_ops[0xbb]	828	1			T4	7		T11	4		T37	2
read_ops[0xeb]	849	1			T4	11		T11	9		T29	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T13	1		T34	2		T138	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T4	2		T39	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T13	1		T38	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T4	1		T29	1		T13	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T13	4		T98	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T29	1		T13	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T13	1		T35	1		T98	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T35	2		T98	1		T39	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T3	1		T4	1		T29	6
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T3	1		T4	3		T11	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T13	1		T34	1		T30	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T13	1		T40	1		T175	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T11	1		T29	1		T13	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T11	1		T175	2		T78	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T29	4		T34	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T30	1		T172	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T190	1		T226	1		T225	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T34	1		T62	1		T182	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T4	2		T10	1		T11	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T4	1		T10	1		T11	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T4	1		T13	1		T34	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T29	2		T13	4		T38	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T11	1		T13	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T11	1		T98	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T11	1		T35	1		T166	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T38	2		T40	1		T178	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T13	1		T98	1		T138	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T13	1		T98	1		T40	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T4	3		T11	4		T37	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T4	3		T37	1		T29	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T11	3		T13	1		T30	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T13	2		T30	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T40	1		T166	1		T186	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T35	1		T30	1		T66	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T38	1		T172	1		T169	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T35	1		T40	2		T80	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T13	1		T186	1		T181	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T11	1		T34	1		T30	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T3	1		T4	8		T29	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T3	1		T4	1		T11	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T11	1		T35	1		T175	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T13	3		T40	1		T175	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T13	1		T39	1		T62	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T34	1		T172	1		T19	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T41	1		T166	1		T177	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T11	1		T66	1		T177	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T38	1		T41	1		T169	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T40	2		T175	2		T200	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T4	3		T11	1		T37	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T4	4		T11	1		T37	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T11	1		T13	1		T34	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T11	1		T13	2		T35	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T4	1		T34	1		T138	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T175	1		T80	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T38	1		T40	2		T169	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T13	1		T30	1		T166	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T38	1		T40	1		T62	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T13	1		T30	1		T40	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	355	1			T4	5		T11	5		T29	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T4	5		T11	2		T13	2