Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3957	1			T4	40		T11	20		T29	98
values[1]	3881	1			T4	20		T11	83		T29	20
values[2]	4136	1			T4	31		T10	6		T11	21
values[3]	4983	1			T4	20		T11	23		T29	85
values[4]	3587	1			T3	6		T4	47		T13	41
values[5]	4355	1			T4	20		T8	4		T46	8
values[6]	3890	1			T4	25		T11	42		T29	173
values[7]	3612	1			T4	41		T12	6		T37	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3969	1			T4	41		T11	20		T29	111
values[1]	5271	1			T3	6		T11	20		T37	16
values[2]	3649	1			T11	21		T29	20		T13	52
values[3]	3940	1			T4	45		T11	23		T46	8
values[4]	3845	1			T4	71		T29	174		T13	145
values[5]	4318	1			T4	87		T8	4		T11	43
values[6]	3974	1			T10	6		T11	20		T12	6
values[7]	3435	1			T11	42		T29	51		T13	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31576

1

T3

6

T4

229

T8

4

auto[1]

825

1

T4

15

T11

15

T29

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	526	1			T11	18		T177	19		T19	87
auto[0]	values[0]	values[1]	508	1			T212	10		T41	20		T169	29
auto[0]	values[0]	values[2]	406	1			T34	19		T175	19		T80	20
auto[0]	values[0]	values[3]	525	1			T35	20		T172	65		T166	25
auto[0]	values[0]	values[4]	709	1			T4	19		T29	47		T13	96
auto[0]	values[0]	values[5]	331	1			T4	20		T13	46		T34	22
auto[0]	values[0]	values[6]	398	1			T13	58		T35	63		T182	19
auto[0]	values[0]	values[7]	456	1			T29	51		T35	20		T80	20
auto[0]	values[1]	values[0]	446	1			T4	17		T13	21		T34	31
auto[0]	values[1]	values[1]	775	1			T41	20		T83	24		T173	20
auto[0]	values[1]	values[2]	368	1			T29	19		T35	25		T227	6
auto[0]	values[1]	values[3]	317	1			T13	20		T40	20		T177	19
auto[0]	values[1]	values[4]	393	1			T35	21		T40	20		T219	2
auto[0]	values[1]	values[5]	564	1			T11	20		T39	20		T66	19
auto[0]	values[1]	values[6]	465	1			T11	17		T13	37		T34	40
auto[0]	values[1]	values[7]	456	1			T11	38		T41	39		T63	12
auto[0]	values[2]	values[0]	436	1			T205	168		T165	20		T228	4
auto[0]	values[2]	values[1]	350	1			T41	20		T177	30		T229	4
auto[0]	values[2]	values[2]	437	1			T11	20		T166	20		T185	18
auto[0]	values[2]	values[3]	771	1			T34	21		T35	81		T40	97
auto[0]	values[2]	values[4]	294	1			T4	29		T173	25		T182	19
auto[0]	values[2]	values[5]	472	1			T38	24		T166	18		T230	4
auto[0]	values[2]	values[6]	602	1			T10	6		T30	64		T62	41
auto[0]	values[2]	values[7]	670	1			T13	19		T175	19		T62	34
auto[0]	values[3]	values[0]	442	1			T38	36		T80	18		T195	6
auto[0]	values[3]	values[1]	1016	1			T13	21		T174	29		T41	20
auto[0]	values[3]	values[2]	610	1			T177	25		T231	20		T232	63
auto[0]	values[3]	values[3]	479	1			T4	20		T11	23		T35	60
auto[0]	values[3]	values[4]	773	1			T29	83		T98	10		T41	20
auto[0]	values[3]	values[5]	623	1			T175	51		T80	20		T66	40
auto[0]	values[3]	values[6]	534	1			T13	20		T169	38		T184	20
auto[0]	values[3]	values[7]	370	1			T38	20		T30	27		T40	20
auto[0]	values[4]	values[0]	475	1			T35	20		T30	39		T41	27
auto[0]	values[4]	values[1]	669	1			T3	6		T40	27		T65	6
auto[0]	values[4]	values[2]	273	1			T40	23		T169	58		T62	20
auto[0]	values[4]	values[3]	378	1			T4	20		T13	21		T30	35
auto[0]	values[4]	values[4]	501	1			T199	10		T191	19		T233	108
auto[0]	values[4]	values[5]	461	1			T4	19		T13	20		T34	75
auto[0]	values[4]	values[6]	500	1			T38	21		T62	24		T78	18
auto[0]	values[4]	values[7]	240	1			T30	20		T182	26		T21	40
auto[0]	values[5]	values[0]	598	1			T13	116		T40	21		T175	32
auto[0]	values[5]	values[1]	752	1			T186	53		T234	10		T18	189
auto[0]	values[5]	values[2]	394	1			T34	21		T175	21		T62	20
auto[0]	values[5]	values[3]	476	1			T46	8		T175	19		T41	20
auto[0]	values[5]	values[4]	366	1			T13	20		T38	23		T41	20
auto[0]	values[5]	values[5]	684	1			T4	19		T8	4		T38	41
auto[0]	values[5]	values[6]	590	1			T80	19		T173	20		T61	2
auto[0]	values[5]	values[7]	402	1			T207	4		T191	40		T21	69
auto[0]	values[6]	values[0]	488	1			T29	108		T13	20		T40	77
auto[0]	values[6]	values[1]	679	1			T11	20		T13	20		T34	19
auto[0]	values[6]	values[2]	616	1			T13	51		T38	22		T35	86
auto[0]	values[6]	values[3]	379	1			T13	29		T35	41		T41	20
auto[0]	values[6]	values[4]	365	1			T29	40		T189	20		T194	12
auto[0]	values[6]	values[5]	561	1			T4	25		T11	18		T29	19
auto[0]	values[6]	values[6]	332	1			T66	50		T191	20		T21	21
auto[0]	values[6]	values[7]	367	1			T40	23		T174	24		T166	22
auto[0]	values[7]	values[0]	463	1			T4	21		T13	20		T35	40
auto[0]	values[7]	values[1]	410	1			T37	16		T35	18		T30	37
auto[0]	values[7]	values[2]	449	1			T235	6		T186	19		T182	41
auto[0]	values[7]	values[3]	500	1			T62	20		T205	20		T236	2
auto[0]	values[7]	values[4]	342	1			T4	20		T13	26		T30	20
auto[0]	values[7]	values[5]	526	1			T29	20		T13	17		T68	13
auto[0]	values[7]	values[6]	444	1			T12	6		T82	22		T173	18
auto[0]	values[7]	values[7]	374	1			T34	24		T30	20		T41	22
auto[1]	values[0]	values[0]	7	1			T11	2		T177	1		T21	1
auto[1]	values[0]	values[1]	15	1			T41	3		T178	2		T233	1
auto[1]	values[0]	values[2]	18	1			T34	1		T175	1		T237	6
auto[1]	values[0]	values[3]	8	1			T166	2		T233	2		T144	2
auto[1]	values[0]	values[4]	15	1			T4	1		T13	2		T138	2
auto[1]	values[0]	values[5]	8	1			T34	3		T238	1		T239	1
auto[1]	values[0]	values[6]	15	1			T13	3		T35	2		T182	3
auto[1]	values[0]	values[7]	12	1			T166	1		T19	2		T232	3
auto[1]	values[1]	values[0]	15	1			T4	3		T39	2		T173	1
auto[1]	values[1]	values[1]	9	1			T185	1		T188	2		T133	2
auto[1]	values[1]	values[2]	9	1			T29	1		T184	1		T240	2
auto[1]	values[1]	values[3]	10	1			T177	1		T186	1		T191	2
auto[1]	values[1]	values[4]	12	1			T35	1		T18	2		T188	2
auto[1]	values[1]	values[5]	9	1			T11	1		T66	1		T233	2
auto[1]	values[1]	values[6]	15	1			T11	3		T13	3		T241	2
auto[1]	values[1]	values[7]	18	1			T11	4		T41	1		T182	3
auto[1]	values[2]	values[0]	3	1			T205	2		T242	1		-	-
auto[1]	values[2]	values[1]	13	1			T177	1		T229	2		T232	2
auto[1]	values[2]	values[2]	13	1			T11	1		T185	2		T184	3
auto[1]	values[2]	values[3]	23	1			T66	1		T189	2		T19	1
auto[1]	values[2]	values[4]	11	1			T4	2		T182	1		T239	2
auto[1]	values[2]	values[5]	15	1			T38	3		T166	2		T78	3
auto[1]	values[2]	values[6]	11	1			T30	2		T166	2		T197	2
auto[1]	values[2]	values[7]	15	1			T13	1		T175	1		T62	1
auto[1]	values[3]	values[0]	24	1			T38	1		T80	2		T172	1
auto[1]	values[3]	values[1]	23	1			T62	3		T19	2		T170	1
auto[1]	values[3]	values[2]	12	1			T243	3		T244	2		T245	1
auto[1]	values[3]	values[3]	10	1			T35	1		T226	1		T246	1
auto[1]	values[3]	values[4]	22	1			T29	2		T66	5		T181	2
auto[1]	values[3]	values[5]	12	1			T175	1		T66	1		T196	2
auto[1]	values[3]	values[6]	19	1			T169	2		T19	1		T226	1
auto[1]	values[3]	values[7]	14	1			T30	3		T62	2		T144	1
auto[1]	values[4]	values[0]	9	1			T41	2		T188	1		T246	1
auto[1]	values[4]	values[1]	15	1			T40	2		T247	4		T221	1
auto[1]	values[4]	values[2]	7	1			T169	1		T62	1		T166	1
auto[1]	values[4]	values[3]	20	1			T4	5		T39	1		T41	4
auto[1]	values[4]	values[4]	6	1			T191	1		T233	1		T188	1
auto[1]	values[4]	values[5]	11	1			T4	3		T178	1		T181	1
auto[1]	values[4]	values[6]	17	1			T38	2		T78	2		T181	1
auto[1]	values[4]	values[7]	5	1			T182	1		T248	1		T249	3
auto[1]	values[5]	values[0]	16	1			T13	2		T40	1		T169	3
auto[1]	values[5]	values[1]	15	1			T18	4		T238	1		T188	1
auto[1]	values[5]	values[2]	9	1			T34	3		T175	1		T190	1
auto[1]	values[5]	values[3]	4	1			T175	1		T250	2		T251	1
auto[1]	values[5]	values[4]	12	1			T38	1		T222	3		T188	4
auto[1]	values[5]	values[5]	9	1			T4	1		T38	3		T252	1
auto[1]	values[5]	values[6]	15	1			T80	1		T233	2		T143	2
auto[1]	values[5]	values[7]	13	1			T21	2		T221	2		T188	1
auto[1]	values[6]	values[0]	9	1			T29	3		T40	1		T175	1
auto[1]	values[6]	values[1]	11	1			T34	1		T40	2		T166	1
auto[1]	values[6]	values[2]	12	1			T13	1		T35	1		T175	1
auto[1]	values[6]	values[3]	27	1			T13	2		T221	1		T226	5
auto[1]	values[6]	values[4]	11	1			T29	2		T231	1		T21	1
auto[1]	values[6]	values[5]	16	1			T11	4		T29	1		T185	1
auto[1]	values[6]	values[6]	7	1			T21	1		T253	3		T254	2
auto[1]	values[6]	values[7]	10	1			T40	1		T166	2		T171	1
auto[1]	values[7]	values[0]	12	1			T186	1		T233	2		T181	2
auto[1]	values[7]	values[1]	11	1			T35	2		T39	2		T174	2
auto[1]	values[7]	values[2]	16	1			T186	1		T182	1		T231	1
auto[1]	values[7]	values[3]	13	1			T223	4		T225	1		T188	2
auto[1]	values[7]	values[4]	13	1			T13	1		T144	2		T242	2
auto[1]	values[7]	values[5]	16	1			T13	3		T205	1		T178	2
auto[1]	values[7]	values[6]	10	1			T173	2		T222	1		T188	2
auto[1]	values[7]	values[7]	13	1			T34	1		T184	1		T255	2