Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	887	1			T14	10		T15	4		T56	10
all_values[1]	887	1			T14	10		T15	4		T56	10
all_values[2]	887	1			T14	10		T15	4		T56	10
all_values[3]	887	1			T14	10		T15	4		T56	10
all_values[4]	887	1			T14	10		T15	4		T56	10
all_values[5]	887	1			T14	10		T15	4		T56	10
all_values[6]	887	1			T14	10		T15	4		T56	10
all_values[7]	887	1			T14	10		T15	4		T56	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3749

1

T14

41

T15

20

T56

39

auto[1]

3347

1

T14

39

T15

12

T56

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2952

1

T14

33

T15

17

T56

35

auto[1]

4144

1

T14

47

T15

15

T56

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4108

1

T14

47

T15

21

T56

47

auto[1]

2988

1

T14

33

T15

11

T56

33

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	186	1			T14	3		T15	1		T18	1
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T14	3		T56	3		T18	1
all_values[0]	auto[0]	auto[1]	auto[0]	159	1			T15	2		T56	3		T19	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T14	1		T19	6		T20	1
all_values[0]	auto[1]	auto[0]	auto[1]	223	1			T14	3		T15	1		T56	3
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T56	1		T18	2		T19	4
all_values[1]	auto[0]	auto[0]	auto[0]	178	1			T15	1		T56	3		T18	2
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T14	3		T18	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	161	1			T14	2		T56	2		T19	4
all_values[1]	auto[0]	auto[1]	auto[1]	94	1			T14	1		T15	1		T56	1
all_values[1]	auto[1]	auto[0]	auto[1]	187	1			T14	2		T15	1		T19	4
all_values[1]	auto[1]	auto[1]	auto[1]	185	1			T14	2		T15	1		T56	4
all_values[2]	auto[0]	auto[0]	auto[0]	209	1			T14	3		T15	2		T56	1
all_values[2]	auto[0]	auto[0]	auto[1]	85	1			T14	1		T56	1		T18	2
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T14	1		T15	2		T56	4
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T14	2		T19	4		T20	2
all_values[2]	auto[1]	auto[0]	auto[1]	188	1			T14	1		T56	2		T18	1
all_values[2]	auto[1]	auto[1]	auto[1]	182	1			T14	2		T56	2		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	196	1			T14	3		T15	2		T19	6
all_values[3]	auto[0]	auto[0]	auto[1]	90	1			T14	1		T56	2		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	159	1			T14	1		T15	1		T19	2
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T18	1		T20	1		T131	2
all_values[3]	auto[1]	auto[0]	auto[1]	204	1			T14	4		T56	2		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	167	1			T14	1		T15	1		T56	6
all_values[4]	auto[0]	auto[0]	auto[0]	183	1			T14	2		T56	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	103	1			T14	1		T15	1		T56	3
all_values[4]	auto[0]	auto[1]	auto[0]	183	1			T14	5		T56	1		T18	2
all_values[4]	auto[0]	auto[1]	auto[1]	70	1			T131	2		T142	1		T143	1
all_values[4]	auto[1]	auto[0]	auto[1]	182	1			T14	1		T15	1		T56	3
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T14	1		T15	2		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	270	1			T15	2		T56	2		T18	2
all_values[5]	auto[0]	auto[1]	auto[0]	257	1			T14	3		T56	4		T19	7
all_values[5]	auto[1]	auto[0]	auto[1]	185	1			T14	1		T15	2		T56	2
all_values[5]	auto[1]	auto[1]	auto[1]	175	1			T14	6		T56	2		T19	4
all_values[6]	auto[0]	auto[0]	auto[0]	187	1			T56	1		T18	1		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T15	2		T18	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T14	5		T56	5		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T56	1		T20	1		T131	5
all_values[6]	auto[1]	auto[0]	auto[1]	202	1			T14	1		T56	2		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	169	1			T14	4		T15	2		T56	1
all_values[7]	auto[0]	auto[0]	auto[0]	169	1			T14	4		T15	4		T56	3
all_values[7]	auto[0]	auto[0]	auto[1]	63	1			T14	1		T56	1		T144	1
all_values[7]	auto[0]	auto[1]	auto[0]	156	1			T14	1		T56	3		T18	3
all_values[7]	auto[0]	auto[1]	auto[1]	94	1			T19	2		T20	2		T21	1
all_values[7]	auto[1]	auto[0]	auto[1]	220	1			T14	3		T56	2		T19	5
all_values[7]	auto[1]	auto[1]	auto[1]	185	1			T14	1		T56	1		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal