Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1738

1

T4

11

T5

7

T9

7

auto[1]

1712

1

T4

17

T5

4

T9

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1877

1

T4

24

T11

5

T26

7

auto[1]

1573

1

T4

4

T5

11

T9

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2720

1

T4

22

T5

11

T9

13

auto[1]

730

1

T4

6

T11

2

T26

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	685	1			T4	7		T5	2		T9	5
valid[1]	681	1			T4	2		T5	1		T9	4
valid[2]	682	1			T4	4		T5	1		T9	2
valid[3]	670	1			T4	6		T5	1		T11	2
valid[4]	732	1			T4	9		T5	6		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	145	1			T4	2		T27	1		T13	1
auto[0]	auto[0]	valid[0]	auto[1]	138	1			T4	1		T5	2		T9	2
auto[0]	auto[0]	valid[1]	auto[0]	98	1			T26	2		T28	2		T175	2
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T9	4		T11	1		T24	5
auto[0]	auto[0]	valid[2]	auto[0]	109	1			T4	1		T13	1		T34	1
auto[0]	auto[0]	valid[2]	auto[1]	149	1			T4	1		T24	4		T25	2
auto[0]	auto[0]	valid[3]	auto[0]	107	1			T34	1		T35	1		T40	1
auto[0]	auto[0]	valid[3]	auto[1]	142	1			T4	1		T24	2		T26	1
auto[0]	auto[0]	valid[4]	auto[0]	132	1			T4	4		T11	1		T34	1
auto[0]	auto[0]	valid[4]	auto[1]	178	1			T5	5		T9	1		T24	1
auto[0]	auto[1]	valid[0]	auto[0]	114	1			T4	3		T26	1		T13	1
auto[0]	auto[1]	valid[0]	auto[1]	142	1			T9	3		T24	4		T26	1
auto[0]	auto[1]	valid[1]	auto[0]	114	1			T4	1		T11	1		T34	1
auto[0]	auto[1]	valid[1]	auto[1]	154	1			T5	1		T24	3		T25	1
auto[0]	auto[1]	valid[2]	auto[0]	105	1			T4	2		T28	1		T38	2
auto[0]	auto[1]	valid[2]	auto[1]	168	1			T5	1		T9	2		T25	3
auto[0]	auto[1]	valid[3]	auto[0]	108	1			T4	3		T41	1		T173	2
auto[0]	auto[1]	valid[3]	auto[1]	168	1			T5	1		T24	2		T26	1
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T4	2		T11	1		T26	1
auto[0]	auto[1]	valid[4]	auto[1]	169	1			T4	1		T5	1		T9	1
auto[1]	auto[0]	valid[0]	auto[0]	81	1			T26	1		T27	1		T13	1
auto[1]	auto[0]	valid[1]	auto[0]	86	1			T27	1		T28	2		T13	3
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T13	1		T38	1		T40	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T30	3		T175	2		T62	1
auto[1]	auto[0]	valid[4]	auto[0]	63	1			T4	1		T13	2		T41	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T4	1		T26	1		T28	1
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T4	1		T30	2		T173	1
auto[1]	auto[1]	valid[2]	auto[0]	80	1			T26	1		T28	1		T13	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T4	2		T11	2		T175	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T4	1		T13	2		T40	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal